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Half Cycle Paths2

Half Cycle Paths occur when data is launched at one clock edge and captured at the opposite edge, resulting in tighter setup and hold checks. The document outlines scenarios for Half Cycle Paths and provides specific timing problems with parameters for analysis. Each scenario illustrates the impact of timing on data transfer between flip-flops in digital circuits.

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260 views6 pages

Half Cycle Paths2

Half Cycle Paths occur when data is launched at one clock edge and captured at the opposite edge, resulting in tighter setup and hold checks. The document outlines scenarios for Half Cycle Paths and provides specific timing problems with parameters for analysis. Each scenario illustrates the impact of timing on data transfer between flip-flops in digital circuits.

Uploaded by

mbalaji00000
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Half Cycle Paths

Half cycle paths:


• The Launch Edge and the Capture Edge are either Positive or
Negative and it is known as Single Cycle-Path.
• But there are scenarios when Data is Launched at Positive Edge
and Captured at Negative Edge and vice versa such cases form
a Half Cycle-Path.
• In other words, when Setup Checks occur at Half Cycle it is
known as Half Cycle-Path
Scenarios for occur Half cycle paths:
1. Data Launched from Positive Edge Triggered Flip-Flop and Captured at
Negative Edge Triggered Flip-Flop.
2. Data Launched from a Negative Edge Triggered Flip-Flop and Captured at
Positive Edge Triggered Flip-Flop
Let us one Scenario :

Fig 1: Half cycle Path

• Let us consider the above Fig. 1 and Fig. 2 in which Data is Launched at the Negative Edge from the Launch Flop
and Captured at the Positive Edge at the Capture Flop.
• Let us take a Time-Period of 20ns, in which the Falling Edge is at 10ns and the Rising Edge is at 20ns. Since it is
a Half Cycle Path, the Data Launched at 10ns should be Captured at 20ns. Thus, Data gets 10ns to travel from
the Launch Flop to the Capture Flop instead of 20ns.
• This makes the Setup Check tighter. Since the Hold Check takes place one cycle before the Capture Edge, the
Hold Check takes place at 0ns. It gives a complete Half Cycle Margin to the Hold Check and thus makes Hold
Slack more Positive
• In case of a Half Cycle Path, the Setup equation modifies to:

• For Hold the equation is:

For 2nd Scenario :


Problem :1
Buf : 1ns ; clk - q delay : 0.9ns ; combo delay: 3ns
Tse: 0.5ns ; Th: 0.3ns ; Time period: 5ns ;clock uncertainty: 0.4
Problem :2
Buf : 0.5ns ; clk - q delay : 0.7ns ; combo delay: 2.2ns
Tse: 0.4ns ; Th: 0.2ns ; Time period: 4ns ;clock uncertainty: 0.35
Problem :3
Buf1X1 : 1ns ; clk - q delay : 0.7ns ; combo delay: 2.5ns
Tse: 0.5ns ; Th: 0.3ns ; Time period: 4ns ;
buf1x1
Clock uncertainty: 0.2ns; buf2X1:1.5ns
Problem :4 buf2x1
Buf1X1: 0.7ns ; clk - q delay : 0.5ns ; combo delay: 3ns
Tse: 0.5ns ; Th: 0.3ns ; Time period: 5ns ;clock uncertainty: 0.2
Buf2X1: 1.5ns
Problem :5
Buf : 1ns ; clk - q delay : 0.9ns ; combo delay: 1.5ns
Tse: 0.5ns ; Th: 0.3ns ; Time period: 3ns ;clock uncertainty: 0.4

Problem :6
Buf : 0.7ns ; clk - q delay : 0.5ns ; combo delay: 1ns
Tse: 0.5ns ; Th: 0.3ns ; Time period: 3ns ;clock uncertainty: 0.2

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