12-1

ADDRESSING MODES
Addressing Modes:

* Specifies a rule for interpreting or modifying the

address field of the instruction (before the operand
is actually referenced)

* Variety of addressing modes

- to give programming flexibility to the user

- to use the bits in the address field of the
instruction efficiently
 Addressing Modes 12-2

Types of Addressing Modes (AM):

1.Implied AM
2.Immediate AM
3.Direct AM
4.Indirect AM
5.Register AM
6.Register Indirect AM
7.Displacement AM
(a)Relative (b) Base Register (BR) (c) Index (XR)
8.Auto-Increment AM
9.Auto-Decrement AM
 Implied Addressing 12-3

Implied Mode
 Address of the operands are specified implicitly

in the instruction
 - No need to specify address in the instruction
 - Ex: CMA(Complement the accumulator)
CLA
 Immediate Addressing 12-4

 Operand is part of instruction

 Operand = address field
 e.g. ADD 5, LOAD R1, #1000
 Add 5 to contents of accumulator
 5 is operand
 Load data (1000) in register R1
• No memory reference to fetch data
• Fast
• Limited range Instruction
Opcode Operand
 Direct Addressing 12-5

 Address field contains address of operand

 Effective address (EA) = address field (A)
 e.g. ADD 500, LOAD R1, 500
 Add contents of memory location (memory word) 500 to
accumulator
 Load R1 with the content of Memory word (Memory
Location) 500
 Look in memory at address 500 for operand
 Single memory reference to access data
 No additional calculations to work out effective address
 Limited address space
 Direct Addressing Diagram 12-6

Instruction
Opcode Address A
Memory

Operand
 Indirect Addressing (1) 12-7

 Memory word pointed to by address field contains the

address of (pointer to) the operand
 EA = (A)
 Look in A, find address (A) and look there for
operand
 e.g. ADD (A), LOAD R1, (500)
 Add contents of Memory word pointed to by contents
of Address field of the instruction to Accumulator.
 Indirect Addressing Diagram 12-8

Opcode Address A
Memory
Instruction
Pointer to operand

Operand
 Register Addressing 12-9

 Operand is held in register named in address filed

 EA = R
 LOAD R1, R2
 Limited number of registers
 Very small address field needed
 Shorter instructions
 Faster instruction fetch
 Register Addressing Diagram 12-10

Instruction
Opcode Register Address R
Set of Registers

Operand
 Register Indirect Addressing 12-11

 Instruction specifies a register which contains the memory address

of the operand
 EA = (R)
 Operand is in memory cell pointed to by contents of register R
 Large address space (2n)
 Register Indirect Addressing Diagram 12-12

Instruction
Opcode Register Address R
Memory

Registers

Pointer to Operand Operand

 Displacement Addressing Mode 12-13

 EA = PC + IR (address)
(a) Relative AM
(b) Base Register (BR) Instruction
(c) Index (XR) Address Field

(a) The address fields R A

of an instruction
specifies the part of the Memory
address (abbreviated
address) which can be
used along with a PC to Operand
calculate the address of R
the operand.
Set of Registers
 Displacement Addressing Mode 12-14

(c) An index register (XR) in a computer’s CPU is a

processor register (or an assigned memory location) used
(b) Base Address for pointing to operand addresses during the run of a
program. It is useful for stepping through strings and
Register (BAR) AM arrays. It can also be used for holding loop iterations and
counters.
EA = XR + IR (address)

EA = BAR + IR (address)

EA = PC + IR (address)
 Auto-Incr. & Auto-Decr.Addressing Mode 12-15

Auto-Increment AM Auto-Decrement AM

Same as the Register Indirect, but when the

address in the register is used to access memory,
the value in the register is decremented before
Same as the Register Indirect, the execution of the instruction.
but when the address in the
register is used to access
memory, the value in the
register is incremented after the
execution of the instruction.
 Numerical on Addressing Mode 12-16

P1: An instruction is stored at location 300 with its address field at

location 301. The address field has the value 400. A processor
register R1 contains the number 200. Evaluate the effective address
(EA) if the addressing mode of the instruction is:
Direct, Immediate, Relative, Register Indirect, Index with R1 as the
index register.
 Numerical on Addressing Mode 12-17

P1: An instruction is stored at location 300 with its address field at

location 301. The address field has the value 400. A processor
register R1 contains the number 200. Evaluate the effective address
(EA) if the addressing mode of the instruction is:
Direct, Immediate, Relative, Register Indirect, Index with R1 as the
index register. Memory
300 Instruction
301 Address =400
Sol: (a) Direct; EA = 400
302 Next Instruction
(b) Immediate; EA = 301
(c) Relative; EA = PC+A = 302 + 400 = 702
(d) Register Indirect; EA = 200 400 Operand
(e) Index; EA = XR+A = 200 + 400 = 600

...
 Numerical on Addressing Mode 12-18

P2: A two-word instruction is stored in memory at an address

designated by the symbol W. The address field of the
instruction(stored at W+1) is designated by the symbol Y. The
operand used during the execution of the instruction is stored at an
address symbolized by Z. An index register contains the value X.
State how Z is calculated from the other addresses if the addressing
mode of the instruction is:
Direct, Indirect, Relative, Indexed.
 Numerical on Addressing Mode 12-19

P2: A two-word instruction is stored in memory at an address

designated by the symbol W. The address field of the
instruction(stored at W+1) is designated by the symbol Y. The
operand used during the execution of the instruction is stored at an
address symbolized by Z. An index register contains the value X.
State how Z is calculated from the other addresses if the addressing
mode of the instruction is:
Direct, Indirect, Relative, Indexed. address Memory
W Instruction
Sol:
W+1 Address = Y
(a) Direct; Z = Y W+2 Next Instruction
PC = W

(b) Indirect; Z = M[Y] XR = X

(c) Relative; Z= PC+A = W + 2 + Y
(d) Immediate; Z = W+1 Y M[Y]

(e) Index; Z = XR+A = X + Y Z Operand

...
 Numerical on Addressing Mode 12-20

P3: To show the differences between the various modes, here shows
the effect of the addressing modes on the instruction defined in the
figure given below. The two-word instruction at address 200 and 201
is “Load to Accumulator (AC)” instruction with an address field
equal to 500. PC has the value 200 for fetching this instruction. The
content of processor register R1 is 400, and the content of an index
register XR is 100. AC receives the operand after the instruction is
executed.
 Numerical on Addressing Mode 12-21

Memory
200 Load to AC Mode
201 Address = 500
202 Next Instruction
Addressing Modes Effective Content of AC
Address (EA) PC = 200
Direct Address 399 450
400 700
Immediate Operand R1 = 400
Indirect Address
500 800
Relative Address XR = 100
Indexed Address
600 900
Register AC
Register Indirect 702 325
Auto-Increment

Auto-Decrement

800 300
 Numerical on Addressing Mode 12-22

The Table lists the value of the effective address (EA) and the
operand loaded into AC for the nine addressing modes
Addressing Effective Content of AC
Modes Address (EA)
Direct Address 500 800
Immediate Operand 201 500
Indirect Address 800 300
Relative Address 702 325
Indexed Address 600 900
Register - 400
Register Indirect 400 700
Auto-Increment 400 700
Auto-Decrement 399 450
Typical Data Transfer Instructions 12-23

Name Mnemonic

Load LD

Store ST

Move MOV

Exchange XCH

Input IN

Output OUT

Push PUSH

Pop POP
Eight Addressing Modes for the Load 12-24
Instructions
Mode Assembly Convention Register Transfer

LD ADR AC ← M[ADR]

LD @ADR AC ← M[M[ADR]]

LD $ADR AC ← M[PC + ADR]

LD #NBR AC ← NBR

LD ADR(X) AC ← M[ADR + XR]

LD R1 AC ← R1

LD (R1) AC ← M[R1]

LD (R1) + AC ← M[R1], R1 ← R1+1

 Eight Addressing Modes for the Load 12-25
Instructions
Mode Assembly Convention Register Transfer

Direct Address LD ADR AC ← M[ADR]

Indirect Address LD @ADR AC ← M[M[ADR]]

Relative Address LD $ADR AC ← M[PC + ADR]

Immediate Operand LD #NBR AC ← NBR

Index Addressing LD ADR(X) AC ← M[ADR + XR]

Register LD R1 AC ← R1

Register Indirect LD (R1) AC ← M[R1]

Autoincrement LD (R1) + AC ← M[R1], R1 ← R1+1

 12-26

ADR Stands for an address

NBR is a number or operand

X is an index register

R1 is a processor register

AC is the accumulator register

@ Character symbolizes an indirect address

$ Character before an address makes the address relative to the

Program Counter (PC)
# Character precedes the operand in an immediate mode instructions.