This document contains a pipelined example of an instruction sequence and its execution over multiple clock cycles in a 5-stage pipeline processor. It shows the lw, sw, add, and sub instructions moving through the fetch, decode, execute, memory, and writeback stages. In each clock cycle, a new instruction enters the pipeline and older instructions progress to subsequent stages. This achieves overlapped execution of multiple instructions to improve processor throughput.
This document contains a pipelined example of an instruction sequence and its execution over multiple clock cycles in a 5-stage pipeline processor. It shows the lw, sw, add, and sub instructions moving through the fetch, decode, execute, memory, and writeback stages. In each clock cycle, a new instruction enters the pipeline and older instructions progress to subsequent stages. This achieves overlapped execution of multiple instructions to improve processor throughput.
This document contains a pipelined example of an instruction sequence and its execution over multiple clock cycles in a 5-stage pipeline processor. It shows the lw, sw, add, and sub instructions moving through the fetch, decode, execute, memory, and writeback stages. In each clock cycle, a new instruction enters the pipeline and older instructions progress to subsequent stages. This achieves overlapped execution of multiple instructions to improve processor throughput.
This document contains a pipelined example of an instruction sequence and its execution over multiple clock cycles in a 5-stage pipeline processor. It shows the lw, sw, add, and sub instructions moving through the fetch, decode, execute, memory, and writeback stages. In each clock cycle, a new instruction enters the pipeline and older instructions progress to subsequent stages. This achieves overlapped execution of multiple instructions to improve processor throughput.
ADD ADD 4 <<2 PC ADDR RD RN1 RD1 32 5 ALU Zero Instruction RN2 5 Memory Register WN File 5 RD2 M WD U ADDR X Data Memory RD M E U 16 X 32 X T WD N 5 D Single-Clock-Cycle Diagram: SW Clock Cycle 2 LW
IF/ID ID/EX EX/MEM MEM/WB
ADD ADD 4 <<2 PC ADDR RD RN1 RD1 32 5 ALU Zero Instruction RN2 5 Memory Register WN File 5 RD2 M WD U ADDR X Data Memory RD M E U 16 X 32 X T WD N 5 D Single-Clock-Cycle Diagram: ADDClock Cycle 3 SW LW
IF/ID ID/EX EX/MEM MEM/WB
ADD ADD 4 <<2 PC ADDR RD RN1 RD1 32 5 ALU Zero Instruction RN2 5 Memory Register WN File 5 RD2 M WD U ADDR X Data Memory RD M E U 16 X 32 X T WD N 5 D Single-Clock-Cycle Diagram: SUBClock Cycle 4 ADD SW LW
IF/ID ID/EX EX/MEM MEM/WB
ADD ADD 4 <<2 PC ADDR RD RN1 RD1 32 5 ALU Zero Instruction RN2 5 Memory Register WN File 5 RD2 M WD U ADDR X Data Memory RD M E U 16 X 32 X T WD N 5 D Single-Clock-Cycle Diagram: Clock Cycle 5 SUB ADD SW LW
IF/ID ID/EX EX/MEM MEM/WB
ADD ADD 4 <<2 PC ADDR RD RN1 RD1 32 5 ALU Zero Instruction RN2 5 Memory Register WN File 5 RD2 M WD U ADDR X Data Memory RD M E U 16 X 32 X T WD N 5 D Single-Clock-Cycle Diagram: Clock Cycle 6 SUB ADD SW
IF/ID ID/EX EX/MEM MEM/WB
ADD ADD 4 <<2 PC ADDR RD RN1 RD1 32 5 ALU Zero Instruction RN2 5 Memory Register WN File 5 RD2 M WD U ADDR X Data Memory RD M E U 16 X 32 X T WD N 5 D Single-Clock-Cycle Diagram: Clock Cycle 7 SUB ADD
IF/ID ID/EX EX/MEM MEM/WB
ADD ADD 4 <<2 PC ADDR RD RN1 RD1 32 5 ALU Zero Instruction RN2 5 Memory Register WN File 5 RD2 M WD U ADDR X Data Memory RD M E U 16 X 32 X T WD N 5 D Single-Clock-Cycle Diagram: Clock Cycle 8 SUB
IF/ID ID/EX EX/MEM MEM/WB
ADD ADD 4 <<2 PC ADDR RD RN1 RD1 32 5 ALU Zero Instruction RN2 5 Memory Register WN File 5 RD2 M WD U ADDR X Data Memory RD M E U 16 X 32 X T WD N 5 D Alternative View – Multiple-Clock-Cycle Diagram CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 Time axis lw $t0, 10($t1) IM REG ALU DM REG
