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PIC 8259 Interface

The document discusses interfacing the 8259 Programmable Interrupt Controller (PIC) with the 8085 microprocessor. It describes how the data and address lines are connected between the two chips and how interrupt request and acknowledgement signals are handled. It also explains how multiple 8259 PICs can be cascaded together when more than 8 interrupt lines are needed. The initialization process for the 8259 PIC using initialization command words is outlined to configure the interrupt vector addresses and operation modes.

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100 views16 pages

PIC 8259 Interface

The document discusses interfacing the 8259 Programmable Interrupt Controller (PIC) with the 8085 microprocessor. It describes how the data and address lines are connected between the two chips and how interrupt request and acknowledgement signals are handled. It also explains how multiple 8259 PICs can be cascaded together when more than 8 interrupt lines are needed. The initialization process for the 8259 PIC using initialization command words is outlined to configure the interrupt vector addresses and operation modes.

Uploaded by

Jeslin John
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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INTERFACING PIC 8259

WITH 8085 MICRO-


PROCESSOR
Interfacing 8259 with 8085

• The low order data bus lines D0-D7 are connected to D0-D7 of 8259.
• The address line A0 of the 8085 processor is connected to A0 of 8259 to provide the internal address.
• The 8259 require one chip select signal. Using 3-to-8 decoder generates the chip select (CS) signal for 8259.
• The RD and WR signals of the IC are connected to I/OR and I/OW terminals respectively.
• INT terminal of the 8259 is connected to the INTR terminal of the processor.
• The INTA output of the processor is connected to the INTA terminal of the 8259.
• The terminal SP / EN is connected to +5 V supply when only one 8259 is used in the system. If many 8259s
are cascaded, then this terminal is connected to the ground terminal.
• The cascaded pins (CAS0 – CAS2) are left open.
• The eight interrupt request pins IR0-IR7 are available for the I/O devices to send the interrupt signals. If any of
these interrupt request pins are not used, they may be connected to the ground so that the noise pulse can
not create any interrupt.
Cascading many 8259 with 8085

• The SP/EN terminal of the master PIC is connected to + VCC, whereas SP/EN terminals of all the slave
PICs are connected to ground.
• The INT output of each slave PICs are connected to one of the interrupt lines (IR 0-IR7) of the master
8259 i.e. 8 INT terminals of 8 slave 8259s are connected to 8 interrupt request lines (IR 0-IR7) .
• When interrupt request line of a slave is activated, the slave PIC in turn activates one of the interrupt
request lines of the master 8259, which in turn interrupts the microprocessor.
• After the INTA is received from the microprocessor, the master enables the corresponding CAS 0 – CAS2
lines to release the vector address on the data bus in the next two INTA signals.
• The output of the address decoder is connected to the CS of the 8259 PIC.
• It communicates with the CPU with the bidirectional bus.
• The two I/O port addresses F0 H and F1 H are chosen for the 8259 with A 0 = 0 and A0 = 1.
• It may be noted here that each 8259A (interfaced with 8085A) has its own I/O address which is defined
by the address decoder.
Interrupt Sequence

• One or more of the INTERRUPT REQUEST lines (IR7 –0) are raised high, setting the corresponding IRR bit(s).
• The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate.
• The CPU acknowledges the INT and responds with an INTA pulse.
• Upon receiving an INTA from the CPU group, the highest priority ISR bit is set, and the corresponding IRR bit is
reset. The 8259A will also release a CALL instruction code (11001101) onto the 8-bit Data Bus through its D7 –0
pins.
• This CALL instruction will initiate two more INTA pulses to be sent to the 8259A from the CPU group.
• These two INTA pulses allow the 8259A to release its preprogrammed subroutine address onto the Data Bus. The
lower 8-bit address is released at the first INTA pulse and the higher 8-bit address is released at the second INTA
pulse.
• This completes the 3-byte CALL instruction released by the 8259A. In the AEOI mode the ISR bit is reset at the end
of the third INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end
of the interrupt sequence
Initialization of 8259
1. Initialization Command Words(ICWs)
2. Operation Command Words (OCWs)

Initialization Command Words


• Four command words – ICW 1, ICW 2, ICW 3, ICW 4.
• ICW 1 and ICW 2 are essential for any 8259 system.
• ICW 3 is used when the system has slave 8259.
• ICW 4 is used for special operations.
 Initialization Command Word 1
 Initialization Command Word 1
 Initialization Command Word 2

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 A15 A14 A13 A12 A11 A10 A9 A8

A15 – A8 OF INTERRUPT VECTOR ADDRESS FOR 8085


 Initialization Command Word 3
• Master Mode ICW 3
• Slave Mode ICW 3
 Initialization Command Word 4
Initialization
Sequence
REFERENCE

• An Introduction to Microprocessor 8085 by Dr. D K Kaushik.


• https://electronicsdesk.com/8259-programmable-interrupt-con
troller.html
• https://www.geeksforgeeks.org/8259-pic-microprocessor/amp/
THANK YOU

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