Memory Management

Chapter 3

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Memory
• Paraphrase of Parkinson’s Law, ‘‘Programs
expand to fill the memory available to hold
them.’’
• Average home computer nowadays has 10,000
times more memory than the IBM 7094, the
largest computer in the world in the early
1960s

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 No Memory Abstraction

Figure 3-1. Three simple ways of organizing memory with an

operating system and one user process. Other possibilities also exist
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Running Multiple
Programs Without a
Memory Abstraction

Figure 3-2. Illustration of the relocation problem. (a) A 16-KB program. (b) Another
16-KB program. (c) The two programs loaded consecutively into memory.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Base and Limit
Registers

Figure 3-3. Base and limit registers can

be used to give each process a separate
address space.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Swapping (1)

Figure 3-4. Memory allocation changes as processes come into

memory and leave it. The shaded regions are unused memory
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Swapping (2)

Figure 3-5. (a) Allocating space for a growing data segment.

(b) Allocating space for a growing stack and a growing data segment.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Memory Management with
Bitmaps

Figure 3-6. (a) A part of memory with five processes and

three holes. The tickmarks show the memory allocation
units. The shaded regions (0 in the bitmap) are free. (b) The
corresponding bitmap. (c) The same information as a list.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
Memory Management with Linked Lists

Figure 3-7. Four neighbor combinations for the

terminating process, X.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Memory Management Algorithms

• First fit
• Next fit
• Best fit
• Worst fit
• Quick fit

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Virtual Memory
• There is a need to run programs that are too
large to fit in memory
• Solution adopted in the 1960s, split programs
into little pieces, called overlays
– Kept on the disk, swapped in and out of memory
• Virtual memory : each program has its own
address space, broken up into chunks called
pages

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Paging (1)

Figure 3-8. The position and function of the MMU. Here the
MMU is shown as being a part of the CPU chip because
it commonly is nowadays. However, logically it
could be a separate chip and was years ago.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Paging (2)

Figure 3-9. The relation between virtual addresses and physical memory
addresses is given by the page table. Every page begins on a multiple of
4096 and ends 4095 addresses higher, so 4K–8K really means 4096–8191
and 8K to 12K means 8192–12287
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Paging (3)

Figure 3-10. The internal

operation of the MMU
with 16 4-KB pages.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Structure of a Page Table Entry

Figure 3-11. A typical page table entry.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Speeding Up Paging
Major issues faced:
1.The mapping from virtual address to physical
address must be fast.
2.If the virtual address space is large, the page
table will be large.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Translation Lookaside Buffers

Figure 3-12. A TLB to speed up paging.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Multilevel
Page Tables

Figure 3-13. (a) A 32-bit

address with two page
table fields. (b) Two-level
page tables.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Inverted Page Tables

Figure 3-14. Comparison of a traditional page table

with an inverted page table.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Page Replacement Algorithms
• Optimal algorithm
• Not recently used algorithm
• First-in, first-out (FIFO) algorithm
• Second-chance algorithm
• Clock algorithm
• Least recently used (LRU) algorithm
• Working set algorithm
• WSClock algorithm
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Not Recently Used Algorithm
• At page fault, system inspects pages
• Categories of pages based on the current
values of their R and M bits:
Class 0: not referenced, not modified.
Class 1: not referenced, modified.
Class 2: referenced, not modified.
Class 3: referenced, modified.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Second-Chance Algorithm

Figure 3-15. Operation of second chance. (a) Pages sorted in FIFO

order. (b) Page list if a page fault occurs at time 20 and A has its R
bit set. The numbers above the pages are their load times.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
Clock Page Replacement Algorithm

Figure 3-16. The clock page replacement algorithm.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Simulating LRU in Software

Figure 3-17. The aging algorithm simulates LRU in software. Shown are
six pages for five clock ticks. The five clock ticks are represented by (a)
to (e).
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Working Set Algorithm (1)

Figure 3-18. The working set is the set of pages used by the k most recent
memory references. The function w(k, t) is the size of the working set at time
t.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Working Set Algorithm (2)

Figure 3-19. The working set algorithm.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 WSClock Algorithm (1)

Figure 3-20. Operation of the WSClock algorithm. (a) and (b)

give an example of what happens when R = 1.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 WSClock Algorithm (2)

Figure 3-20. Operation of the WSClock algorithm.

(c) and (d) give an example of R = 0.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Summary of Page Replacement
Algorithms

Figure 3-21. Page replacement algorithms discussed in the text.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
Local versus Global Allocation Policies (1)

Figure 3-22. Local versus global page replacement.

(a) Original configuration. (b) Local page replacement.
(c) Global page replacement.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
Local versus Global Allocation Policies (2)

Figure 3-23. Page fault rate as a function of the number of

page frames assigned.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
Separate Instruction and Data Spaces

Figure 3-24. (a) One address space.

(b) Separate I and D spaces.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Shared Pages

Figure 3-25. Two processes sharing the same

program sharing its page table.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Shared Libraries

Figure 3-26. A shared library being used by two processes.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Page Fault Handling (1)
1. The hardware traps to kernel, saving program
counter on stack.
2. Assembly code routine started to save general
registers and other volatile info
3. system discovers page fault has occurred, tries
to discover which virtual page needed
4. Once virtual address caused fault is known,
system checks to see if address valid and the
protection consistent with access
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Page Fault Handling (2)
5. If frame selected dirty, page is scheduled for
transfer to disk, context switch takes place,
suspending faulting process
6. As soon as frame clean, operating system
looks up disk address where needed page is,
schedules disk operation to bring it in.
7. When disk interrupt indicates page has
arrived, tables updated to reflect position,
and frame marked as being in normal state.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Page Fault Handling (3)
8. Faulting instruction backed up to state it had
when it began and program counter is reset
9. Faulting process is scheduled, operating
system returns to routine that called it.
10. Routine reloads registers and other state
information, returns to user space to
continue execution

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Instruction Backup

Figure 3-27. An instruction causing a page fault.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Backing Store

Figure 3-28. (a) Paging to a static swap area.

(b) Backing up pages dynamically.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Separation of Policy and
Mechanism (1)
Memory management system is divided into
three parts
1.A low-level MMU handler.
2.A page fault handler that is part of the kernel.
3.An external pager running in user space.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
Separation of Policy and Mechanism (2)

Figure 3-29. Page fault handling with an external pager.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Segmentation (1)
Examples of tables generated by compiler:
1.The source text being saved for the printed listing
2.The symbol table, names and attributes of variables.
3.The table containing integer and floating-point
constants used.
4.The parse tree, syntactic analysis of the program.
5.The stack used for procedure calls within compiler.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Segmentation (2)

Figure 3-30. In a one-dimensional address space with

growing tables, one table may bump into another.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Segmentation (3)

Figure 3-31. A segmented memory allows each table to grow

or shrink independently of the other tables.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Segmentation (4)

Figure 3-32. Comparison of paging and segmentation

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
Implementation of Pure Segmentation

Figure 3-33. (a)-(d) Development of checkerboarding.

(e) Removal of the checkerboarding by compaction.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
Segmentation with Paging: MULTICS (1)

Figure 3-34. The MULTICS virtual memory. (a) The descriptor

segment pointed to the page tables.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
Segmentation with Paging: MULTICS (2)

Figure 3-34. The MULTICS virtual memory. (b) A segment

descriptor. The numbers are the field lengths.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
Segmentation with Paging: MULTICS (3)

Figure 3-35. A 34-bit MULTICS virtual address.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
Segmentation with Paging: MULTICS (4)

Figure 3-36. Conversion of a two-part MULTICS address into a main

memory address.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
Segmentation with Paging: MULTICS (5)

Figure 3-37. A simplified version of the MULTICS TLB. The existence of two page
sizes made the actual TLB more complicated.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Segmentation with Paging:
The Intel x86 (1)

Figure 3-38. An x86 selector.

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Segmentation with Paging:
The Intel x86 (2)

Figure 3-39. x86 code segment descriptor.

Data segments differ slightly.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Segmentation with Paging:
The Intel x86 (3)

Figure 3-40. Conversion of a (selector, offset)

pair to a linear address.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 Segmentation with Paging:
The Intel x86 (4)

Figure 3-41. Mapping of a linear address

onto a physical address.
Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
 End

Chapter 3

Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.