HND in Computing and Software

Engineering
SEC4101: Fundamentals in Computer Systems
Level: 4
Credit Value: 10

Lesson 03 - Combinational Circuits

Lecturer: Mr.
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 Unit Aim

This module provides a foundation for all professional computer

personnel in computer technology and related topics, in particular the
areas of: number systems, hardware, operating systems, systems software,
and system performance measurement.

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 Unit Learning Outcomes

On successful completion of this unit a learner will:

Understand the principles of the architecture and organization of computer

systems.
Understand the fundamental aspects of all digital computers and the
operating principles of computer peripherals.
Understand the principles underlying operating systems and system software.

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 Reference Materials
Williams, R., Computer Systems Architecture - A Networking Approach,
Prentice Hall (2nd Ed), 2006.
Clements, A., The Principles of Computer Hardware, Oxford University
Press (4th Ed), 2006.
Tanenbaum, Andrew, S., Modern Operating Systems, Prentice Hall (4th Ed),
2014..

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 Assessment Strategy
Examination: Learning Outcome 1, & 2.
Exam will cover 70% of the total marks for the module.
Exam which contain multiple choice and essay questions.

Presentation : Learning Outcome 3.

Presentation will cover 30% of the total marks for the module.

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 Learning Outcome 01

Understand the principles of the architecture and

organization of computer systems.

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 Integrated Circuits (ICs)
An Integrated Circuit is a small silicon semiconductor
crystal(chip), containing the electronic components for
digital gates.
Various gates are interconnected inside the chip to form the
required circuits.
Chip is mounted in a ceramic or plastic container and
connections are welded by thin gold wires to the external
pins to form the integrated circuit.

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 Integrated Circuits

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 Integrated Circuits (ICs)
The IC pins provide access to the input and output terminals of individual
gates as well as power supply to the whole device.

Figure 4-17. An SSI chip containing four gates.

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 Integrated Circuits (Contd.)
ICs are roughly classified based on the number of gates they contain:

SSI (Small Scale Integrated) circuit: contain several independent

gates in a single package (1 to 10 gates.)

MS I (Medium Scale Integrated) circuit: 10 to 200 gates are in a

single package. Usually perform specific elementary digital functions
such as adders, decoders and registers.

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 Integrated Circuits (Contd.)
LSI (Large Scale Integrated) circuit: has 200 to few thousand gates
in a single package. They include digital systems such as processors,
memory chips and programmable modules.

VLSI (Very Large Scale Integrated) circuit: >100,000 gates.

Examples : large memory arrays and complex microcomputer chips.
 characteristics – size is small and low cost and this is
revolutionized the computer system design technology by
designing economical computers.

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 Combinational Circuits
A connected arrangement of logic gates with a set of inputs
and outputs
At any given time, the binary values of the outputs are a
function of the binary combination of the inputs.
This circuits are employed in digital computers for generating
binary control decisions and for providing digital components
required for data processing.

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 Combinational Circuits

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 Designing Combinational Circuits
In general we have to do following steps:
1. Problem description
2. Input/output of the circuit
3. Define truth table
4. Simplification for each output
5. Draw the circuit

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 Combinational Circuits
To demonstrate the design of combinational circuits, two simple
arithmetic circuits can be given
• Half-Adder
• Full-Adder

• Half-Adder
 A combinational circuit that performs the arithmetic addition of two
bits is called half adder.

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 Combinational Circuits
– Half-Adder
Input variables of the Half-Adder
• Augend and addend bits.
The Output variables
• sum and carry
It is necessary to specify the two output variables because sum of 1 +1 is
binary 10. which is two digits.

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 Exclusive-OR
The XOR ( exclusive-OR ) gate acts in the same way as the logical
"either/or."
The output is "true" if either, but not both, of the inputs are "true."
The output is "false" if both inputs are "false" or if both inputs are "true."
Another way of looking at this circuit is to observe that the output is 1 if
the inputs are different, but 0 if the inputs are the same.

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 Exclusive-OR

Truth table for XOR gate

INPUT
INPUT OUTPUT
OUTPUT

0 0 0

0 1 1

1 0 1

1 1 0

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 AND Gate
INPUT
INPUT OUTPUT
OUTPUT  
A F = A.B
B  
A
A B
B F=A.B
F=A.B
       
Inputs Output
False as one
0 0 0 or more
A B inputs are
0 1 0 false
1 0 0
True as all
1 1 1 inputs are true

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 Combinational Circuits: Half Adder
Half Adder : The sum is XOR operation and the carry an
AND

Sum= A’B+AB’
A+ B
Carry=AB

Figure 4-23 (a) Truth table for 1 bit addition. (b) A circuit for a half adder
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 Combinational Circuits – Full Adder
1. A full adder is a combinational circuit that forms the
arithmetic sum of three input bits.
2. It consists three inputs and two outputs.
3. Define a truth table.

Input Output X Sum

x y z C S
0 0 0 0 0 Y full
0 0 1 0 1 adder C
0 1 0 0 1 Z
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
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 Combinational Circuits – Full Adder
4. Simplification for each output
C= xy’z + x’yz + xy
Input Output =z(xy’ + x’y) + xy
x y z C S
0 0 0 0 0 =z(x  y) + xy
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
S=xy’z’ + x’y’z + xyz + x’yz’
1 0 0 0 1 = z’(xy’ + x’y) + z(x’y’ + xy)
1 0 1 1 0
1 1 0 1 0 = z’(x  y) + z(x  y)’
1 1 1 1 1 =a’b + ab’ (let a=z, b=x  y)
=x  y  z
(x y)’=(xy’+x’y)’
=x’y’’ + x’’y’
=x’y + xy’
=(x’+y)(x+y’) Duality
=x’x+x’y’+xy+yy’ Identity
22 =x’y’+xy
 Combinational Circuits: Full Adder
5. Draw a diagram

Input Output
x y z C S x
y
0 0 0 0 0 c
0 0 1 0 1 z
0 1 0 0 1
0 1 1 1 0 s
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

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 Maps of Full-Adder

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 General Digital System Diagram

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 Synchronous and Asynchronous Sequential Logic
Synchronous
• the timing of all state transitions is controlled by a common clock
• changes in all variables occur simultaneously

Asynchronous
• state transitions occur independently of any clock and normally
dependent on the timing of transitions in the input variables
• changes in more than one output do not necessarily occur
simultaneously

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 Synchronous and Asynchronous Sequential Logic
(Contd.)
Clock
• A clock signal is a square wave of fixed frequency Often, transitions
will occur on one of the edges of clock pulses
• Clock signals are used to maintain the desired timing in the circuits.
• Clock circuits emit pulse trains of precise repetition interval and width.
• Sometimes it is necessary to have one clock pulse train trail another by a
fixed time.
• A circuit with the appropriate delay may be inserted to achieve the
desired phase shift

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 Clock Signals

Clock circuit and the clock waveforms

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 Flip-Flops (Latch)
 A flip-flop or latch is a circuit that has two stable states
and can be used to store state information.
This circuit can be made to change state by signals
applied to one or more control inputs and will have one or
two outputs
Flip-flops are the fundamental element of sequential
circuits.
• (gates are the fundamental element for combinational circuits)
Flip-flops is a binary cell capable of storing one bit
information and basic storage element in sequential logic

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 Flip-Flops
Flip-flops have two outputs
• One for the normal value (Q)
• One for the complement value the bit stored it (Q).
Flip-flops can be either simple (transparent or asynchronous)
or clocked (synchronous)
the transparent ones are commonly called latches.[
 The word latch is mainly used for storage elements
The clocked devices are described as flip-flops.

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 Flip-Flops(Contd.)
Usage: Flip-flops and latches are a fundamental building block of digital
electronics systems used in computers, communications, and many other
types of systems.

Main types of flip-flops

• S-R(Set-Reset) Flip-Flop
• D (Data or Delay) Flip Flop
• J-K Flip-Flop

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 S-R Flip-Flops
A RS-flip-flop is the simplest possible memory element.
It is constructed by feeding the outputs of two NOR gates back to the
other NOR gates input.

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 S-R Flip-Flops

 S=0 and R=0: Assume the flip flop is set (Q=0 and Q=1), then the
output of the top NOR gate remains at Q=1 and the bottom NOR gate
stays at Q=0.
 Similarly, when the flip flop is in a reset state (Q=1 and Q=0), it will
remain there with this input combination.
 Therefore, with inputs S=0 and R=0, the flip flop remains in its state.

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 S-R Flip-Flops

 S=0 and R=1: Similar to the arguments above, the outputs become Q=0
and Q=1.
 We say that the flip flop is reset.

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 S-R Flip-Flops

 S=0 and R=0: Assume the flip flop is set (Q=0 and Q=1), then the
output of the top NOR gate remains at Q=1 and the bottom NOR gate
stays at Q'=0.
 Similarly, when the flipflop is in a reset state (Q=1 and Q'=0), it will
remain there with this input combination.
 Therefore, with inputs S=0 and R=0, the flipflop remains in its state.
 S=1 and R=1: This input combination must be avoided.

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