WDT
Watch Dog Timer
Introduction
Watchdog Timer (WDT) can be helpful to
automatically reset the system whenever a timeout
occurs.
System reset is required for preventing failure of the
system in a situation of a hardware fault or program
error.
There are countless applications where the system
cannot afford to get stuck at a point (not even for a
small duration of time). For example, in a radar
system, if the system hangs for 5 minutes, it can result
in serious repercussions (an enemy plane or missile
may go undetected resulting in huge losses).
Introduction..,
The system should be robust enough to automatically
detect the failures quickly and reset itself in order to
recover from the failures and function normally
without errors.
One can manually reset the system to recover from
errors. But it is not always feasible to manually reset
the system, especially once it has been deployed.
To overcome such problems, a watchdog timer is
necessary to automatically reset the system without
human intervention.
PC2148 has an inbuilt watchdog timer. The watchdog
when enabled generates a system reset if the user
program fails to feed (or reload) the watchdog within a
predetermined amount of time.
The watchdog consists of a fixed divide by 4 prescalar
and a 32-bit counter. The clock is fed to the timer
through the prescalar.
The counter can be loaded with any value between
0xFF and 0xFFFFFFFF. If the counter is loaded with
any value less than 0xFF, the counter is initialized with
a value 0xFF.
The watchdog needs to be fed with a pre-determined
sequence of 0xAA followed by 0x55 before watchdog
timer underflows to prevent reset/interrupt.
Features
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a
watchdog reset/interrupt to be disabled.
Incorrect/Incomplete feed sequence causes
reset/interrupt if enabled.
Flag to indicate Watchdog reset.
Programmable 32-bit timer with internal pre-scaler.
Selectable time period from (TPCLK x 256 x 4) to
(TPCLK x 232 x 4) in multiples of TPCLK x 4.
Features
The purpose of the watchdog is to reset the
microcontroller within a reasonable amount of time if
it enters an erroneous state.
When enabled, the watchdog will generate a system
reset if the user program fails to feed (or reload) the
watchdog within a predetermined amount of time.
Description
divide by 4 fixed pre-scaler
32-bit counter
The clock is fed to the timer via a pre-scaler
The timer decrements when clocked
The minimum value from which the counter
decrements is 0xFF
When the Watchdog counter underflows, the program
counter will start from 0x0000 0000 as in the case of
external reset.
Description…
The Watchdog Time-Out Flag (WDTOF) can be
examined to determine if the watchdog has caused the
reset condition.
The WDTOF flag must be cleared by software.
WDT- Programming
Set the watchdog timer constant reload value in
WDTC register.
Setup mode in WDMOD register.
Start the watchdog by writing 0xAA followed by 0x55
to the WDFEED register.
Watchdog should be fed again before the watchdog
counter underflows to prevent reset/interrupt
WDT- Registers
WDMOD Watchdog Mode register
This register contains the basic mode and status of the
Watchdog Timer.
WDTC Watchdog Timer Constant register
This register determines the time-out value.
WDFEED Watchdog Feed sequence register
Writing 0xAA followed by 0x55 to this register reloads the
Watchdog timer to its preset value.
WDTV Watchdog Timer Value register
This register reads out the current value of the Watchdog
timer
W DMOD (Watchdog Mode Register)
WDMOD (Watchdog Mode Register)
It is an 8-bit read-write register.
It is used to control the operation of the watchdog.
Bit 0 – WDEN (Watchdog Interrupt Enable)
Bit 1 – WDRESET (Watchdog Reset Enable)
Bit 2 – WDTOF (Watchdog Time-Out Flag)
This bit is set when the watchdog times [Link] is cleared by software.
Bit 3 – WDINT (Watchdog Interrupt Flag)
This bit is set when the watchdog times out. This bit is cleared when
any reset [Link] is a read only bit.
WDMOD (Watchdog Mode Register)`
WDEN WDRESET Mode of Operation
0 0 or 1 Debug/Operate without watchdog running
Watchdog Interrupt Mode: Debug with watchdog interrupt
but no WDRESET enabled.
1 0
A watchdog counter underflow will set the WDINT flag and
the watchdog interrupt request will be generated.
Watchdog Reset Mode: Operate with the watchdog
interrupt and WDRESET enabled.
A watchdog counter underflow will reset the
1 1
microcontroller. Although the watchdog interrupt is also
enabled (WDEN=1), it will not be recognized since the
watchdog reset will clear the WDINT flag.
WDTC (Watchdog Timer Constant
Register)
Every time a sequence feed occurs, the WDTC content
is loaded into the watchdog timer.
The 8 least significant bits (bits 7:0) of this register are
set to 1 on reset.
Any value below 0xFF will cause 0xFF to be loaded in
this register. Hence, the minimum timeout interval is
(TPCLK * 256 * 4).
WDFEED (Watchdog Feed Register)
It is an 8-bit write only register.
Writing a 0xAA followed by 0x55 to this register will
reload the watchdog timer with the WDTC value.
This operation will also start the watchdog if it is
enabled via the WDMOD register.
Making WDEN bit 1 in the WDMOD register is not
sufficient to start the watchdog. A valid feed sequence
must be completed so that the watchdog is able to
generate an interrupt/reset. Until then, the watchdog
will ignore feed errors.
WDFEED (Watchdog Feed Register)
Once a 0xAA is written to the FEED register, the next
operation should be a 0x55 write to the FEED register,
otherwise, the watchdog is triggered.
The interrupt/reset will be generated during the
second PCLK following an incorrect access to a
watchdog timer register during a feed sequence.
Interrupts should be disabled during the feed
sequence. An abort condition will occur if an interrupt
occurs during the feed sequence.
WDTV (Watchdog Timer Value Register)
It is a 32-bit read only register.
It is used to read the current value of watchdog timer.
How to use the Watchdog in LPC2148?
Set the watchdog timer constant reload value in the
WDTC register
Select the mode using the WDMOD register
Start the watchdog by feeding it with 0xAA followed
by 0x55 in the WDFEED register
How to use the Watchdog in LPC2148?
Make sure to feed the watchdog again before the timer
counter underflows in order to prevent reset/interrupt
The Watchdog Time-Out Flag (WDTOF) can be
monitored to determine if the watchdog has caused
reset condition. The WDTOF flag must be cleared
using software.
WDT diagram
WDT Program
#include <lpc214x.h>
#include <stdint.h>
void delay_ms(uint16_t j)
{
uint16_t x,i;
for(i=0;i<j;i++)
{ for(x=0; x<6000; x++); /* loop to generate 1 milisecond
delay with Pclk=15MHz */
}
}
WDT Program…
int main(void)
{
IO0DIR = IO0DIR | 0x00000003; /* P0.0,P0.1 as
outputs for LEDs */
IO0CLR = 0x00000003; /* LEDs OFF */
delay_ms(3000);
WDT Program…
if ( WDMOD & 0x04 )
{
IO0CLR = 0x00000003;
IO0SET = 0x00000002; /* P0.1 LED ON */
delay_ms(3000); /* Indicate Watchdog Reset using
LED at P0.1 */
IO0CLR = 0x00000002; /* P0.1 LED OFF */
delay_ms(2000);
}
WDT Program…
WDTC = 0x0007FFFF; // For 139msec delay
WDMOD = 0x03;// Watchdog interrupt enable with
watchdog reset
WDFEED = 0xAA;
WDFEED = 0x55;
IO0SET = 0x00000001; /* P0.0 LED ON */
delay_ms(50);
IO0CLR = 0x00000001; /* P0.0 LED OFF */
delay_ms(50);
WDT Program…
WDFEED = 0xAA;
WDFEED = 0x55;
IO0SET = 0x00000001; delay_ms(55);
IO0CLR = 0x00000001; delay_ms(55);
WDFEED = 0xAA;
WDFEED = 0x55;
return 0;
}
