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Aim of The Experiment Design and Implementation of A 16 Bit Program Counter

The document describes the design and implementation of a 16-bit program counter (PC) module in Verilog. The PC register stores the memory address of the next instruction to be fetched. It supports incrementing by 1 and adding/subtracting a given offset value. The PC is implemented as a 16-bit register using basic components like full adders and D flip-flops. Its functionality is tested with a testbench that applies different operations and verifies the output.

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169 views13 pages

Aim of The Experiment Design and Implementation of A 16 Bit Program Counter

The document describes the design and implementation of a 16-bit program counter (PC) module in Verilog. The PC register stores the memory address of the next instruction to be fetched. It supports incrementing by 1 and adding/subtracting a given offset value. The PC is implemented as a 16-bit register using basic components like full adders and D flip-flops. Its functionality is tested with a testbench that applies different operations and verifies the output.

Uploaded by

Amogh Vr
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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AIM OF THE EXPERIMENT

Design and Implementation of a


16 bit Program Counter
DEFINITION
For a microprocessor to load and execute an instruction, it first
needs to fetch the instruction from the memory.
To do so, there has to be a register in the microprocessor which
stores the memory address of the next instruction to be fetched.
That register is the Program Counter (PC).
WORKING OF THE PROGRAM
COUNTER
• Typically, the microprocessor fetches and executes
instructions
• But occasionally, there can be jumps---the next instruction to
be fetched and executed may be several instructions ahead or
behind the current instruction.
• Likewise, the circuitry associated with the PC registers needs
to support two operations:
(1) increment the PC contents by one,
(2) add/subtract given value to PC contents.
• The PC register is of length 16-bits.
• After the reset signal is applied, its contents should be zero.
• Considering the PC module as a black box, it has the following
inputs: clk, reset, inc, add, sub, offset of which only offset is a
wire vector of length 16.
• The only output of pc is a 16-bit wire vector of PC register
contents.
• The increment and add/subtract operations each take one
clock cycle, so one or add/subtract operation can be
performed every clock.
• Depending upon the inputs received in the current clock
cycle, the increment or add/subtract can be performed and
made available at the inputs to the PC register in the current
clock cycle itself.
• But the contents of the PC register will change only at the
positive clock edge and so the updated register output will be
seen only in the next clock cycle but during which the next
operation can be computed.
• In this way one operation can be performed every clock cycle.
1. When inc is high, the increment operation is to be
performed.

 The add, sub, offset inputs are ignored and the contents of the PC
register are simply incremented by one.
2. When add or sub is high, the add or subtract operation
respectively is performed, during which the value offset is
added to or subtract from the PC register contents, and the
result is stored back in the PC register.
3. When inc, add and sub are all low, PC register value remains
unchanged. It is guaranteed that at most one of inc, add or
sub will be high in a clock cycle.
DESIGN AND SIMULATION
iverilog -o tb_pc lib.v pc.v tb_pc.v

vvp tb_pc

The pc module can be tested using the supplied tb_pc.v with


the commands to simulate:
You can use the lib.v supplied for basic components.

Waveform observation with the command:

gtkwave tb_pc.vcd
•
pc.v Module 1
module fa (input wire i0, i1, cin, output wire sum,
cout);
wire t0, t1, t2;
xor3 _i0 (--------------------);
and2 _i1 (----------------------);
and2 _i2 (-----------------------);
and2 _i3 (------------------);
or3 _i4 (--------------------);
endmodule
pc.v Module 2
module addsub (input wire addsub, i0, i1, cin,
output wire sumdiff, cout);
wire t;
fa _i0 (--------------------);
xor2 _i1 (--------------------);
endmodule
pc.v Module 3
module pc_slice (input wire clk, reset, cin, load,
inc, sub, offset, output wire cout, pc);
wire in, inc_;
invert invert_0 (-------------);
and2 and2_0 (-----------------);
addsub addsub_0 (----------------------);
dfrl dfrl_0 (------------------------);
endmodule
pc.v Module 4
module pc_slice0 (input wire clk, reset, cin, load,
inc, sub, offset, output wire cout, pc);
wire in;
or2 or2_0 (--------------------);
addsub addsub_0 (----------------);
dfrl dfrl_0 (----------------------);
endmodule
pc.v Module 5
module pc (input wire clk, reset, inc, add, sub, input wire [15:0] offset,
output wire [15:0] pc);
input wire load; input wire [15:0] c;
or3 or3_0 (------------------);
pc_slice0 pc_slice_0 (clk, reset, sub, load, inc, sub, offset[0], c[0], pc[0]);
pc_slice pc_slice_1 (clk, reset, c[0], load, inc, sub, offset[1], c[1], pc[1]);
-----------------------------------------------------------------------------------------------
pc_slice pc_slice_15 (clk, reset, c[14], load, inc, sub, offset[15], c[15],
pc[15]);
endmodule
OUTPUT TABLE

inc add sub offset


1 0 0 XXXX
0 1 0 00A5
0 0 0 XXXX
1 0 0 XXXX
0 0 1 0014

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