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Name: S. Karthikeyan. Class: ll-MECHATRONICS. ROLL NO: 17MC023. Sub: Microprocessor & Microcontroller. DATE: 16/04/2019

This document summarizes the architecture of the 8085 microprocessor, including its bus structure and internal components. It discusses the 16-bit address bus, 8-bit data bus, and control bus. It describes the registers, accumulator, flag bits, program counter, and stack pointer inside the CPU. Examples are given of memory read and instruction fetch operations.

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27 views14 pages

Name: S. Karthikeyan. Class: ll-MECHATRONICS. ROLL NO: 17MC023. Sub: Microprocessor & Microcontroller. DATE: 16/04/2019

This document summarizes the architecture of the 8085 microprocessor, including its bus structure and internal components. It discusses the 16-bit address bus, 8-bit data bus, and control bus. It describes the registers, accumulator, flag bits, program counter, and stack pointer inside the CPU. Examples are given of memory read and instruction fetch operations.

Uploaded by

Shocky S
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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NAME : S. KARTHIKEYAN.

Class : ll- MECHATRONICS.


ROLL NO : 17MC023.
SUB : MICROPROCESSOR &
MICROCONTROLLER.
DATE : 16\04\2019.

1
8085 Microprocessor Architecture

2
The 8085 Bus Structure
The 8-bit 8085 CPU (or MPU – Micro Processing Unit)
communicates with the other units using a 16-bit
address bus, an 8-bit data bus and a control bus.

3
The 8085 Bus Structure

Address Bus
 Consists of 16 address lines: A0 – A15

 Operates in unidirectional mode: The address


bits are always sent from the MPU to peripheral
devices, not reverse.

 16 address lines are capable of addressing a


total of 216 = 65,536 (64k) memory locations.

 Address locations: 0000 (hex) – FFFF (hex)

4
The 8085 Bus Structure
Data Bus
 Consists of 8 data lines: D0 – D7
 Operates in bidirectional mode: The data bits
are sent from the MPU to peripheral devices,
as well as from the peripheral devices to the
MPU.
 Data range: 00 (hex) – FF (hex)
Control Bus
 Consists of various lines carrying the control
signals such as read / write enable, flag bits.

5
The 8085: CPU Internal Structure

The internal architecture of the 8085 CPU is


capable of performing the following operations:

 Store 8-bit data (Registers, Accumulator)

 Perform arithmetic and logic operations (ALU)

 Test for conditions (IF / THEN)

 Sequence the execution of instructions


 Store temporary data in RAM during execution

6
The 8085: CPU Internal Structure

Simplified block diagram

7
The 8085: Registers

8
The 8085: CPU Internal Structure
Registers
 Six general purpose 8-bit registers: B, C, D, E, H,
L

 They can also be combined as register pairs to


perform 16-bit operations: BC, DE, HL
 Registers are programmable (data load, move,
Accumulator
etc.)
 Single 8-bit register that is part of the ALU !
 Used for arithmetic / logic operations – the
result is always stored in the accumulator.
9
The 8085: CPU Internal Structure
Flag Bits
 Indicate the result of condition tests.

 Carry, Zero, Sign, Parity, etc.

 Conditional operations (IF / THEN) are executed


based on the condition of these flag bits.
Program Counter (PC)
 Contains the memory address (16 bits) of the
instruction that will be executed in the next step.
Stack Pointer (SP)
10
Example: Memory Read Operation

11
Example: Instruction Fetch Operation

12
Example: Instruction Fetch Operation

13
Thank you.

14

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