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CPLB management
April 2007 Jerry Zeng
What is CPLB ?
CPLB:
Cacheability Protection Lookaside Buffer
Cache:
collection
of data duplicating original values stored elsewhere or computed earlier, where the original data is expensive (usually in terms of access time) to fetch or compute relative to reading the cache
Cache
Direct mapped cache 2-way cache
Instruction Cache
Bank
Only
one bank can be set as cache Bank size is 16K bytes.
Sub-bank
Each
sub-bank is 4k bytes. One bank has 4 sub-banks. Needs 2-bits to identify each sub-bank.
4-way
Each
cache
sub-bank is organized as 4-way cache. Each way is 1K bytes. Each way is independent with each other. Each way has 32 lines, needs 5-bits to identify. Each lines has 64 words. These words are continuous in memory.
Diagram of instruction cache
Instruction cache line
Data Cache
Bank
Each
bank is 16K bytes size. May set one or two banks as data cache.
Half-bank
Each
sub-bank is 8k bytes. One bank has 2 half-banks.
Sub-bank
Each
sub-bank is 4k bytes. Each sub-bank is organized as 2-way cache. Each way is independent with each other.
Data Cache Configuration DCBS=1
Independent
Each
cache
bank can be configured as one 16k bytes, 2-way cache. Bank A and bank B can be set as two 16k bytes, 2-way cache at the same time, A[23] selects the cache. Each bank serves an alternating 8M byte blocks of memory.
Data cache configuration DCBS=0
One
32K, 2-way cache
Only
when two banks are set as cache and DCBS=0. A[14] selects cache. Each bank serves an alternating 16K byte blocks of memory. Two blocks of memory are continuous.
I-Cache Operations
Hits
and Misses
Address
for an instruction request from the core does or not match a valid entry in the cache.
Line
Fills
Fetching
32 bytes from memory. 4x64 bits from line buffer, 8x32 bits from EAB.
Line
Replacement
First
check invalid entries. Priority: Way0,Way1,Way2,Way3. LRU (least recently used) algorithm when no invalid entries.
D-Cache Operations
Cache
status
Invalid. Exclusive
(valid and clean). Modified (valid and dirty).
Write
method
Write-through
: write to external memory upon write to cache Write-back: write to external memory when replace or load the line
Data
cache flush
the specified cache line with external memory.
Synchronize
Data
cache invalidation
Case
1: flush is required. Case 2: flush is not required.
CPLB and CPLB management
Cache
Disable/Enable
I-cache and D-cache. Register: DMEM_CONTROL
Memory
Based
on page management. Consists of CPLB descriptors. One descriptor, one page. Total 16 ICPLB and 16 DCPLB descriptors.
I-CPLB
Total
descriptor
16 descriptors (entries). Registers: ICPLB_ADDR, ICPLB_DATA
D-CPLB
Total
descriptor
16 DCPLB descriptors (entries). Registers: DCPLB_ADDR, DCPLB_DATA
CPLB and CPLB management
Page
Be
attributes
configured in ICPLB_DATA and DCPLB_DATA Page size: 1K, 4K, 1M, 4M bytes. Page cacheable or non-cacheable. Write-through or write-back when cacheable. Dirty or modified. Super and user write access permission. User read access permission. Entry data valid or invalid. Lock (no permit replacement).
Address
Every
comparing
fetch, load, store operation
CPLB management
Hardware
Address
compare. Trigger exception when no valid CPLB descriptor. Writes exception trigger source in register SEQSTAT. Writes faulting address in ICPLB_FAULT_ADDR or DCPLB_FAULT_ADDR. Place CPU into supervisor mode. Place PC to vector of exception.
Software
Check
exception trigger source. Data CPLB protection violation Data access multiple CPLB hits Data access CPLB miss Instruction CPLB protection violation Instruction access multiple CPLB hits Instruction access CPLB miss
Critical Registers
DMEM_CONTROL
ICPLB_DATAx
ICPLB_ADDRx DCPLB_DATAx DCPLB_ADDRx ICPLB_STATUS DCPLB_STATUS DCPLB_FAULT_ADDR ICPLB_FAULT_ADDR
15
External Memory - SDRAM
Kernel
Page size: 4M bytes Cacheable User read access permission for Instruction User read, write and super write access permission for data For data, write back or write through. For data, cache line read and write permission CPLB valid Lock Dirty for data, replacement permission
Generic
The same with kernel except lock
16
External Memory - Flash
Instruction
Page size: 4M bytes User read access permission CPLB valid
Data
Page size: 4M bytes CPLB valid Non-cacheable
17
External Memory MAC buffer
Page
size: 4M bytes CPLB valid Non-cacheable
External Memory External Device Register
Page
size: 4M bytes CPLB valid Non-cacheable
19
Blackfin Kernel
L1 Memory
Instruction
Page size: 1M bytes User read permission Lock CPLB valid Non-cacheable
Data
Page size: 4M bytes User read and write permission Super write permission CPLB valid Non-cacheable
20
