The document describes the Y86 instruction set architecture (ISA), which defines the basic components and execution model of the Y86 processor. The Y86 ISA provides an abstraction of the real computer that hides implementation details while specifying instruction syntax, semantics, and the programmer-visible state including registers, memory, and condition codes. It defines common instructions like arithmetic, logical, move, jump, call, return, and stack operations. The Y86 architecture falls between RISC and CISC and provides a simplified version of the IA32 instruction set to explore computer organization and programming.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online from Scribd
The document describes the Y86 instruction set architecture (ISA), which defines the basic components and execution model of the Y86 processor. The Y86 ISA provides an abstraction of the real computer that hides implementation details while specifying instruction syntax, semantics, and the programmer-visible state including registers, memory, and condition codes. It defines common instructions like arithmetic, logical, move, jump, call, return, and stack operations. The Y86 architecture falls between RISC and CISC and provides a simplified version of the IA32 instruction set to explore computer organization and programming.
The document describes the Y86 instruction set architecture (ISA), which defines the basic components and execution model of the Y86 processor. The Y86 ISA provides an abstraction of the real computer that hides implementation details while specifying instruction syntax, semantics, and the programmer-visible state including registers, memory, and condition codes. It defines common instructions like arithmetic, logical, move, jump, call, return, and stack operations. The Y86 architecture falls between RISC and CISC and provides a simplified version of the IA32 instruction set to explore computer organization and programming.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online from Scribd
The document describes the Y86 instruction set architecture (ISA), which defines the basic components and execution model of the Y86 processor. The Y86 ISA provides an abstraction of the real computer that hides implementation details while specifying instruction syntax, semantics, and the programmer-visible state including registers, memory, and condition codes. It defines common instructions like arithmetic, logical, move, jump, call, return, and stack operations. The Y86 architecture falls between RISC and CISC and provides a simplified version of the IA32 instruction set to explore computer organization and programming.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online from Scribd
Download as ppt, pdf, or txt
You are on page 1/ 25
Processor Architecture
Topics Y86 instruction set architecture Suggested Reading: 4.1
Goal Understand basic computer organization
Instruction set architecture
Deeply explore the CPU working mechanism
How the instruction is executed
Help you programming
Fully understand how computer is organized and works will help you write more stable and efficient code
Instruction Set Architecture #1 What is it ?
Assemble Language Abstraction Machine Language Abstraction Instruction Set Architecture (ISA)
What does it provide?
An abstraction of the real computer, hide the details of implementation The syntax of computer instructions
The semantics of instructions
The execution model Programmer-visible computer status
Instruction Set Architecture #2 Assembly Language View
Processor state Registers, memory,
Application Program Compiler OS ISA CPU Design Circuit Design Chip Layout
Instructions
addl, movl, leal, How instructions are encoded as bytes
Layer of Abstraction Above: how to program machine Processor executes instructions in a sequence
Below: what needs to be built
Use tricks to make it run fast E.g., execute multiple instructions simultaneously
Instruction Set Architecture #3 ISA define the processor family
Two main kind: RISC and CISC RISC: SPARC, MIPS, PowerPC, ARM CISC: X86 (or called IA32)
Under same ISA, there are many different processors
From different manufacturers X86 from Intel, AMD and VIA
Different models 8086, 80386, Pentium, Pentium 4
Y86 Processor State
Program Registers Same 8 as with IA32. Each 32 bits
Program registers %eax %ecx %edx %ebx %esi %edi %esp %ebp
Condition Codes Single-bit flags set by arithmetic or logical instructions OF: Overflow ZF: Zero SF: Negative
Condition codes OF ZF SF
Program Counter Indicates address of instruction
Memory Byte-addressable storage array Words stored in little-endian byte order
PC
Memory
Y86 Instructions Format (P259)
1--6 bytes of information read from memory Can determine instruction length from first byte Not as many instruction types, and simpler encoding than with IA32
Each accesses and modifies some part(s) of the program state
Errata: JXX and call are 5 bytes long.
Encoding Registers Each register has 4-bit ID
%eax %ecx %edx %ebx 0 1 2 %esi %edi %esp %ebp
6 7 4 5
Same encoding as in IA32, but IA32 using only 3-bit ID
Register ID 8 indicates no register
Will use this in our hardware design in multiple places
Instruction Example Addition Instruction
Generic Form addl rA, rB 6 0 rA rB
Encoded Representation
Add value in register rA to that in register rB
Store result in register rB Note that Y86 only allows addition to be applied to register data
Set condition codes based on result
Instruction Example Addition Instruction
Generic Form addl rA, rB 6 0 rA rB
Encoded Representation
e.g., addl %eax,%esi Two-byte encoding
Encoding: 60 06
First indicates instruction type Second gives source and destination registers
Arithmetic and Logical Operations
Instruction Code Function Code Add addl rA, rB 6 0 rA rB
Subtract (rA from rB)
subl rA, rB 6 1 rA rB
Refer to generically as OPl Encodings differ only by function code
Low-order 4 bites in first instruction word
And andl rA, rB 6 2 rA rB
Exclusive-Or xorl rA, rB 6 3 rA rB
Set condition codes as side effect Notice: no multiply or divide operation
Move Operations rrmovl rA, rB 2 0 rA rB irmovl V, rB 3 0 8 rB V
Jump Instructions Jump Unconditionally jmp Dest 7 0 Dest
Jump When Less or Equal jle Dest 7 1 Dest Jump When Less jl Dest 7 2 Jump When Equal je Dest 7 3 Jump When Not Equal jne Dest 7 4 Dest Dest Dest
Jump When Greater or Equal jge Dest 7 5 Dest Jump When Greater jg Dest 7 6 Dest
Refer to generically as jXX Encodings differ only by function code Based on values of condition codes Same as IA32 counterparts Encode full destination address Unlike PC-relative addressing seen in IA32
Y86 Program Stack
Stack Bottom Region of memory holding program data Used in Y86 (and IA32) for supporting procedure calls Stack top indicated by %esp Increasing Addresses
Address of top stack element
Stack grows toward lower addresses
Top element is at lowest address in the stack When pushing, must first decrement %esp stack pointer When popping, increment stack pointer
Stack Top
Stack Operations pushl rA a 0 rA 8
Decrement %esp by 4 Store word from rA to memory at %esp Like IA32
popl rA b 0 rA 8
Read word from memory at %esp Save in rA Increment %esp by 4 Like IA32
Subroutine Call and Return
call Dest 8 0 Dest
Push address of next instruction onto stack Start executing instructions at Dest Like IA32 ret 9 0
Pop value from stack Use as address for next instruction Like IA32
Miscellaneous Instructions nop 0 0
Dont do anything halt 1 0
Stop executing instructions IA32 has comparable instruction, but cant execute it in user mode We will use it to stop the simulator
