------------------------------------------------------------- Author: http://www.teahlab.
com/ --- Circuit: Two-Four-Decoder with Enable --- Structure: --From a basic gates perspective, a 2-to-4 decoder with -Enable is constituted of four NAND gates and three -Inverters. When we speak of structural design in -VHDL, we mean precisely the description of a circuit -by presenting its constituent components and -interconnecting wires. The following VHDL program is -a structural design of the 2-to-4 decoder. As such -the circuit is designed in two stages: --In stage one we define the basic entities: AND, NOT. -In stage two we use the basic entities to construct -the decoder. --One of the advantages of structural designs is that -from the VHDL program you can tell what the physical -circuit looks like. --It is very important to learn structural design (RTL) -strategies because as your assignments become larger -and larger, knowledge of register transfer level -(RTL) design strategies become indispensable. ------------------------------------------------------------- This is the AND gate library ieee; use ieee.std_logic_1164.all; entity nandGate is port( A, B, C : in std_logic; F : out std_logic); end nandGate; architecture func of nandGate is begin F <= not (A and B and C); end func; --*============================ -- This is the NOT gate library ieee; use ieee.std_logic_1164.all; entity notGate is port( inPort : in std_logic; outPort : out std_logic); end notGate; -architecture func of notGate is begin outPort <= not inPort; end func; --*========================*======================= -Now we write the definition for the 2-to-4 Decoder
library ieee; use ieee.std_logic_1164.all; -entity Decoder_2to4_E is port( A0, A1, E : in std_logic; D0, D1, D2, D3 : out std_logic); end Decoder_2to4_E; -architecture func of Decoder_2to4_E is component nandGate is --import AND Gate entity port( A, B, C : in std_logic; F : out std_logic); end component; component notGate is --import NOT Gate entity port( inPort : in std_logic; outPort : out std_logic); end component; signal invA0, invA1,invE : std_logic; begin GI1: notGate port map(A0, invA0); GI2: notGate port map(A1, invA1); GI3: notGate port map(E, invE); GA1: nandGate port map(invA0, invA1, invE, D0); GA2: nandGate port map(A0, invA1, invE, D1); GA3: nandGate port map(invA0, A1, invE, D2); GA4: nandGate port map(A1, A0, invE, D3); end func; ---------------------------------------------------------END ---------------------------------------------------------END
