Industry Academia Conclave - 2025
AI/ML-Powered FPGA Design & Simulation
Hackathon
Organized by NIT Jamshedpur in collaboration with VLSI FOR ALL
Problem Statements
& Instructions Booklet
FPGA Visionary
(Hardware ML Acceleration)
Logic Forge
(RTL Design Challenge)
Neuro Edge
(TinyML + Embedded AI)
Silicon Sprint
(High-Speed Digital Design)
Circuit Intelligence
(FPGA + AI Co-Design)
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GENERAL INSTRUCTIONS
This hackathon is organized by VLSI For All under the theme
AI/ML-Powered FPGA Design & Simulation.
Each participant must submit their final design, RTL code,
simulation results, and reports before the deadline.
Use Verilog/VHDL/SystemVerilog for RTL design unless otherwise
specified.
Python, MATLAB, or other ML frameworks may be used for model
training where required.
Plagiarism is strictly prohibited. Submissions must be original.
FPGA boards may be simulated; physical boards are optional.
Follow the problem statement requirements carefully. Points will
be awarded based on completion, innovation, and correctness.
Judges’ decision will be final.
HACKATHON RULES
Time Duration: Participants must submit within the allocated
hackathon window.
Team Size: Individual participation or teams of up to 3 members.
Evaluation Criteria:
- Technical Accuracy
- Innovation & Optimization
- RTL Code Quality
- Simulation & Reporting
- ML Pipeline Correctness (if applicable)
Bonus points for low-power design, modularity, documentation,
and clean architecture.
Any attempt to violate rules will lead to disqualification
Contact Emails: info@[Link]
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PROBLEM STATEMENTS
1. FPGA-Based Transport Safety Monitoring System
Using ML
Build an FPGA system that monitors driver behavior & road
conditions using sensor fusion and ML inference.
Requirements include a simulated dataset (acceleration, steering
angle, and braking patterns).
Anomaly detection ML model, real-time thresholding, emergency
trigger logic, and priority-interrupt
hazard handling.
Output: RTL + ML training pipeline + safety-event report.
2. AI-Driven Traffic Congestion Prediction & FPGA-
Based Signal Controller
Design a hybrid AI-ML + FPGA-based system to predict traffic
congestion and dynamically adjust signal timing.
Requirements: Dataset creation, ML congestion prediction, FPGA
timing control, emergency overrides, deterministic fail-safe mode.
Output: ML model + RTL + simulation waveforms
3. Hardware Neural Network Accelerator
(Without IPs)
Build a 3-layer NN accelerator using custom activation logic, weight
storage, and configurable datapaths. Support runtime model
swapping via UART.
Output: RTL + Python host interface + test patterns.
For any queries, 9643070368.
4. FPGA-Based Speech Recognition System
(MATLAB + VHDL)
Create a simple ASR system with MATLAB coefficient generation and
VHDL/Verilog hardware implementation. Include an energy-efficient
preprocessing pipeline.
Output: FPGA demo + MATLAB scripts.
5. AI-Powered Power Management System for
FPGA-Enabled Medical Devices
Develop ML-based workload prediction and FPGA-controlled power
scaling (voltage islands, clock domains).
Output: ML integration + RTL power controller.
6. Explainable ML Framework for RTL Timing
Prediction
Create an RTL dataset, extract features (nodes, depth, fan-out),
apply SHAP/LIME, and predict timing slack.
Target accuracy: <10% error. Output: Jupyter notebook +
interpretation charts.
7. Real-Time FPGA–TinyML Speech Command
Recognition
Build a dataset (5–7 commands), implement FPGA FFT/MFCC, and
deploy a TinyML classifier.
Output: RTL + ML model + accuracy report.
For any queries, 9643070368.
8. Multi-Core Soft Processor Cluster With
Deterministic Memory Arbitration
Design 3–5 custom soft processors with deterministic arbitration
(TDMA/RR/FP) and deadlock prevention.
Output: RTL + testbenches + trace logs.
9. Bit-Serial Neural Computation Engine Without
MAC Units
Build a bit-serial computation engine with no DSPs/MACs. Must
support one hidden layer and streaming data.
Output: RTL + timing report + resource analysis.
10. Adaptive FPGA Architecture for Dynamic Power
Governance
Implement dynamic clock scaling, logic gating, and biomedical
real-time signal processing using the RTL power-state machine.
Output: RTL + dataset + power-profiling report.
For any queries, 9643070368.
IMPORTANT DATES
23 Nov 25 Inauguration
24 Nov 25 Problem Selection
6 Dec 25 Final Submission
8 Dec 25 Result
13 Dec 25 Presentation
SUBMIT REPORT ON
vlsiforallcareer@[Link]
For any queries, 9643070368.
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