RVS TECHNICAL CAMPUS – COIMBATORE

KANNAMPALAYAM, COIMBATORE-641402
DEPARTMENT OF B. E. COMPUTER SCIENCE AND ENGINEERING (ARTIFICIAL
INTELLIGENCE AND MACHINE LEARNING)
ACADEMIC YEAR 2024-2025
LESSON PLAN LTPC
3 0 0 3
Subject Name: Digital Principles and Computer Organization
Subject Code : CS3351 CLASS / SEM: II CSE/ IIISEM
Staff In-Charge: [Link]
GENERAL OBJECTIVES:

The student will be able to:

 To analyze and design combinational circuit
 To understand the basic structure and operation of a digital computer
 To analyze and design sequential circuits
 To study the design of data path unit, control unit for processor and to familiarize with the hazards
 To understand the concept of various memories and I/O interfacing
COURSE OUTCOMES:

CO’S Course Outcome Knowledge

Level
CO1 Design various combinational digital circuits using logic gates K3
CO2 Design sequential circuits and analyze the design procedures K6&K4
State the fundamentals of computer systems and analyze the
CO3 K4
execution of an instruction
CO4 Analyze different types of control design and identify hazard. K4
Identify the characteristics of various memory systems and I/O
CO5 K3
communication.

COURSE OUTCOME MAPPING WTH PROGRAM OUTCOME:

CO’S PO PO PO PO PO PO PO PO PO PO PO PO PSO PSO

1 2 3 4 5 6 7 8 9 10 11 12 1 2
CO1 3 3 3 3 3 2 1 1 1 1 2 3 2 3
CO2 3 3 3 3 2 1 1 1 1 1 2 3 1 2
CO3 3 3 3 3 2 2 1 1 1 1 2 3 2 3
CO4 3 3 3 3 1 1 1 1 1 1 1 2 1 3
CO5 3 3 3 3 1 2 1 1 1 1 1 2 1 2
Overall
Correlati 3 3 3 3 1.8 1.6 1 1 1 1 1.6 2.6 1.4 2.6
on

Mapping Correlation level:

3-Substantial (Highly Relevant) 2-Moderate (Medium) 1-Slight (Low)

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 UNIT- I
COMBINATIONAL LOGIC
Unit wise objectives:
 To familiar with various combinational logic circuits.

Methodology
Relevant COs

/ Techniques

Resources
Required

Teaching
Cognitive

referred
Highest
Hours
[Link].

Topic Objective(s) of the

Level
Topic

To review the
Combinational 1
1 Introduction of CO1 K1 GB T1,R3
Circuits combinational circuits.
To simply two variable,
K-map three variable, four 1
2 CO1 K2 GB T1,R3
simplifications variable Boolean
functions
To analyze and design
Analysis and Design 1
3 logic diagram ,Boolean CO1 K4 GB T1,R3
procedures functions and truth table
To know the possible
4 Binary Adder elementary operations of 2 CO1 K2 GB T1,R3
Binary Adder
To know the possible
5 Binary Subtractor elementary operations of 1 CO1 K2 GB T1,R3
Binary Subtractor
Decimal Adder To understand the
6 functions of Decimal 1 CO1 K2 GB T1,R3
Adder.
Magnitude To design single and 4 Bit 1
7 Magnitude comparator CO1 K4 GB T1,R3
Comparator
Decoder – Encoder To realize of Boolean
8 function using Decoder 1 CO1 K4 GB T1,R3
and Encoder .
Multiplexers – To Implement Boolean
Demultiplexers Function using 1
9 CO1 K4 GB T1,R3
Multiplexers and
Demultiplexers
Lab Session
Verification of To Verify of
MANUA
1 Boolean theorems Boolean theorems using 2 CO1 K3 DEMO
L
using logic gates logic gates
Design and To Design and
implementation of implementation of
MANUA
2 combinational combinational 4 CO1 K3 DEMO
L
circuits using gates for circuits using gates for
arbitrary functions. arbitrary functions.
Implementation of 4-
To Implementation of 4-
bit binary MANUA
3 bit binary 4 K3 DEMO
adder/subtractor CO1 L
adder/subtractor circuits.
circuits.
To Implementation of Implementation of code CO1 MANUA
4 2 K3 DEMO
code converters converters L
5 -Implementation of To Implementation of 4 CO1 K3 DEMO MANUA

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 BCD adder, encoder BCD adder, encoder and
L
and decoder circuits decoder circuits
Implementation of Implementation of
MANUA
6 functions using functions using 2 CO1 K3 DEMO
L
Multiplexers Multiplexers
Total hours 9+18
Learning Outcomes:
On learning this unit, the student should be able to:
 Understand the Familiarity with various combinational digital circuits using logic gates
Real – world applicability of the topics under this unit:
Combinational circuits play a crucial role in various electronic devices and systems, such as
calculators, computers, and digital appliances.
Bridging with other subjects/ Applicability in learning other topics / subjects
 Number systems & Boolean Algebra
 Digital logic gates
Scope for extra learning / Assignments / Activities:
[Link]
UNIT- II
SYNCHRONOUS SEQUENTIAL LOGIC
Unit wise objectives:
 To impart to student, the concepts of sequential circuits, enabling them to analyze
Sequential systems in terms of state machines.

Methodology
Relevant COs

/ Techniques

Resources
Required

Teaching
Cognitive

referred
Highest
Hours

Topic Objective(s) of the

Level
Topic
[Link].

Introduction to To Introduction to
1 1 CO2 K1 GB T1,R3
Sequential Circuits Sequential Circuits
Flip-Flops – operation To know types of Flip T1,R3
2 1 CO2 K2 GB
and excitation tables, Flops and its Operations
Triggering of FF To know about the T1,R3
3 1 CO2 K2 GB
Triggering of Flip Flops
Analysis and design of To Analysis and design of
clocked sequential clocked sequential circuits
4 2 CO2 K2 GB T1,R3
circuits Design – Design – Moore/Mealy
Moore/Mealy models, models
State minimization, To understand the State
State assignment, minimization, State
5 1 CO2 K2 GB T1,R3
assignment,

Circuit To Understand Circuit T1,R3

6 1 CO2 K3 GB
implementation implementation
Registers To understand the theory T1,R3
7 and operation of 1 CO2 K3 GB
Registers
Counters. To study about the types T1,R3
8 1 CO2 K2 GB
of Counters
Lab Session
Implementation of To Implementation of MANUA
1 4 CO2 K2 DEMO
Synchronous Counters Synchronous Counters L
Implementation of
To Implementation of MANUA
2 Universal Shift 4 CO2 K2 DEMO
Universal Shift Registers L
Registers
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 Simulator Based study To study Simulator Based MANUA
3 4 CO2 K2 DEMO
of Architecture study of Architecture L
Total hours 9+12
Learning Outcomes:
On learning this unit, the student should be able to:
 Understand the various registers and Counters used in sequential circuit models
Real – world applicability of the topics under this unit:
Commonly used in digital systems to implement timers, counters, and memory elements and are
essential components in digital systems design
Bridging with other subjects/ Applicability in learning other topics / subjects
 Flip Flops and registers
Scope for extra learning / Assignments / Activities:
[Link]
[Link]

UNIT- III
COMPUTER FUNDAMENTALS
Unit wise objectives:
 To Understand the Various Architecture of computer hardware systems
 To Know about the memory location ,Instruction, Computer languages

Methodology
Relevant COs

/ Techniques

Resources
Required

Teaching
Cognitive

referred
Highest
Hours

Topic Objective(s) of the

Level
Topic
[Link].

Functional Units of To describe the

1 a Digital Computer Functional Units of a 1 CO3 K2 GB T2, R1, R2
Digital Computer
Von Neumann To describe the Von T2, R1, R2
2 1 CO3 K2 GB
Architecture Neumann Architecture
Operation and To apply the Operation T2, R1, R2
Operands of and Operands of
3 2 CO3 K3 GB
Computer Hardware Computer Hardware
Instruction Instruction
Instruction Set To know the Instruction T2, R1, R2
4 1 CO3 K4 GB
Architecture (ISA) Set Architecture (ISA
Memory Location, To study the operation of T2, R1, R2
5 Address and the Memory Location, 1 CO3 K4 GB
Operation Address and Operation
Instruction and To describe the T2, R1, R2
6 Instruction Instruction and 1 CO3 K3 GB
Sequencing Instruction Sequencing
Addressing Modes, To know Addressing T2, R1, R2
7 Encoding of Machine Modes, Encoding of 1 CO3 K3 GB
Instruction Machine Instruction
Interaction between To compareInteraction T2, R1, R2
8 Assembly and High between Assembly and 1 CO3 K4 GB
Level Language. High Level Language.
Topic Beyond the Syllabus
9 Modulators and To know the Functions 1 CO3 K2 GB T2

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 of Modulator and
demodulator
Demodulator
Total hours 10
Learning Outcomes:
On learning this unit, the student should be able to:
 Gained knowledge about Functional Units of a Digital Computer
 Real – world applicability of the topics under this unit:
Computers are used at homes for several purposes like online bill payment, watching movies or
shows at home, home tutoring, social media access, playing games, internet access, etc. They provide
communication through electronic mail.
Bridging with other subjects/ Applicability in learning other topics / subjects
 Computer Architecture
Scope for extra learning / Assignments / Activities:
[Link]

UNIT- IV
PROCESSOR
Unit wise objectives:
To Understand the different ways of control design and the types of hazard.

Methodology
Relevant COs

/ Techniques

Resources
Required

Teaching
Cognitive

referred
Highest
Hours

Topic Objective(s) of the

Level
Topic
[Link].

1 Instruction To study the function T2, R1, R2

Execution of Instruction 1 CO4 K2 GB
Execution
2 Building a Data Path To study about 1 T2, R1, R2
CO4 K4 GB
Building a Data
3 Designing a Control To study how to 1 T2, R1, R2
CO4 K4 GB
Unit design a Control Unit
4 Hardwired Control To apply the T2, R1, R2
Hardwired Control of 1 CO4 K3 GB
Processor
5 Microprogrammed To study the T2, R1, R2
Control Microprogrammed 1 CO4 K4 GB
Control
6 Pipelining To study the T2, R1, R2
Functions of 1 CO4 K2 GB
Pipelining
7 Data Hazard To study about the 1 T2, R1, R2
CO4 K2 GB
Data Hazard
8 Control Hazards. To study the Control 1 T2, R1, R2
CO4 K2 GB
Hazards
9 Instruction To study about the T2, R1, R2
Execution Function of 1 CO4 K4 GB
Instruction
Topic Beyond the Syllabus

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 10 Various digital To Know the various
communication digital communication 1 CO4 K2 GB T1, R2, R3
systems systems
Total hours 10
Learning Outcomes:
On learning this unit, the student should be able to:
 To control the data path and control unit through instruction cycle .
Real – world applicability of the topics under this unit:
Used in Instruction parallelism .
Bridging with other subjects/ Applicability in learning other topics / subjects :
 Data Structures
Scope for extra learning / Assignments / Activities:
[Link]

UNIT- V
MEMORY AND I/O
Unit wise objectives:
 To understand the characteristics of various memory systems and I/O communication.

Methodology
/ Techniques
Relevant Cos

Resources
Required

Teaching
Cognitive

referred
Highest
Hours
[Link].

Topic Objective(s) of the

Level
Topic

Memory Concepts To understand the T2, R1, R2

1 and Hierarchy Memory Concepts and 1 CO5 K2 GB
Hierachy
Memory To understand the T2, R1, R2
2 Management functions of Memory 1 CO5 K2 GB
Management
Cache Memories: To understand the T2, R1, R2
Mapping and Cache Memories:
3 Replacement Mapping and 2 CO5 K3 GB
Techniques Replacement
Techniques
Virtual Memory – To apply the Virtual T2, R1, R2
4 DMA Memory and Direct 1 CO5 K3
Memory Access GB
I/O – Accessing I/O: To understand the /O – T2, R1, R2
5 Parallel and Serial Accessing I/O: Parallel 2 CO5 K2 GB
Interface and Serial Interface
Interrupt I/O To study about the T2, R1, R2
6 1 CO5 K3 GB
Interrupts I/O
Interconnection To analyse T2, R1, R2
7 Standards: USB, Interconnection 1 CO5 K3 GB
SATA Standards: USB, SATA
Total hours 9
Topic Beyond the Syllabus

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 The Top Data To discuss the Top Data
T1, R2,
8 Storage Devices on Storage Devices on the 1 CO4 K2 GB
R3
the Market Market
Total hours 10
Learning Outcomes:
On learning this unit, the student should be able to:
• To understand the types of memory management and interconnection standards

Real – world applicability of the topics under this unit:

Application memory management involves supplying the memory needed for a program's objects
and data structures
Bridging with other subjects/ Applicability in learning other topics / subjects :
Computer Memory Organisation
Scope for extra learning / Assignments / Activities:
[Link]

Resources Name of Resources

T1 M. Morris Mano, Michael D. Ciletti, “Digital Design : With an Introduction to the
Verilog HDL,
VHDL, and System Verilog”, Sixth Edition, Pearson Education, 2018.
T2 David A. Patterson, John L. Hennessy, “Computer Organization and Design, The
Hardware/Software Interface”, Sixth Edition, Morgan Kaufmann/Elsevier, 2020.
R1 Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian, “Computer
Organization and Embedded Systems”, Sixth Edition, Tata McGraw-Hill, 2012.
R2 William Stallings, “Computer Organization and Architecture – Designing for
Performance”, Tenth Edition, Pearson Education, 2016.
R3 M. Morris Mano, “Digital Logic and Computer Design”, Pearson Education, 2016

Staff in charge HoD

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