STUDY OF XILINX TOOL WITH FPGA TRAINER KIT
Aim:
To study Xilinx Software with FPGA Trainer kit by implementing a Full
Adder.
Software and Hardware used:
Xilinx ISE Suite, FPGA Trainer kit.
Theory:
Xilinx:
Xilinx software encompasses a range of development tools tailored for designing
and deploying digital logic on FPGAs and SoCs. The key offering, Vivado Design
Suite, is a highly integrated environment that supports the entire design flow from
concept to implementation. It includes tools for:
1. Design Entry: Users can create designs using various methods, including
schematic entry, HDL (VHDL, Verilog, SystemVerilog), and high-level
synthesis (HLS) from C/C++ code.
2. Simulation and Verification: Vivado provides comprehensive simulation tools to
test and verify the functionality of digital designs before implementation, ensuring
they meet specified criteria.
3. Synthesis: The software converts high-level designs into optimized gate-level
implementations tailored for Xilinx FPGAs, focusing on performance, area,
and power optimization.
4. Implementation: This stage involves placing and routing the design onto the
FPGA fabric, balancing timing constraints and resource utilization to meet
the design specifications.
5. Programming and Debugging: Once the design is finalized, Vivado allows
users to program the FPGA and offers powerful debugging tools like the
Integrated Logic Analyzer (ILA) to observe internal signals in real-time.
FPGA Trainer kit:
An FPGA trainer kit is an educational platform that provides a practical
approach to learning and experimenting with digital logic design and FPGA (Field-
Programmable Gate Array) programming. These kits are equipped with an FPGA chip, which
is a reconfigurable silicon device that can be programmed to perform a wide range of digital
functions, from simple logic gates to complex processing systems. The core of an FPGA
trainer kit is its development board, which includes the FPGA itself along with various
input/output peripherals such as switches, LEDs, displays, and communication interfaces.
This hardware setup allows users to create and test digital circuits by configuring the FPGA
to behave as custom hardware, tailored to specific design requirements. FPGA trainer kits
often come with accompanying software tools that enable users to write, simulate, and
synthesize hardware description languages (HDLs) like VHDL or Verilog. These tools
convert the high-level design into a configuration file that programs the FPGA. The
reconfigurability of FPGAs makes them ideal for educational purposes, as students can
experiment with different designs without needing new hardware.
FULL ADDER:
Full Adder is the adder that adds three inputs and produces two outputs. The
first two inputs are A and B and the third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S which is SUM. The C-OUT
is also known as the majority 1’s detector, whose output goes high when more than one
input is high. A full adder logic is designed in such a manner that can take eight inputs
together to create a byte-wide adder and cascade the carry bit from one adder to another. We
use a full adder because when a carry-in bit is available, another 1-bit adder must be used
since a 1-bit half-adder does not take a carry-in bit. A 1-bit full adder adds three operands
and generates 2- bit results.
The sum (S) of the full-adder is the XOR of A, B, and Cin. Therefore,
Sum, S=A ⊕ B ⊕ Cin= A′B′Cin + A′B C′in+ AB′C′in +ABCin
The carry © is
Carry, C= AB + Acin + Bcin
Fig 1.1 Full Adder Block Diagram
Fig 1.2 Full Adder Circuit
Fig 1.3 Truth Table
Source Code:
module full_adder_d (
input a,b,cin,
output sum,carry
);
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (b & cin) | (cin & a)
; endmodule
Procedure:
Compilation:
a) Click on Xilinx ISE Suite in your computer and open the application.
After opening, click on File -> New Project . A dialog box will appear
, type the required file name. And set the Top level Source Type as
Schematic. Then click Next
Fig 1.4
b) Now, click on the Family and choose Spartan3E, Similarly for the rest
of the choices choose the options as mentioned in the image below.
Then click Next
Fig 1.5
c) After finishing setting up the project, Now select the full adder file in
Hierarchy and right click the file. Then Select New Source. After
Selecting New Source , in this dialog box fill the details as given in the
image. The project name and source name should be same.
Fig 1.6
d)After creating the source file , write the code and save the file. Then in the
View click on Simulation. Then in the processes extract the ISim
Simulator by clicking on the + sign . Then double click on the Behavioral
Check Syntax, if the program contains no error then a green tick mark
will appear as like in the image , otherwise if there is error correct the
error and do the above step again.
Fig 1.7
Simulation:
After compiling, click on Simulate Behavior model, then a window appears as above.
There for the all the three inputs A, B , Cin give leading and trailing edge value and
timeperiods using Force Clock. Then run it to get the above results
Fig 1.8
Fig 1.9
Fig 1.10
Fig 1.11
Fig 1.12
Fig 1.13
Fig 1.14
Implementation:
a) After simulation in the Xilinx , we can go for implementation. To
do this click on the Implementation button in View. Then select the full adder file. In the
processes page extract the design utilites and do all the processes. First Create Schematic
Symbol. And do the remaining
Fig 1.15
Fig 1.16
b) After design utilities, do the processes in the user constraints which
are pre synthesis and post synthesis , which will lead to the a window where enter the pin
numbers for the input and output of full adder which we are going to use in FPGA Trainer
kit under the heading SITE.
Fig 1.17
c) After implementing design process, run the generate programming
file process and generate the progamming file.
Fig 1.18
d) Finally go to the project folder , copy the file which will be named
as our project name with the extension .bit and then open the FPGA_Download folder
which is available in the desktop , there delete the output.bit file and paste the copied file
and renamed the copied file as output.bit . Then run the prog folder, which will implement
our design in the FPGA trainer kit.
Fig 1.19
Synthesis Report:
Fig 1.20
Result:
Thus the Xilinx tool and FPGA Trainer kit is studied by implementing a full adder and
the output is verified successfully.
