Turbo Codes 1. Concatenated Coding System: RS Encoder Algebraic Decoder Layer 2
Turbo Codes 1. Concatenated Coding System: RS Encoder Algebraic Decoder Layer 2
Layer 1
Channel
Fig. 12.1
! Concatenated coding has the multilevel coding structure, illustrated in Fig.12.1 A relatively shot random inner code can be used with MLD to achieve a modest error probability, say a bit-error rate of Pb=10-2, at a code-rate which is near channel capacity. Then a long high-rate algebraic Reed-Solomon outer code can be used along with a powerful algebraic error-correction algorithm to drive down the error probability to a level as low as desired with only a small code-rate loss.
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! For convolutional codes with Viterbi decoding, soft decisions are incorporated easily into the Viterbi decoding algorithms in a very nature way, providing an increase in coding gain of over 2.0 dB with respect to the comparable hard-decision decoder over AWGN channel. However, the convolutional codes cannot be implemented easily at high coding rates. They also have an unfortunate tendency to generate burst errors at the decoder output as the noise level at the input is increased. ! In the concatenated coding system, the convolutional code (with soft-decision Viterbi decoding) is used to clean up the channel for Reed-Solomon code, which in turn corrects the burst errors emerging from the Viterbi decoder.
! By the proper choice of codes the probability of error can be made to decrease exponentially with overall code length at all rates less than capacity. ! Generally, the outer code is more specialized in preventing errors generated by the inner code when it makes a mistake. The inner code can also be a binary block code other than a binary convolutional code. For a hard-limited channel, trellis codes often are selected as inner codes.
where B is the bandwidth of the channel in Hz and S is the average power of the signal. N is the noise power. Shannon bound For BPSK-modulated system, let be the spectral efficiency of the modulation format. It is the average number of information bits transmitted per two-dimensional signaling interval of duration T. If T is normalized an related in terms of bits per second per Hz (b/s/Hz). It follows that S/N = Eb/N0, where Eb is the average energy per information bit. No : noise power spectral density.
For a given spectral efficiency, this expression sets the limit on SNR above which there exist coding schemes that will provide arbitrarily low bit error rate. ! For BPSK, =1, the lower limit on SNR is 1 or 0 dB. ! The maximum spectral efficiency of an AWGN channel
max = log 2 (1 +
S ) N bits / s / Hz
! In the limit as the signal is allowed to occupy an infinity amount of bandwidth, that is, as
max
, one obtains
Shannons 1948 paper entitled A Mathematical Theory of Communication launched the twin fields of Information Theory and Error Control Coding. In this paper, Shannon defined the concept of channel capacity. He then show that, as long as the rate at which information is transmitted is less than the channel capacity, there exist error control codes that can provide arbitrarily high levels of reliability at the receiver output. The prof of this, the Noisy Channel Coding Theorem was existential and not constructive. We were left knowing that nice decoding schemes existed, but had no idea how to construct them. The subsequent fifty years of error control coding have been an effort to achieve this goal. The 1993 paper by C. Berrou, A. Glavieux, and P. Thitimasjshima entitled Near Shannon Limit Error Correcting Coding and Decoding : Turbo Codes has brought us within a hairs
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breadth of achieving Shannons promise. This paper was presented at 1993 IEEE International Conference on Communications in Geneva. In their presentation, Berrou et al claimed that a combination of parallel concatenation an iterative decoding can provide reliable communication at a SNR that is within a few tenth of a dB of the Shannon limit. They show by simulation that turbo codes are capable of achieving a bit-error rate (BER) of 10-5 at an Eb/N0 ratio of just 0.7dB. It appears that the 40-year effort to reach channel capacity was achieved by this latest discovery. However, in order to achieve this level of performance, long block sizes of 65,532 data bits are required. Because of the probability long latency involved with such long block sizes, the original turbo codes are not applicable to most real-time two-way communication systems.
Key Design Innovations of Turbo Coding: (1) parallel concatenated encoding. (2) iterative decoding. Parallel concatenated encoders (PCEs) consist of two or more component encoder (or constituent encoders) for block or convolutional encoders. Iterative decoding : Although, in principle, it is possible to derive the optimal decoder for any given PCE, the result would be an extremely expensive and computationally inefficient system. Iterative decoding is a suboptimal alternative that provides extremely good performance which requiring only a modest level of complexity. The key to the iterative decoder is its exploitation of the component code structure of the PCE. The iterative decoder has a soft-input/soft-output (SISO) component decoder for each of the component decoder in the PCE.
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The decoders take turns operating on the received data, forming and exchanging estimates of the message block. Since these component decoders operate on each others incompletely decoded outputs, they are reminiscent of a turbo charged engine, and hence the name turbo codes. When decoded by an iterative process, turbo codes offer an optimum performance. The way to achieve this decoding is using the principle of Maximum A Posteriori (MAP)
# Note: The iterative decoding scheme is based on
alternately decoding the two constituent codes nearing a soft-input soft-output (SISO) algorithm and transferring the soft information (extrinsic information) to the next decoding stage. The extrinsic information generated in the previous decoding stage will be used as the priori information for the nest decoding stage. This iterative manner is similar to a turbo engine.
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I1
Encoder 1
c 1( i )
IM
Encoder M
(i) M
_ (i )
I1,,IM: interleaver
_ (i )
Cj
Cj
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This encoder structure is called a parallel concatenation because all of the constituent encoders operate on the same set of input bits. For most of applications, only two such encoders are used and the input to the 1st encoder is not interleaved. These Constituent encoders themselves are identical and are usually recursive systematic convolutional encoders (RSC codes). Extra tail bits are added in order to ensure that the constituent convolutional encoders return to the all-zero state at the end of such block. Example : Rate 1/3 turbo encoder
Interleaver
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( c 0i )
m (i )
c 1( i )
Figure 12.29 Example of a non-recursive nonsystematic convolutional encoder
m (i )
( c 0i )
d (i )
c 1( i )
Figure 12.30 Example recursive systematic convolutional encoder
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A convolutional encoder can be used to generate a block code if the internal state of the encoder is known at the beginning and end of the codeword. The usual convention is to initialize the encoder to the all-zero state and then to encoder the data. After the k data bits are encoded, a number of tail bits are added to the encoded word in order to force the encoder block to the all-zero state. The number of tail bits required is on the order of the memory m of the convolutional encoder. A tail of m zeros brings a nonrecursive convolutional encoder back to the all zeros state. Due to the presence of feedback, a tail of zeros does not necessarily bring a recursive convolutional encoder back to the all-zeros state.
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The tail required to bring a recursive convolutional encoder to the all-zero state is found by solving a state-variable equation at the feedback element. For example, in Fig.12.31, the state equation at the feedback element is given by
d ( i ) = m ( i ) d ( i 1) d ( i 2 )
Since one wants to bring the encoder back to the all-zero state, d(i) is set to zero so that one obtains
m ( i ) = d ( i 1) d ( i 2 )
m (i )
( c 0i )
Interleaver
c 1( i )
( c 2i )
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5. Interleaver Design
One key to the effectiveness of turbo coding systems is the interleaver. The interleaver allows the constituent decoders to generate separate estimates of the a posteriori probability (APPs) for a given information symbol based on data sources that are not highly corrected. The interleaver also ensure that the set of code sequences generated by the PCE has nice weight properties, which reduces the probability that the decoder will mistake one codeword for another. Example : (Fig.13.31) A rate 1/3 turbo encoder, which use the example RSC encoder in Fig.12.31 is shown in Fig.12.31. The pesudorandom interleaver in this circuit is used to permute the input bits in such a manner that the two encoders operate
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on the same set of input bits, but with different input sequence to the encoders. In [20] and [21], it is shown that by the proper design of the pesudorandom interleaver, it is possible to force both of the constituent encoders back to all-zero state with a single m-bit tail. The condition on the interleaver is based on the fact that the impulse response of each RSC constituent encoder is periodic with some period given by
P 2m 1
If the feedback polynomial is primitive of degree m, then the impulse response is a maximal length sequence, and equality holds in the above equation. The feedback polynomial for the example (Fig.12.31) encoder is given by
g( X ) = 1 + X + X 2
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that the impulse response of this example constituent RSC encoder is periodic with period p=22-1=3. (From Chapter 9) An interleaver maps an integer 0<l<n+1 onto another integer l0 for 0<l0<n+1. A bit in position l at the input to the interleaver is placed in position l0 at the output of the interleaver. If this mapping function is call a, then the mapping can be expressed by
l 0 = a (l )
A condition for the interleaver [ref.21] that allows both of the RSC encoders to be terminated with the same tail, is the following :
l mod p = a (l ) mod p
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The design condition is best illustrated with example. If we use the example turbo encoder in Fig.12.31 and encode data words of length k = 32, then the interleaver must be capable of encoding blocks of length n = k + m = 34. An interleaver that meets the condition stated above is shown in Table 12.5.
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and
C2
1/2 (as shown in Fig.12.32). Other code rate can be achieved by using additional parity generators and/or different puncturing pattrerns.
( c 0i )
c1(i ) c1'(i )
Interleaver
c1(i )
20
When puncturing is used, the joint effect of the interleaver and multiplexer on the codes = distance properties must be taken into account. It is suggested in [24] that when puncturing is used, the interleaver should be designed in such a manner that even bits are mapped to the even indexed bits and the add indexed bits are mapped to added indexed bits.
21
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a posteriori probability (APP) of the individual bits of the codeword, rather than the ML estimate of the transmitted codeword. For encoder given in Fig.12-32, there are two elementary decoders that are interconnected as Fig.12-33 and Fig.12-34. In Figs.12.33 and 12.34, it is assumed that the information stream C0(i) in Fig.12.32 is received as r0(i), while the parity stream C1(i) is received as r1(i). The received information stream r0 is demultiplexed into the received parity-check bits r1(i) and r2(i), corresponding to C1(i) and C2(i), respectively.
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For the encoder given in Fig.12.32, there are two elementary decoders that are interconnected as shown in Fig.12.33 and Fig. 12.34.
r
(i ) 1
Interleaver (I2)
r2( i )
Fig. 12.33 Initialization stage
r0( i )
r1( i )
Soft-in / Soft-out MAP (DEC1) Interleaver (I2)
r2( i )
Soft-in / Soft-out MAP (DEC2)
r1( i )
De-interleaver
r2( i )
( I 31 )
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In Fig12.33. (Initialize stage) The information stream C0(i) is received as r0(i), while the parity stream C1(i) is received as r1(i). r1 is demultiplexed into r1(i) and r1(i), corresponding to C1(i) and C1(i), respectively. The parity bits r1(i) is sent to DEC1 and r1(i) are sent to DEC2. DEC1 produces a soft decision which is based on its received parity bits r1(i) along with the received information stream r0(i). DEC2 uses the received parity bits r2(i) along with the interleaver soft decision from DEC1 to produce a soft decision of its own.
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Fig 12.34 (Iteration stage) In order to find an estimate that approaches the MAP estimate, the information produced by the two elementary decoders must be shared with one another. In Fig12.34. The soft-decision of DEC2 is de-interleaved by I2-1 and re-introduced as the input to DEC1. DEC1 once again produces a soft estimate that interleaved by I2 and feedback into DEC2. As the number of these iterations approaches infinity, the estimates MAP solution. In practice, the number of iteration needs only to be about 18, and in mamy cases, as few as 6 iterations provide satisfactory performance.
^ (i )
r1
and
^ (i )
r2
at the output
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Note: The elementary decoders in Fig.12.34 used the modifier BJCR algorithm. The modified BCJR algorithm suffers from a complexity that is significantly higher that that the Viterbi algorithm Effects have been under way to find reduced-complexity elementary decoders. Modification of the Viterbi algorithm, such as soft-output Viterbi Algorithm (SOVA) seems most promising.
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