COMSATS University Islamabad, Lahore Campus

Department of Electrical Engineering

EEE231 –Electronics-I
Lab Manual for FALL 2025& Onwards

Lab Resource Person

Ms. Arfa Tariq

Theory Resource Person

Dr. Asim Ali Khan

Supervised By
Dr. Nadeem Rafique

Name: Registration Number: CUI/ - - /LHR

Program: Batch:

Semester
Revision History

Date
S. No. Activity Performed by
(MM/YYYY)
Engr. Saad
1 Lab Manual Preparation 01/2015 Aslam/Engr. Sara
Sajid
09/2015 Dr. Asim Ali Khan/
2 Lab Manual review
Dr. Naeem Awais
Engr. Talha Raheem/
3 Lab Manual Modifications 09/2017 Engr. Ramsha
Bukhari
4 Lab Manual Review 10/2017 Dr. Abbas Javed
Engr. Salman Javid/
5 Lab Manual Format Changes 09/2018 Engr. Ghazala
Mushtaq
Dr. Muhammad
Yaqoob Javed/Dr.
6 Lab Manual Review 10/2018
Muhammad Naeem
Shahzad
Abubaker Shakoor/
Ms. Nisma Saleem
7 Layout modifications 02/2020

Ms. Amna Arif

8 Lab Manual Modifications 09/2021 Mr. Ali Raza
Arfa Tariq

9 Lab Manual Modification 10/2022 Ms. Arfa Tariq

Ms. Ghazala Mushtaq
Mr. Ali Raza
Mr. Nesrum Inallah
10 Lab Manual Review 10/2022 Dr. Asim Ali Khan
Dr, Muhammad
Nadeem Rafique
Dr. Masood Ahmad
11 Lab Manual Modifications 09/2023 Engr Ayesha Ali
Engr Amna Arif
Preface
This manual is intended for use in semiconductor devices course namely Electronics-I. The manual contains
sufficient exercises for a typical 15-week course using a three-hour practicum period. The topics cover three
major portions namely Diodes and its applications, Bipolar Junction Transistors and Field Effect Transistors.
For equipment, each lab station includes a dual adjustable DC power supply, a dual trace oscilloscope, a
function generator and a quality DMM. For components, a selection of standard value ¼ watt carbon film
resistors ranging from a few ohms to a few mega-ohms is required along with an array of typical capacitor
values. The students are expected to design and test their circuit on breadboard using these components as per
the requirements of each experiment.
Each exercise begins with an Objective and a Theory Overview. The Equipment List follows with space
provided for serial numbers and measured values of components. Schematics are presented next along with the
step-by-step procedure. Many exercises include sections on troubleshooting and design. All data tables are
grouped together, typically with columns for the theoretical and experimental results, along with a column for
the percent deviations between them. Finally, a group of appropriate questions are presented.
Books
Textbooks
1. Electronic Devices & Circuit Theory by Robert L. Boylestad, (Eleventh Edition).
2. Electronic Devices by Floyd, (Sixth Edition).
Learning Outcomes
Theory CLOs
After successfully completing this course, the students will be able to:
1. Explain structure and operation of electronic devices, particularly diodes, Bipolar Junction Transistors
(BJTs), and Field-Effect Transistors (FETs) based on semiconductor theory.(PLO1-C2)
2. Explain, analyze and design simple dc and ac circuits containing diodes, BJTs and FETs using
standard circuit analysis techniques.(PLO3-C5)

Lab CLOs
After successfully completing this course, the students will be able to:

3. Design simple dc and ac circuits containing diodes, BJTs and FETs using standard circuit analysis
techniques.(PLO3-C5)
4. Construct dc and ac circuits containing diodes, BJTs and FETs and measure their input and output
voltages and currents using breadboard, digital multimeter (DMM), digital storage oscilloscope (DSO)
and simulation tools. (PLO5-P3)

CLOs – PLOs Mapping

PLO
PLO1

PLO2

PLO3

PLO5

CLO Cognitive Domain Affective Domain Psychomotor Domain

CLO1 x C2

CLO2 x C5
CLO3 x C5

CLO4 x P3
Lab CLOs – Lab Experiment Mapping
Lab

Lab10

Lab11

Lab12
Lab1

Lab2

Lab3

Lab4
Lab5

Lab6

Lab7

Lab8

Lab9
CLO

CLO4 P2 P2 P2 P3 P3 P3 P2 P2 P2 P3 P3 P3
P3

Grading Policy (Project Lab [PL])

Lab Assignments:
i. Lab Assignment 1 Marks (Lab marks from Labs 1-3)
ii. Lab Assignment 2 Marks (Lab marks from Labs 4-6) 25%
iii. Lab Assignment 3 Marks (Lab marks from Labs 7-9)
iv. Lab Assignment 4 Marks (Lab marks from Labs 10-12)
Lab Mid Term = 0.5*(Lab Mid Term exam) + 0.5*(average of lab
25%
evaluation of Lab 1-6)
Lab Terminal = 0.2*(Lab Project) +0.3*(Lab Terminal Exam)
+0.375*(average of lab evaluation of Lab 7-12) + 0.125*(average 50%
of lab evaluation of Lab 1-6)

Total (lab) 100%

The minimum pass marks for both lab and theory shall be 50%. Students obtaining less than 50%
marks (in either theory or lab, or both) shall be deemed to have failed in the course. The final marks
would be computed with 75% weight to theory and 25% to lab final marks.
List of Equipment

S.NO NAME OF EQUIPMENT

Analog / Digital Trainers

1
A-Tek (Model AT-700) (ULT-3000)
Function Generators
2
Load Star (Model FG-2100A)
DC Power Supplies
3
(Model DF1730SL3A) 0-30Vdc 3A
Multimeter Digital
4
Model M-3900 & UT55
LCR Meter
5
TECPEL (LCR-612)
DIGITAL OSCILLOSCOPES
6
INSTEK (GDS-1052-U)
ANALOG OSCILLOSCOPES
7
(Model GOS-620)
8 Soldering & Desoldering Station
Curve Tracer
9
QT4812A

Software Resources
OrCAD PSpice®
Laboratory Guidelines (Laboratory procedures)
Every week before lab, each student should read over the laboratory experiment and work out the various
calculations, etc. that are outlined in the pre-lab.
 Return parts and jumper wires to correct bins when you are finished with them.
 Do not put suspected defective parts back in the bins. Give them to the Lab Technician for testing or
disposal.
 Report all equipment problems to Lab Instructor or Lab Technician.
 Most experiments have several parts; students must alternate in doing these parts as they are expected
to work in group.
 Each student must have a laboratory notebook. The notebook should be a permanent document that is
maintained and witnessed properly, and that contains accurate records of all lab sessions.
  Laboratory and equipment maintenance is the responsibility of not only the Lab Technician, but also
the students. A concerted effort to keep the equipment in excellent condition and the working
environment well-organized will result in a productive and safe laboratory.

Safety in the Laboratory

To minimize electric shock hazard, the experiments are designed for low voltage; however, one should never
assume that electric circuits are safe. Few milliamps of current through the body can be lethal. For your safety
you must follow safety rules particularly:
 Turn off power before working on circuits.
 Know the location of the emergency power-off switch.
 Make sure that the transformers and equipment are plugged into utility lines, have no exposed wiring.
Check with the instructor if you are not certain about the procedure.
 Take care when using power supplies, which may be low voltage but can supply currents in the
ampere range. Shorting such a supply can led to a serious burn as high currents arc and can ignite
flammable material. This is precisely why a car battery needs to be treated with respect. The hundreds
of amps a battery can supply are sufficient to cause serious burns.
 The equipment is heavy enough to be generally stable on the bench. Be sure to keep the equipment
away from the edges of the benches to avoid having a piece of equipment fall off the bench. Besides
endangering people who might be struck, falling equipment endangers everyone in vicinity by stressing
the power cords, possibly causing a line short or live fault on the equipment, not to mention damage to
the expensive lab equipment. In general, electronic equipment does not survive harsh treatment.
Laboratory Notebook
The laboratory notebook is a record of all work pertaining to the experiment. This record should be sufficiently
complete so that you or anyone else of similar technical background can duplicate the experiment and data by
simply following your laboratory notebook. Record everything directly into the notebook during the
experiment. Do not use scratch paper for recording data. Do not trust your memory to fill in the details at a
later time.

GUIDELINES FOR LABORATORY NOTEBOOK

• State the objective of the experiment.
• Draw the circuit diagram and mention the values of resistances etc. which are used.
• Make a note of all the measuring instruments you have used.
• Mention the formulas used.
• Create a table and write down the readings, including the units.
• Show all your calculations neatly and SYSTEMATICALLY. Do this is an organized manner.
• Attach graph if any.
• Be concise. Complete sentences are not necessary as long as the context is clear.
• If mistakes are made, they should not be erased. Just bracket them and make a short note explaining
the problem.
• Make entries as the lab progresses; don't assume you can fill it in later. The instructor will ask to see it
during the lab.
• Date every page.
• All-important results must be underlined.
• Attach simulation and hand calculation to your notebook.
 • Draw the figure using pencil before you come to the lab so that you can make corrections to it in case
you need to do so by erasing and re drawing. This will ensure tidy and neat work.
• Prepare the READING TABLE using pencil and ruler and not just by sketching lines. Sketching gives
rise to crooked lines and gives the lab notebook a haphazard look.
• Take a few short notes (2-3 lines), which explains some of the problems you encountered while doing
the experiment. This will help you write better reports.
General Lab Report Format
Following the completion of each laboratory exercise in Engineering courses, a report must be written and
submitted for grading. The purpose of the report is to completely document the activities of the design and
demonstration in the laboratory. Reports should be complete in the sense that all information required to
reproduce the experiment is contained within. Writing useful reports is a very essential part of becoming an
engineer. In both academic and industrial environments, reports are the primary means of communication
between engineers.
There is no one best format for all technical reports but there are a few simple rules concerning technical
presentations which should be followed. Adapted to this laboratory they may be summarized in the following
recommended report format:
• Titlepage
• Introduction
• Experimental Procedure
• Experimental Data
• Discussion
• Conclusions
Detailed descriptions of these items are given below.
• Title Page:
The title page should contain the following information.
• Your name
• ID
• Course number (including section)
• Experiment number and title
• Date submitted.
• Instructors Name
• Introduction:

It should contain a brief statement in which you state the objectives, or goals of the experiment. It should
also help guide the reader through the report by stating, for example, that experiments were done with three
different circuits or consisted of two parts etc. or that additional calculations or datasheets can be found in
the appendix, or at the end of the report.
• The Procedure
It describes the experimental setup and how the measurements were made. Include here circuit schematics
with the values of components. Mention instruments used and described any special measurement
procedure that was used.
• Results/Questions:
This section of the report should be used to answer any questions presented in the lab handout. Any tables
and/or circuit diagrams representing results of the experiments should be referred to and
discussed/explained with detail. All questions should be answered very clearly in paragraph form. Any
unanswered questions from the lab handout will result in loss of points on the report.
 The best form of presentation of some of the data is graphical. In engineering presentations, a figure is
often worth more than a thousand words. There are some simple rules concerning graphs and figures
which should always be followed. If there is more than one figure in the report, the figures should be
numbered. Each figure must have a caption following the number. For example, “Figure 1.1: TTL
Inverter” In addition, it will greatly help you to learn how to use headers and figures in MSWord.
• The Discussion
It is a critical part of the report which testifies to the student’s understanding of the experiments and its
purpose. In this part of the report you should compare the expected outcome of the experiment, such as
derived from theory or computer simulation, with the measured value. Before you can make such
comparison, you may have to do some data analysis or manipulation.
When comparing experimental data with numbers obtained from theory or simulation, make very clear
which is which. It doesn’t necessarily mean that your experiment was a failure. The results will be
accepted, provided that you can account for the discrepancy. Your ability to read the scales may be one
limitation. The value of some circuit components may not be well known, and a nominal value given by
the manufacturer does not always correspond to reality. Very often, however, the reason for the difference
between the expected and measured values lies in the experimental procedure or in not considering all
factors that enter into analysis.
• Conclusion:
A brief conclusion summarizing the work done, theory applied, and the results of the completed work
should be included here. Data and analyses are not appropriate for the conclusion.
Notes
Typed Reports are required. Any drawings done by hand must be done with neatness, using a straight edge
and drawing guides wherever possible. Free hand drawings will not be accepted.
Pre-lab results should be reported in the provided sheets at the end of the manual. It is your responsibility
to obtain the instructor’s signature and to include the signed sheet with your final experiment report. Each
student must submit an individual report based on an individual effort.
Table of Contents
LAB # 1: To explain how to generate a signal using function generator and display using oscilloscope ................................... 12

Objectives................................................................................................................................................................................... 12

Pre-Lab ...................................................................................................................................................................................... 12

In-Lab......................................................................................................................................................................................... 13
Rubric for Lab Assessment ...................................................................................................................................................... 19

LAB #2: To show a diode-based circuit output using hardware tools ....................................................................................... 20

Objectives ................................................................................................................................................................................. 20

Pre-Lab ...................................................................................................................................................................................... 20

In-Lab......................................................................................................................................................................................... 34
Rubric for Lab Assessment ...................................................................................................................................................... 37

LAB #3: To reproduce a half wave rectifier circuit and display the output waveform using hardware tools ............................ 38

Objectives ................................................................................................................................................................................. 38

Pre-Lab ...................................................................................................................................................................................... 38

In-Lab......................................................................................................................................................................................... 39
Rubric for Lab Assessment ...................................................................................................................................................... 46

LAB #4: To Reproduce a full wave rectifier circuit output and display the waveform using hardware tools ............................ 47

Objectives ................................................................................................................................................................................. 47

Pre-Lab ...................................................................................................................................................................................... 47

In-Lab ........................................................................................................................................................................................ 48
Rubric for Lab Assessment ...................................................................................................................................................... 56

LAB # 5: To reproduce a zener diode based circuit and trace its I-V characteristics graph ....................................................... 57

Objectives................................................................................................................................................................................... 57

Pre-Lab ...................................................................................................................................................................................... 57

In-Lab......................................................................................................................................................................................... 58
Rubric for Lab Assessment ...................................................................................................................................................... 62

LAB # 6: To display the output of diode based clipper circuit using hardware tools ................................................................ 63

Objectives ................................................................................................................................................................................. 63

Pre-Lab ...................................................................................................................................................................................... 63

In-Lab ........................................................................................................................................................................................ 64
Rubric for Lab Assessment ...................................................................................................................................................... 72

LAB # 7: To display the output of diode based clamper circuit using hardware tools .............................................................. 73

Objectives ................................................................................................................................................................................. 73
 Pre-Lab ...................................................................................................................................................................................... 73

In-Lab ........................................................................................................................................................................................ 74
Rubric for Lab Assessment ...................................................................................................................................................... 84

LAB # 8: To construct the Emitter Biased BJT circuits and measure quiescent operating point of using hardware tools .......... 85

Objectives................................................................................................................................................................................... 85

Pre-Lab ...................................................................................................................................................................................... 85

In-Lab ........................................................................................................................................................................................ 85
Rubric for Lab Assessment ...................................................................................................................................................... 88

LAB # 9: To construct the Voltage Divider Biased BJT circuits and measure quiescent operating point of using hardware tools
............................................................................................................................................................................................... 89

Objectives................................................................................................................................................................................... 89

Pre-Lab ...................................................................................................................................................................................... 89

In-Lab ........................................................................................................................................................................................ 89
Rubric for Lab Assessment ...................................................................................................................................................... 92

LAB # 10: To construct a simple JFET biasing circuit and sketch its output and transfer characteristics using digital multimeter
............................................................................................................................................................................................. 115

Objectives................................................................................................................................................................................. 115

Pre-Lab .................................................................................................................................................................................... 115

In-Lab ...................................................................................................................................................................................... 116

Rubric for Lab Assessment .................................................................................................................................................... 119

LAB #11: To construct fixed-biased and self-biased common-source circuit and measure its Q point voltage and current using
digital multimeter ................................................................................................................................................................. 120

Objectives................................................................................................................................................................................. 120

Pre-Lab .................................................................................................................................................................................... 120

In Lab ....................................................................................................................................................................................... 122

Rubric for Lab Assessment .................................................................................................................................................... 125

LAB #12: To construct a voltage-divider biased common-source circuit and measure its Q point voltage and current using
digital multimeter ................................................................................................................................................................. 126

Objectives................................................................................................................................................................................. 126

Pre-Lab .................................................................................................................................................................................... 126

In-Lab ...................................................................................................................................................................................... 127

Rubric for Lab Assessment .................................................................................................................................................... 128
LAB # 1: To explain how to generate a signal using function generator and display
using oscilloscope
Objectives
 To Explain the amplitude and time period of voltage signal using oscilloscope
 To Explain how to generate and measure the amplitude and duration of a voltage signal using function
generator

Pre-Lab

Introduction to Oscilloscope

The oscilloscope is the most important instrument available to the practicing technician or engineer. It permits
the visual display of a voltage signal that can reveal a range of information regarding the operating
characteristics of a circuit or system that is not available with a standard multi-meter. At first glance the
instrument may appear complex and difficult to master. Be assured, however, that once the function of each
section of the oscilloscope is explained and understood and the system is used throughout a set of experiments,
your expertise with this important tool will develop quite rapidly. In addition to the display of a signal, it can
also be used to measure the average value, rms value, frequency, and period of a sinusoidal or non-sinusoidal
signal. The screen is divided into centimeter divisions in the vertical and horizontal directions. The vertical
sensitivity is provided (or set) in volts/div, while the horizontal scale is provided (or set) in time (s/div.). If a
particular signal occupies 6 vertical divisions and the vertical sensitivity is 5mV/div. The magnitude of the
signal can be determined from the following equation:

Amplitude of signal voltage = voltage sensitivity (V/div.) x deflection (div.)

VS = (5mV/div)(6 div) = 30mV

If one cycle of the same signal occupies 8 divisions on the horizontal scale with horizontal sensitivity of
5µs/div., the period and frequency of the signal can be determined using the following equations:

Period of signal voltage = horizontal sensitivity(s/div) x deflection (div)

T = (5µs/div)(8 div) = 40µs
f = 1/T = 1/40µs = 25 kHz
Introduction to Function Generator
A function generator is usually a piece of electronic test equipment used to generate different types of
electrical waveforms over a wide range of frequencies. Some of the most common waveforms produced by the
function generator are the sine, square, triangular and saw-tooth shapes. These waveforms can be either
repetitive or single shot. Integrated circuits used to generate waveforms may also be described as function
generator ICs.
Function generators are used in the development, test and repair of electronic equipment. For example, they
may be used as a signal source to test amplifiers or to introduce an error signal into a control loop.
 Task

Read the Oscilloscope user manual and describe the function and use of each of the following controls or
sections of the oscilloscope in your own words.

a. Vertical and horizontal position controls

b. Vertical Sensitivity:

c. Horizontal sensitivity:

d. Vertical mode selection:

e. AC-GND-DC switch:

f. Calibrate switches:

g. Trigger section:

h. External trigger input:

i. Probe:

Describe one mistake that can damage a multimeter for each of the following measurements:
A. Voltage
B. Resistance
C. Current
State whether propagation of errors can be used to find the uncertainty of:
A. A quantity measured directly using a multimeter.
B. A calculated quantity based on more than one measurement.
C. Both above

In-Lab

Lab Task 1:

Procedure
a. Turn on the oscilloscope and adjust the necessary controls to establish a clear, bright, horizontal
line across the center of the screen. Do not be afraid to adjust the various controls to see their
effects on the display.
b. Connect the function generator to, one vertical channel of the oscilloscope and set the output of
the generator to a 1000 Hz sinusoidal waveform.
c. Set the vertical sensitivity of the scope to 1 V/div. and adjust the amplitude control of the function
generator to establish a 4 V peak to-peak (p-p) sinusoidal waveform on the screen.
Horizontal Sensitivity

a. Determine the period of the 1000 Hz sinusoidal waveform in milliseconds using the equation T =
1/f. Show all work for each part of the experiment. Be neat.
T (calculated) =_ _

b. Set the horizontal sensitivity of trio scope to 0.25 ms/div. Using the results of Part 2(a) predict and
calculate the number of horizontal divisions required to properly display one full cycle of the 1000
Hz signal.
Number of divisions (calculated) =____

c. Use the oscilloscope measure the number of required divisions and insert below. How does the
result compare to the calculated number of divisions?
Number of divisions (measured) = ____ _
d. Change the horizontal sensitivity of the oscilloscope to 0.5 ms/div without touching any of the
controls of the function generator. Using the results of Part 2(a) how many horizontal divisions will
now be required to display one full cycle of the 1000 Hz signal?
Number of divisions (calculated) =___ _

e. Using the oscilloscope measure the number of required divisions and insert below. How does the
result compare to the calculated number of divisions?
Number of divisions (measured) =___
f. Change the horizontal sensitivity of the oscilloscope to I ms/div without touching any of the controls
of the function generator. Using the results of Part 2(a), how many horizontal divisions will now be
required to display one full cycle of the 1000 Hz signal?
Number of divisions (calculated) = ___
g. Using the oscilloscope measure the number of required divisions and insert below. How does the
result compare to the calculated number of divisions?
Number of divisions (measured) =___

h. What was the effect on the appearance of the sinusoidal waveform as the horizontal sensitivity was
changed from 0.2 ms/div. to 0.5 ms/div. and finally to 1 ms/div.

i. Did the frequency of the signal on the screen change with each horizontal sensitivity? What
conclusion can you draw from the results regarding the effect of the chosen horizontal
sensitivity on the signal output of the function generator?

j. Given a sinusoidal waveform on the screen, review the procedure to determine its frequency. Develop
a sequence of steps to calculate the frequency of a sinusoidal waveform appearing on the screen of
an oscilloscope.
Lab Task 2: Vertical Sensitivity:

a. Do not touch the controls of the function generator but set the sensitivity of the scope to 0.2ms/div. and
the vertical sensitivity to 2 V/div. Using this latter sensitivity, calculate the peak-to-peak value of the
sinusoidal waveform on the screen by first counting the number of vertical divisions between peak
values and multiplying by the vertical sensitivity.

Peak-to-peak value (calculated) =___ _

b. Change the vertical sensitivity of the oscilloscope to 0.5 V/div. and repeat Part2(a)
Peak-to-peak value (calculated) =___ _

c. What was the effect on the appearance of the sinusoidal waveform as the vertical sensitivity was
changed from 2 V/div. to 0.6V/div.?

d. Did the peak-to-peak voltage of the sinusoidal signal change with each vertical sensitivity? .What
conclusion can you draw from the results regarding the effect of changing the vertical sensitivity on
the output signal of the function generator?

e. Can the peak or peak-to-peak output voltage of a function generator be set without the aid of an
auxiliary instrument such as an oscilloscope or DMM? Explain.
Lab Task 3:

a. Make all the necessary adjustments to clearly display a 6000-Hz 6Vp-p sinusoidal signal on the
oscilloscope. Establish the zero volt line at confer of the screen. Record the chosen sensitivities:

Vertical sensitivity=_____

Horizontal sensitivity =__

b. Draw the waveform on Fig. 1.1 carefully noting the required number of horizontal and vertical
divisions. Add vertical and horizontal dimensions to the waveform using the chosen sensitivities listed
above.

GRAPH:

Figure 1.1 Graph for Lab task 4, part (b)

c. Calculate the period of the waveform on the screen using the number of horizontal divisions for a full
cycle as shown.
T (calculated) =__
d. Repeat Part 3(a) for a 200-Hz 0.8 Vp-p sinusoidal waveform on Fig.1.2.
Vertical sensitivity=___
H
orizontal sensitivity=__ _
T (calculated) =___ _

GRAPH:

Figure 1.2 Graph for Lab task 4, part (d)

e. Repeat Fart 3(a) for a 100-kHz 4 Vp-p square wave on Fig. 1.3. Note that a square wave is called for
Vertical sensitivity=___
Horizontal sensitivity=__ _
T (calculated)=___ _

GRAPH:

Fig 1.3 Graph for Lab Task 4, Part (e)

Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: ______________________________ Date: ____________________

LAB #2: To show a diode-based circuit output using hardware tools
Objectives
 To explain the behavior of a diode by constructing a circuit in forward and reverse biased
configuration
 To show and display the response of a diode-based circuit

Pre-Lab

Familiarize yourself with diode

Introduction
Diode is a semiconductor device that, only allow current flow in one direction. The schematic diagram is
shown in Figure 1, where the line denotes cathode or the N-material while the base is the anode or the P-
material. Current flows from P to N or anode to cathode.

Stripe

Cathode Anode

+ -

Figure 2.1 Diode Symbol

There are many specifications for each type of diode, the most important two are :(1) PIV (Peak inverse
Voltage) maximum voltages the diode can tolerate in reverse direction. (2) IF (Forward Current) maximum
forward current though diode when it is conducting.
Diodes have small impedance to current flow in one direction (forward-biased) and large impedance in the
reverse-biased mode. When diodes fail they either short-circuit (pass current in both directions – i.e. low
resistance in both directions) or open-circuit (do not pass current at all). Since the low impedance path is the
one from anode to cathode, one needs to know which end is which.

Diodes are widely used in applications such as mixers, detectors, and protection circuits. In this experiment you
will investigate few applications of diodes such as AND gate, half wave rectifier and Zener limiter. Diode
limiters are wave shaping circuits in that they are used to prevent signal voltage from going above or below
certain levels. Because of this clipping capability, the limiter is also called clipper.

Most modern· day digital multimeters can be used to determine the operating condition of a diode. They have
a scale-denoted by a diode symbol that will indicate the condition of a diode in the forward and reverse-
-bias regions. If connected to establish a ' forward bias condition the meter will display the forward voltage
across the diode at a current- level typically in the neighborhood of 2 mA. If connected to establish a reverse-
bias condition an "OL" should appear on the display to support the open-circuit approximation frequently
applied to this region. If the meter does not have the diode-checking capability the condition of the diode can
also be checked by obtaining some measure of the resistance level in the forward and reverse-bias region.
Both techniques for checking diode will be introduced in the first part of the experiment. The current-volt (I-
V) characteristics of a silicon or germanium diode have the general shape shown in Fig. 2.2. Note the change in
scale for both the vertical and horizontal axes.
In the reverse-biased region the reverse saturation currents are constant from 0 V to the Zener potential. In the
forward-bias region the current increases quite rapidly with increasing diode voltage. Note that the curve is rising
almost vertically at a forward-biased voltage of less than 1 V. 'The forward-biased diode current will be limited
solely by the network in which the diode is connected or by the maximum current or the power rating of the
diode.

Figure 2.2 Diode I-V Characteristics Curve

Tasks
1. Review the INTRODUCTION section above.
2. Simulate the diode characteristic using Pspice for comparison with experimentally measured results.
Determine rd, Vγ, and n for the 1N4004 diode in your diode characteristic plot. Simulate the circuit
shown in Figure 2.3 for the resistor (R) values shown using a DC sweep test (sweep V in and R
simultaneously).
In-Lab

Testing of diode with an analog Multimeter

To verify the diode is good or bad measure a DC forward resistance and DC reverse resistance. Good diode
show low forward resistance and very high reverse resistance. Ratio of reverse and forward resistance should
be 1000:1. If meter needle show deflection, the Red lead with terminal of diode show Cathode and vice versa.

Testing ordinary diode using a digital Multimeter

To check a silicon diode using a digital Multimeter, put the Multimeter selectors witch in the diode check
mode. Connect the positive lead of Multimeter to the anode and negative lead to cathode of the diode. If
Multimeter displays a voltage between 0.6 to 0.7, we can assume that the diode is healthy. This is the test for
checking the forward conduction mode of diode. The displayed value is actually the potential barrier of the
silicon diode and its value ranges from 0.6 to 0.7 volts depending on the temperature.
Now connect the positive lead of Multimeter to the cathode and negative lead to the anode. If the Multimeter
shows an infinite reading (over range), we can assume that the diode is healthy. This is the test for checking the
reverse blocking mode of the diode.

Working of Diode in Forward &Reverse Biasing

Lab Task 1: Forward Bias

+ VR
-

R +

E VD

Figure 2.3
Procedure:
Assemble the circuit on proto board of diode, resister (1 kΩ) and variable power supply in series as given
below.
a. Construct the network in Fig 2.3 with the supply (E) set at 0 V. Record the measure value of resistor.

b. Increase the supply voltage until VR reads 0.1 V. Then measure VD and insert its voltage in Table 2.1.
Calculate the value of the corresponding current ID.
 Table 2.1

E
VR 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 3
VD
ID=
VR/ R

E
VR 4 5 6 7 8 9 10 11 12 13 14 15
VD
ID= VR/
R

c. Sketch the waveform of the voltage across the diode and the current across the diode. This step will
develop the characteristic curve of solid-state conventional diode.

GRAPH:

Figure 2.4
Lab Task 2: Reverse Bias

VR
- +
-
R

E 20V VD

Figure 2.5

Assemble the circuit on proto board of diode, resister and variable power supply in series as mention above.
a. In Fig 2.5 reverse bias condition has been established. Since the reverse saturation current will be
relatively small, a large resistance of 1MΩ is required if the voltage across the resistance is to be of
measurable amplitude. Record the measurable value of R.
b. Measure the voltage VR. Calculate the reverse saturation current from Is=VR (RM||R). The internal
resistance of DMM (RM) is included because of the large amplitude of resistance R. A typical value of
10 MΩ is taken.
RM =
VR (measured) =Is
(calculated) =
Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: ______________________________ Date: ____________________

LAB #3: To reproduce a half wave rectifier circuit and display the output
waveform using hardware tools
Objectives
 To Explain the behavior of a half wave rectifier circuit and display the output

Pre-Lab

Introduction
When AC signal is applied to a forward biased diode. The diode conducts for half positive or negative cycle
and remains off for other half cycle. Diode converts the AC signal to Pulsating DC that can be observed on
oscilloscope screen. The Primary function of half wave rectification is to establish a DC level from a sinusoidal
input signal that has zero average (DC) level. DC voltage level in half wave rectification is equal to 31.8% of

𝑉DC= 0.318 𝑉𝑝𝑒𝑎𝑘

the peak voltage Vm considering the ideal diode.

Vm

Vdc = 0.318Vpeak

0
t
T
Figure 3.1

Tasks
1. Design a half wave rectification circuit using limiting resistor R, load resistor RL and diode. Graphs of
Input voltage vi, output voltage vo , and current IR are shown in Fig. 3.1. Also find the values of
limiting resistor R and load resistor RL.
 vi

10V

-10V

Figure 3.2 Input voltage vi, output voltage vo and current iR

2. Simulate the circuit in Figure 3.2, using Pspice. Apply sinusoidal input voltage with 4V amplitudes
and 1 kHz Frequency. (Double click the VSIN source and change only Vamp and Frequency, and
make all other values zero). Go to analysis → set up choose transient analysis, choose print step—
20ns, Final time----1ms (5 cycles), save and choose Simulate from analysis, you will observe a Probe
Window, Go to Trace →to Add Trace, in that add the input and output traces.(Note: You can also
use voltage Marker to plot the input & output directly).

+
+
2.2KΩ Vo
-
-
Si
Figure 3.3

In-Lab
Lab Task 1

a. Design a half wave rectifier circuit that could completely clip off negative half of input ac signal.
Consider 1000Hz 8 Vp-p sinusoidal input voltage.

b. Plot the sinusoidal input on the graph of Fig 3.3. Determine the chosen vertical and horizontal
sensitivities.
GRAPH:

Figure 3.4

Vertical Sensitivity =
Horizontal Sensitivity =

c. Using the Oscilloscope with the AC-GND-DC coupling switch in the DC position, obtain the voltage
Vo and sketch the waveform on Fig 3.4. Before viewing Vo be sure that to set the Vo = 0V.
 GRAPH:

Figure 3.5

Lab task 2
a. Design a half wave rectifier circuit that could completely clip off positive half cycle of the input
ac signal.

AC
Vi Vo

Figure 3.6
b. Plot the input ac voltage signal in Fig. 3.6. Determine the chosen vertical and horizontal
sensitivities.
GRAPH:

Figure 3.7

c. Using the Oscilloscope with the AC-GND-DC coupling switch in the DC position, obtain the
voltage Vo and sketch the waveform on Fig 3.4. Before viewing Vo be sure that to set the Vo = 0V
GRAPH:

Figure 3.8
Lab Task 3
a. Construct the network of Fig 3.8.Use R=2.2kΩ

VR

R +

AC Vo

Figure 3.9

b. Determine the theoretical output voltage for Fig 3.8 and sketch the waveform on Fig 3.8 for one cycle.
Indicate the maximum and minimum values on the output waveform.
GRAPH:

Fig 3.10

c. Using the oscilloscope with the coupling switch in DC position obtain the voltage V o and sketch the
wave form on Fig 3.10 using the same sensitivities as in Part b.
GRAPH:

Fig 3.11
Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: ______________________________ Date: ____________________

LAB #4: To Reproduce a full wave rectifier circuit output and display the waveform
using hardware tools
Objectives
 To explain the behavior of a full wave rectifier circuit and display its output waveform

Pre-Lab

Introduction
The objective of the lab is to reacquaint you with the fundamentals of AC (alternating current) and DC (direct
current) voltages as well as introduce you to the basics of AC to DC conversion through the use of diode
rectifiers. The first section of the power supply in Figure 4.2, after the AC voltage source, is the transformer.
It is responsible for converting the AC signal from a standard wall outlet down to a 12 VAC signal. Most DC
power supplies maintain a voltage much less than 120 volts, so the transformer stage is necessary to get the AC
source amplitude down to a more reasonable level.
When AC signal is applied to the rectifier circuit the diode D1 and D4 are on for positive half cycle due to
forward bias to produce output as replica of input at the same time, the diodes D2 and D3 remains open due to
reverse bias. When negative half cycle of input signal is applies to the rectifier circuit the diodes D 1 and D4 is
off due to reverse bias but diode D2 and D3 are on due to forward bias. Use capacitor across the load and see
the effect of it. Use voltage regulator LM7805 here for output voltage regulation.

𝑉DC= 0.636 𝑉𝑝𝑒𝑎𝑘

Vm

Vdc = 0.636Vm

0
t
T
Figure 4.1
1. Design full wave bridge rectifier circuit that could generate an output voltage as shown in Fig.4.2.

100V

vi vo

-100V

Figure 4.2
 2. Simulate the circuit in Figure 4.4 in PSpice. Use two VSIN sources instead of center-tap transformer
(as shown in Fig. 4.3). Note: rest of the circuit is same in experimental procedure, so follow
experimental procedure to do PSpice work.

Figure 4.3

In-Lab
Lab Task 1: Threshold Voltage
Choose one of the four silicon diodes you received and determine the threshold voltage, V T using the diode
checking capability of DMM.
VT =
Secondary
Primary
+ D2 D1
120Vrms Vo
12.6 Vrms

3.3kΩ
- D4 D3

Figure 4.4

a. Measure the rms voltage at the transformer secondary using DMM set to AC. Record that rms value
below. Does it differ from the rated12.6V.
Vrms (measured) =
b. Calculate the peak value of secondary voltage using the measured (Vpeak = 1.414Vrms)
Vpeak (calculated)=
c. Sketch the expected output waveform Vo on Fig 4.5. Choose a vertical and horizontal sensitivity
based on the amplitude of the secondary voltage.
GRAPH:

Figure 4.5

Vertical Sensitivity =
Horizontal Sensitivity =

d. Using the Oscilloscope with coupling switch in the DC position obtain the waveform for V o and record
on Fig 4.6. Use the same sensitivities employed in part c and be sure to preset V o = 0V.
GRAPH:

Figure 4.6
Vertical Sensitivity =
Horizontal Sensitivity =

a. How do the waveform of part c and part d compare?

Lab Task 2

a. Determine the DC level of full-wave rectified waveform ofFig.4.6.

VDC (calculated) =

b. Measure the DC level of the output waveform using the DMM and calculate the present difference
between the measured and calculated values.

VDC (measured) =

(% Difference )=

Lab Task 3
a. Replace diode D3 and D4 in Fig 4.4 by 2.2kΩ resistors and forecast the appearance of the output voltage
Vo . Sketch the waveform of Vo on Fig 4.7 and label the magnitude of minimum and maximum
values.

GRAPH:

Figure 4.7
Vertical Sensitivity =
Horizontal Sensitivity

52
b. Sketch the expected output waveform Vo using Oscilloscope in Fig 4.7. Choose a vertical and
horizontal sensitivity based on the amplitude of secondary voltage.

GRAPH:

Figure 4.8

Vertical Sensitivity =
Horizontal Sensitivity =

c. How do the waveform of part a and part b compare?

53
Lab Task 4

a. Determine the DC level of full-wave rectified waveform ofFig.4.8.

VDC (calculated) =

b. Measure the DC level of the output waveform using the DMM and calculate the present difference
between the measured and calculated values.

VDC (measured) =

( % Difference )

54
Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: ______________________________ Date: ____________________

LAB # 5: To reproduce a zener diode based circuit and trace its I-V characteristics
graph
Objectives
 To reproduce a circuit where zener diode behaves as a regulator.
 To trace the I-V graph for a Zener diode

Pre-Lab

Introduction
A zener diode is a special kind of diode which allows current to flow in the forward direction in the same
manner as an ideal diode, but will also permit it to flow in the reverse direction when the voltage is above a
certain value known as the breakdown voltage,"zener knee voltage" or "zener voltage." The device was named
after Clarence Zener, who discovered this electrical property.
Zener diodes are heavily doped silicon diodes that, unlike normal diodes, exhibit an abrupt reverse break-down
at relatively low voltages. The Zener diode is designed to operate in reverse breakdown region. Zener diode is
used for voltage regulation purpose. Zener diodes are designed f or specific reverse breakdown voltage called
Zener breakdown voltage (Vz). The value of Vz depends on amount of doping Zener diodes are available in
various families (according to their general characteristics, encapsulations and power ratings) with reverse
breakdown (Zener) voltages in the range 2.4V to 200 V.

Figure 5.1
Tasks
1. Design a voltage regulator that will maintain an output voltage of 20V across a 1 kΩ load with an
input that will vary between 30V and 50V. That is, determine the proper value of Rs and the maximum
current Izm.
2. Simulate all the circuits in the lab on PSpice.
3. Write down all the calculated values of all lab tasks before coming to the lab.

In-Lab

Lab Task 1: To Plot I-V Characteristics

+ VR -
+
R
E Vz
10 V
Zener
-
Figure 5.2

a. Construct the circuit of Fig 5.1 and set the DC supply to 0 V, use R=100 Ω and record the measured
value ofR.
b. Set the DC supply (E) to the value appearing in the table and measure both V Z andVR.

Table 5.1
E(V) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VZ (V)
VR (V)
IZ= VR/R
(mA)

c. This step will develop the characteristic curve of Zener diode. Since the Zener region is in third
quadrant to complete diode characteristic curve, place a minus sign in front of each level of IZ and VZ
for each data point. With this convention in mind plot the data of the table 5.1 on the graph. Choose
an appropriate scale for IZ and VZ as determined by the range of values for each parameter.
GRAPH:

Figure 5.3

Lab Task 2: Zener as a voltage regulator

a. ConstructthenetworkofFig5.2, use R=1kΩandRL=1kΩ.Recordthemeasurevalueof each

resistor.

+ VR -

+ +
R
E 15V
10 V RL VL
Vz
Zener

- -
Figure 5.4

b. Determine whether the Zener diode is in “on” state that is operating in Zener breakdown
region. For the diode in “on ” state calculate the expected value of VL, VR , IR , IZ ,IL.
VL (calculated ) =
VR (calculated) =
 IR (calculated)=
IL (calculated)=
IZ (calculated)=

c. Energize the network of Fig 5.2 and measure the value of VL,VR , IR , IZ ,IL.
VL ( measured ) =
VR (measured) =
IR (measured) =
IL (measured) =
IZ (measured) =

d. Change RL to 1.2 kΩ and determine whether the Zener diode is in “on” state that is operating
in Zener breakdown region. For the diode in “on ” state calculate the expected value of V L, VR

, IR , IZ , I L.
VL (calculated ) =
VR (calculated) =
IR (calculated) =
IL (calculated) =
IZ (calculated) =

e. Energize the network of Fig 5.2 and measure the value of VL,VR , IR , IZ ,IL.
VL ( measured ) =
VR (measured) =
IR (measured) =
IL (measured) =
IZ (measured) =

f. Change RL to 1.5 kΩ and determine whether the Zener diode is in “on” state that is operating
in Zener breakdown region. For the diode in “on ” state calculate the expected value of V L, VR

, IR , IZ , I L.
VL (calculated ) =
VR (calculated) =
IR (calculated) =
IL (calculated) =
IZ (calculated) =
g. Energize the network of Fig 5.2 and measure the value of V L, VR , IR , IZ ,IL.

VL ( measured ) =
VR (measured) =
IR (measured) =
IL (measured) =
IZ (measured) =
h. Change RL to 2.2 kΩ and determine whether the Zener diode is in “on” state that is operating
in Zener breakdown region. For the diode in “on ” state calculate the expected value of V L, VR
, IR , IZ , I L.
VL (calculated ) =
VR (calculated) =
IR (calculated) =
IL (calculated) =
IZ (calculated) =

i. Energize the network of Fig 5.2 and measure the value of VL,VR , IR , IZ ,IL.
VL ( measured ) =
VR (measured) =
IR (measured) =
IL (measured) =
IZ (measured) =

j. Change RL to 3.3 kΩ and determine whether the Zener diode is in “on” state that is operating
in Zener breakdown region. For the diode in “on ” state calculate the expected value of V L, VR

, IR , IZ , I L.
VL (calculated ) =
VR (calculated) =
IR (calculated) =
IL (calculated) =
IZ (calculated) =

k. Energize the network of Fig 5.2 and measure the value of VL,VR , IR , IZ ,IL.
VL ( measured ) =
VR (measured) =
IR (measured) =
IL (measured) =
IZ (measured) =

l. Determine the minimum value of RL required to ensure that Zener is in “on”state.

RL (calculated ) =
 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: ______________________________ Date: ____________________

62
LAB # 6: To display the output of diode based clipper circuit using
hardware tools

Objectives
 To measure the output dc and ac voltages of diode based series clipper circuit using digital storage
oscilloscope (DSO).
 To measure the output dc and ac voltages of diode based shunt clipper circuit using digital storage
oscilloscope (DSO).

Pre-Lab

Introduction
It is frequently necessary to modify the shape of various waveforms for use in instrumentation, controls,
computation, and communications. Wave shaping is often achieved by relatively simple combinations of
diodes, resistors, and voltage sources. Such circuits are called clippers, limiters, amplitude selectors, or slicers.
Clipper circuits are primarily used to prevent a waveform from exceeding a particular limit, either positive or
negative. For example, one may need to limit a power supply’s output voltage so it does not exceed +5 V. The
most widely used wave shaping circuit is the rectifier, which you have previously studied.
In electronics, a clipper is a circuit design to prevent the output of a circuit from exceeding a predetermined
voltage level without distorting the remaining part of the applied waveform.
Diode clippers could be used at the inputs of small-signal instruments to protect against accidental application
of large input signals. This is a low-current application, so you use signal diodes, not current diodes.
Figure 6.1 shows a positive clipper circuit. As indicated, the output voltage has the entire positive half -cycles
clipped off. The circuit works as follows: During the positive half-cycle of the input voltage, the diode turns on.
For an ideal diode, the output voltage is zero. For an actual diode the output voltage is equal to Vγ, the cut-in
voltage of the diode.
During the negative half-cycle, the diode is reverse-biased and can be approximated by an open circuit. In many
clippers, the load resistor, RL, is much larger than the series resistor, R. In which case, essentially all of the
negative half-cycle voltage appears at the output through voltage-divider action. If RL and R are comparable,
then on the negative half-cycle, the output voltage would be given by
𝑉𝑜 = 𝑝1 = 𝑉𝑝 • (𝑅𝐿 / (𝑅𝐿 + 𝑅))
Since the first Vγ volts are used to begin conduction in the diode, the output signal is clipped near Vγ, rather
than at 0V. If the diode polarity is reversed, the result is a negative clipper that removes the negative half cycle.
In this case, the clipping levels occur near -Vγ.

63
 Figure 6.1 A positive clipper circuit: (a) Sinusoidal input to clipper circuit; (b) A positive clipper circuit;
(c) Output of ideal positive clipper circuit; and (d) Output of actual positive clipper circuit
Tasks
1. Design a clipping circuit with input voltage vi = 40 V p-p that can generate an output voltage vo
as shown in figure6.2.

Figure 6.2 output voltage vo of required clipping circuit

2. Simulate all the circuits in PSpice and perform the transient analysis before coming to the lab.
3. Write down all the calculated values in the lab.

In-Lab

Task 1: Determine Threshold voltage

Determine the threshold voltage for the silicon and germanium diodes using the diode-checking capability of
the DMM or a curve tracer. Round off to hundredths place when recording in the designated space below. If
the diode-checking capability or curve tracer is unavailable assume VT= 0.7 V for the silicon diode and 0.3 V
for the germanium diode.
VT(Si)=

VT(Ge)=

Task 2: Parallel Clippers

64
a) Construct the clipping network of figure 6.3 with R=2.2 kΩ. Record the measured
resistance value of the cell. Note that the input is an 8 VP-P square wave at a frequency
of1000Hz.

Vi
R
4V

+
+
Vp-p =8v

Vo
0 f=1000Hz Vi
T=
t 1 ms
1.5V

-
-4V

Figure 6.3

b) Using the measured values of R, E, and VT calculate the voltage Vo when the applied square wave is
+4V. What is the level of Vo? Show all the steps of your calculations to determine Vo.
Vo (calculated)=

GRAPH:

Figure 6.4

65
c) Repeat part 2(b) when the applied square wave is -4V.

d) Using the results of parts 2(b) and 2(c) sketch the expected waveform for Vo in Fig.6.5

e) Using the sensitivities provided in part 2(d) set the input square wave and record Vo on Fig 6.5 using
the oscilloscope. Be sure to preset the Vo = 0V line using the GND position of the coupling switch
(and the DC position to view the waveform)

GRAPH:

Figure 6.5

How does the waveform of Fig 6.5 compare with the predicted results of Fig 6.4?

f) Reverse the battery of Fig 6.3 and using the measured values of R, E and VT, calculate the level
of Vo for the time interval when Vi=+4V

Vo(calculated) =__
g) Repeat part 2(f) for the time interval when Vi=-4V

66
 VO(calculated) =__
h) Using the results of parts 2(f) and 2(g) sketch the expected waveform for V o using the horizontal
axis of Fig 6.6 as the Vo = 0V line. Use the same sensitivities provided in part2(d).

GRAPH:

Figure 6.6

i) Set the input square wave and record Vo on fig 6.7 using the oscilloscope. Be sure to preset the Vo =
0V line using the GND position of the coupling switch (and the DC position to view the waveform).

j) How does the waveform of Fig 6.6 compare with the predicted results of Fig6.7?

67
GRAPH:

Figure 6.7

Task 3: Series Clippers

a) Construct the circuit of Fig 6.8 using R=1 MΩ. Record the measured resistance value and the DC level
of the D cell. The applied signal is 8VP-P square wave at a frequency of1000Hz.

R Vo

-
Figure 6.8

b) Using the measured values of R, E, and VT calculate the voltage Vo for the time interval when
Vi=+4V.

VO(calculated) =__
68
 c) Using the measured values of R, E, and VT calculate the voltage Vo for the time interval when Vi = -
4V.

VO(calculated) =__

d) Using the results of parts 6(b) and 6(c) sketch the expected waveform Vo using the horizontal axis of
Fig 6.9 as the Vo = 0V line. Insert your chosen vertical and horizontal sensitivities below:

GRAPH:

Figure 6.9
Vertical sensitivity=___

Horizontal sensitivity =___

e) Using the sensitivities chosen in part 6(d) set the input square wave and record V o on Fig 6.10 using
the oscilloscope. Be sure to preset the Vo = 0V line using the GND position of the coupling switch
(and the DC position to view the waveform)

69
GRAPH:

Figure 6.10

f) How does the waveform of Fig 6.9 compare with the predicted results of Fig6.10?

g) Reverse the battery of Fig 6.8 and using the measured values of R, E, and VT calculate the level of Vo
for the time interval when Vi =+5V.

VO(calculated) =__

h) Repeat part 6(f) for the time interval when Vi=-4V

VO(calculated) =__
i) Using the results of part 6(f) and 6(g) sketch the expected waveform for Vo using the horizontal axis
of Fig 6.11 as the Vo = 0V line. Use the following sensitivities:
Vertical: 2V/cm
Horizontal: 0.2ms/cm

70
GRAPH:

Figure 6.11

71
Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: ______________________________ Date: ____________________

72
LAB # 7: To display the output of diode based clamper circuit using hardware
tools
Objectives

 To measure the output voltages of diode based positive and negative clamper circuits using digital
storage oscilloscope(DSO).
 To measure the output voltages of diode based biased clamper circuits using digital storage
oscilloscope(DSO).

Pre-Lab
Introduction
Clampers are designed to “clamp” an alternating input signal to a specific level without altering the peak to
peak characteristics of the waveform. Clampers are easily distinguished form clippers in a way that they
include a capacitive element. A typical clamper will include a capacitor, diode, and resistor with some also
having a dc battery. The best approach to the analysis of the clampers is to use step by step approach. The first
step should be an examination of the network for that part of the input signal that forward biased the diode.
Choosing this part of the input signal will save time and some unnecessary confusion. With the diode forward
biased the voltage across the capacitor and across the output terminals can be determined. For the rest of the
analysis it is then assumed that the capacitor will hold on to the charge and voltage level established during
this interval of the input signal. The next part of the input signal can then be analyzed to determine the effect
of the stored voltage across the capacitor and the open-circuit state of the diode.
The analysis of a clamper can be quickly checked by simply noting whether the peak-to-peak voltage of the
output signal is the same as the peak-to-peak voltage of the applied signal. This check is not sufficient to be
sure the entire analysis was correct but it is a characteristic of clampers that must be satisfied.
In Figure 7.1 a positive dc clamper is shown. The clamper operates as follows: During the negative half-cycle
of the input voltage, the diode turns on. At the negative peak, the capacitor charges up to Vp with the polarity
shown and the output voltage is zero. As the voltage grows beyond the negative peak, the diode shuts off.
Tasks
1. Design a clamping circuit which is able to perform the function as shown in Figure7.0
Diodes
vi Network vo
30 V
20 V +
+

vi vo

t 0 t
- -
-10 V
-20 V

Figure 7.1

2. Simulate all the circuits in PSpice.

3. Write down all the calculated values in the lab.
73
In-Lab

Lab Task 1
Part 1: Determine the threshold voltage for the silicon diode using the diode checking capability of the
DMM or a curve tracer. If either approach is unavailable assume VT = 0.7V.

Part 2: Clampers (R, C, Diode Combination)

a) Construct the network of Fig 7.1 using R=100 kΩ and record the measured value of R.
Vi

4V + Vc -

+
+
1µF

Vo-
R

Vi
t

-4V -

Figure 7.2

b) Using the value VT from part 1 calculate VC and VO for the interval of Vi that causes the diode to be in
“on”state

VC(calculated)=___ _
VO(calculated) =__
c) Using the results of part 2(b) calculate the level of VO after Vi switches to the other level and turns the
diode“off”.

d) Using the results of part 2(b) and 2(c) sketch the expected waveform for V O in Fig 7.2 for one cycle of
Vi. Use the horizontal centre axis as the Vo = 0V line. Record the chosen vertical and horizontal
sensitivities below:

74
GRAPH:

Figure 7.3

Vertical Sensitivity=__

Horizontal Sensitivity =___

e) Using the sensitivities of part2(b) use the oscilloscope to view the output waveform V O .Be sure to
preset the VO = 0V line on the screen using the GND position of the coupling switch (and the DC
position to view the waveform). Record the resulting waveform on Fig7.3.

f) How does the waveform of Fig 7.3 compare with the expected waveform of Fig7.2?

75
GRAPH:

Figure 7.4

g) Reverse the diode of Fig 7.1, determine the levels of VC and VO for the interval of Vi that causes the
diode to be in “on”state.

VC(calculated)=___ _
VO(calculated) =__
h) Using the results of part 2(f) calculate the level of VO after Vi switches to the other level and turns the
diode“off”.

VO(calculated) =__
i) Using the results of part 2(f) and 2(g) sketch the expected waveform for V O in Fig 7.4 for one cycle of
Vi. Use the horizontal centre axis as the Vo= 0V line. Record the chosen vertical and horizontal
sensitivities below:

76
GRAPH:

Figure 7.5

Vertical Sensitivity=__

Horizontal Sensitivity =___

j) Using the sensitivities of part 2(h) use the oscilloscope to view the output waveform VO. Be sure
to preset the VO = 0V line on the screen using the GND position of the coupling switch (and the
DC position to view the waveform). Record the resulting waveform on Fig7.5.

77
GRAPH:

Figure 7.6

k) How does the with the expected waveform of Fig 7.4 ?waveform of Fig 7.5compare

Lab Task 2: Clampers (R, C, Diode Combination with a DC battery)

a) Construct the network of Fig 7.6 using R=100 kΩ and record the measured value of R and E.
Vi

4V + Vc -
+
+

Vo-

R
Vi

E 1.5
t
-

-4V

Figure 7.7

78
b) Using the value VT from part 1 calculate VC and VO for the interval of Vi that causes the diode to be in
“on”state

VC(calculated)=___ _
VO(calculated) =__
c) Using the results of part 3(b) calculate the level of VO after Vi switches to the other level and turns the
diode “off”.

d) Using the results of part 7(b) and 7(c) sketch the expected waveform for V O in Fig 7.2 for one cycle of
Vi. Use the horizontal centre axis as the Vo = 0V line. Record the chosen vertical and horizontal
sensitivities below:

GRAPH:

Figure 7.8

Vertical Sensitivity=__

Horizontal Sensitivity =___

e) Using the sensitivities of part2(b) use the oscilloscope to view the output waveform V O .Be sure to
preset the VO = 0V line on the screen using the GND position of the coupling switch (and the DC
position to view the waveform). Record the resulting waveform on Fig7.3.
How does the waveform of Fig 7.8 compare with the expected waveform of Fig 7.7 ?
79
GRAPH:

Figure 7.9

f) Reverse the diode of Fig 7.6, determine the levels of VC and VO for the interval of Vi that causes the
diode to be in “on”state.

VC(calculated)=___ _
VO(calculated) =__
g) Using the results of part 3(f) calculate the level of VO after Vi switches to the other level and turns the
diode “off”.

VO(calculated) =__
h) Using the results of part 3(f) and 3(g) sketch the expected waveform for V O in Fig 7.2 for one cycle of
Vi. Use the horizontal centre axis as the V o = 0V line. Record the chosen vertical and horizontal
sensitivities below:

80
GRAPH:

Figure 7.10

Vertical Sensitivity=__

Horizontal Sensitivity =___

i) Using the sensitivities of part3(h) use the oscilloscope to view the output waveform V O .Be sure to
preset the VO = 0V line on the screen using the GND position of the coupling switch (and the DC
position to view the waveform). Record the resulting waveform on Fig 7.10.

82
GRAPH:

Figure 7.11

j) How does the waveform of Fig 7.10 compare with the expected waveform of Fig7.9

83
Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: ______________________________ Date: ____________________

84
LAB # 8: To construct the Emitter Biased BJT circuits and measure quiescent
operating point of using hardware tools
Objectives

To measure the quiescent operating point of Emitter Biased BJTs using digital multi-meter(DMM)

Pre-Lab
Introduction to Fixed and Emitter Biasing of BJTs
Bipolar transistors operate in three modes: cutoff, saturation, and linear. In each of these modes, the physical
characteristics of the transistor and the external circuit connected to it uniquely specify the operating point of-
the transistor. In the cutoff mode, there is only a small amount of reverse current from emitter to collector,
making the device akin to an open switch. In the saturation mode, there is a maximum current flow from
collector to emitter. The amount of that current is limited primarily by the external network connected to the
transistor; its operation is analogous to that of a closed switch. Both of these operating modes are used digital
circuits. For amplification with a minimum of distortion, the linear region of the transistor characteristics is
employed. A DC voltage is applied to the transistor, forward-biasing the base-emitter junction and reverse-
biasing the base-collector junction, typically establishing a quiescent point near or at the center
of the linear region. In the first part of this experiment, we will investigate the voltage divider-
bias network.

In-Lab
Lab Task 1:
Determining β: Construct the network of Fig. 9.1 using the 2N3904 transistor. Insert the measured
resistance values.
VCC
IC

2.7kΩ
RC
1MΩ +

VCE
IB
-

85
 Figure 9.1
a) Measure the voltage VBE and VRC

VBE (measured)=__
VRC (measured) =__

b) Using the measured resistor values calculate the resulting base current using the equation:

IB = VRB/ RB = (VCC - VBE)/ RB

and the collector current using the equation.
IC = VRC/ RC
The voltage VRB was not measured directly for determining IB because of the loading effects
meter across the high resistance RB

Insert the resulting values of IB. and Ic in Table 8.1.

c) Using the results of step1(b), calculate the value of βand recording Table 8.1, This value of beta will
be used for the 2N3904 transistor throughout this experiment.

Table8.1
2N3904 VB VE VC VCE IC IB IE
Calculated
Measured

Part 2: LabTasks

In this part, the emitter bias circuit is investigated.

The emitter bias configuration in Fig. 9.3 can be constructed using a single or a dual power supply. Both
configurations offer increased stability over the fixed bias of previous Experiment. In particular, if the beta
times of the transistor times the resistance of the emitter resistor is large compared to the resistance of the base
resistor, the emitter current becomes essentially independent of the beta of the transistor. Thus, if we exchange
transistors in a properly designed emitter-bias circuit, the changes inIc and𝑉𝐶𝐸 should be small.

In the first part of this experiment, we will investigate the fixed-bias network.

Lab Task 1: Determining Beta

a) Construct the network of Fig. 9.3 using 2N39Q4 transistor, Insert the measured resistor values:

86
 +20 V

430kΩ 2kΩ
10 µF
Vo
10 µF
Vi

1 kΩ 40 µF

Figure 8.2

b) Measure the voltages V B andVc .

, . V B (measured)

V c (measured)
c) Using the results of Part (b) and the measured resistor values calculate the resulting base currents IB
and IC using the following equations:
IB=Vcc-VB/RB
And IC=VRC/RC
Record in table 8.2
IB (measured)=_____________________
IC (measured)=_____________________

Table 8.2
Transistor type VCE IC IB Β
2N3904
2N4401

87
Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: ______________________________ Date: ____________________

88
LAB # 9: To construct the Voltage Divider Biased BJT circuits and measure
quiescent operating point of using hardware tools
Objectives

To measure the quiescent operating point of Voltage Divider Biased BJTs using digital multi-

meter(DMM)

Pre-Lab
Introduction to Fixed and Emitter Biasing of BJTs
Bipolar transistors operate in three modes: cutoff, saturation, and linear. In each of these modes, the
physical characteristics of the transistor and the external circuit connected to it uniquely specify the
operating point of- the transistor. In the cutoff mode, there is only a small amount of reverse current from
emitter to collector, making the device akin to an open switch. In the saturation mode, there is a maximum
current flow from collector to emitter. The amount of current is limited primarily by the external network
connected to the transistor; its operation is analogous to that of a closed switch. Both operating modes are
digital circuits. For amplification with a minimum of distortion, the linear region of the transistor
characteristics is employed. A DC voltage is applied to the transistor, forward-biasing the base-emitter
junction and reverse- biasing the base-collector junction, typically establishing a quiescent point
near or at the center of the linear region. In the first part of this experiment, we will
investigate the voltage divider- bias network.

In-Lab

a) Construct the network of Fig. 9.2 using the 2N3904 transistor. Insert the measured value of
each resistor.

+18 V

39kΩ 10 kΩ

vo
10 µF IB + 10µF
vi VCE
VB -

3.9 kΩ 1.5 kΩ

Figure 9.2

R1 (measured)=___
R2 (measured)=___
RC (measured)=__
RE (measured) =___
89
 b) Using the beta determined in Part 1 for the 2N3904 transistor, calculate the theoretical levels of
VB, VE,VC, IE, IC, and IB, for the network of Fig.9.2.Insert the results in Table 9.1.

Table9.1
2N3904 VB VE VC VCE IC IB IE
Calculated
Measured

c) Energize the network of Fig. 9.1 and measure VB, VE, VC and VCE. Record their values in Table
9.3. In addition, measure the voltages VR1 and VR2. Try to measure the quantities to the hundredth or
thousandth place, Calculate the currents IE and IC and the currents I1 and I2 (using I1 = VR1, /R1 and I2
= VR2, /R2) from the voltage readings and measured resistor values. Using the results for I1 and I2,
calculate the current IB using Kirchhoff’s current law. Insert the calculated current levels for IE, IC,
and IB in Table 9.1.

How do the calculated and measured values of Table 9.1 compare? Are there any significant
differences that need to be explained?

d) Insert the measured value of VCE and calculated values of Ic and

IBfromstep3(c)inTable11.4along with the magnitude of beta from Part1.

e) Replace the 2N3904 transistor of Fig 9.1 with the 2N4401 transistor. Then measure the
voltages VCE, VRC, VR1, and VR2. Again, be sure to read VR1 and VR2 to the hundredth or
thousandth place to ensure an accurate determination of IB. Then calculate IC, I1,I2, and determine
IB. Complete table 9.4 with the levels of VCE, IC,IB, and beta for this transistor

Table 9.1
Transistor type VCE IC IB Β
2N3904
2N4401

f) Calculate the percent change in β, IC, VCE and IB from the data of table 11.4. Use the
formulas appearing in step 2(e), Eq. 9.1, and record your results in table 9.2
Percentage changes in β, I C, VCE and IB
Table 9.2
Transistor VCE IC IB β
type
2N3904
2N4401

90
Lab Tasks

a) Using the β determined in Part I, calculate the values of I B and I C for the network of Fig. 9.1 using
measured resistor values and the supply voltage VCC. In other words, perform a theoretical analysis
of the network. Insert the results in Table 9.2.

IB(measured)=----------------------

IC(measured)=----------------------

b) How do the calculated values compare with the measured values of |Part 2 of lab Task1(c)?

c) Using the β determined in Lab task 2 calculate the levels of VB, VC, VE, VBE and VCE and insert in
Table 9.2.

Table 9.2 (Calculated Values)

Transistor VCE VB VC VE VBE VCE IB
type
2N3904
2N4401

Table 9.3 (Measured values)

Transistor VCE VB VC VE VBE VCE IB
type
2N3904
2N4401

d) Calculated from the measured values

2N3904β=_

2N4401β=

e) Replace the 2N3904 transistor of Fig. 9.2 with the 2N4401 transistor and measure the resulting voltages
VB and VRC, Then calculate the currents IB and IC using measured resistance values. Finally calculate
the value of β for this transistor. This will be the value of beta used
for the 2N4401 transistor throughout this experiment. Record the levels of IB, IC and β in Table9.2.
VB(measured)=______________

VRC(measured)=______________

f) Using the beta determined in step 1(c), perform a theoretical analysis of Fig. 10.2 with the 2N4401
transistor. That is, calculate the levels of IB, IC, VB, VC, VE and VCE insert in Table 9.3

91
Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: ______________________________ Date: ____________________

92
LAB # 10: To construct a simple JFET biasing circuit and sketch its output and
transfer characteristics using digital multimeter

Objectives

To sketch the characteristic curve for JFET transistor

Pre-Lab
Introduction to JFET
Junction Field Effect Transistor (JFET)is a three terminal device namely, Drain(D),Source(S),Gate(G)as
shown in Figure13.0.

Figure 10.1 n channel and p channel JFET symbols

The junction field-effect transistor (JFET) is a uni-polar conduction device. In the n-channel JFET the
conduction path' is an n-doped material, germanium or silicon, while in the p-channel the conduction path is
p-doped germanium or silicon. Conduction through the channel is controlled by the depletion region
established by oppositely doped regions in the channel. The channel is connected to two terminals, referred
to as the drain and the source, respectively. Forn-channel JFETs ,the drain is connected to a positive voltage,
and the source to a negative voltage, to establish a flow of conventional current in the channel. The polarities
of the applied voltages for the p-channel JFET are opposite to those of the n-channel JFET.
A third terminal, referred to as the gate terminal, provides a mechanism for controlling the depletion region
and thereby the width of the channel through which conventional flow can exist between the drain and
source terminals. For an n-channel JFET, the more negative the gate-to-source voltage is, the smaller the
channel width is. This experiment will establish the relationships between the various voltages and currents
flowing in a JFET. The nature of these relationships determines the range of JFET applications.
Unlike bipolar junction transistors, FETs do not have a fixed forward biased junction potential. This makes
bias analysis a little trickier. It is often useful to have a couple of device parameters on hand, namely IDSSand
VGS(OFF). As is the case with BJTs, finding the main current (ID) is the key to finding all other circuit currents
and voltages. One convenient aspect of JFETs is that the gate current can be ignored for most bias
applications. Self-Bias may be analyzed through the use of a Self-Bias curve or through an iterative process
of estimation of VGS leading to drain currents via Ohm’s law and the general FET transconductance
equation. Self-Bias tends to have modestly stable Q points. Source Bias is an improvement over Self Bias.
It tends to swamp out V GS variation via the addition of a negative source bias voltage. This topology also
turns out potentially to have a very stable transconductance although it is not examined in this exercise.
115
Finally,
Current Source Bias utilizes a BJT to establish a very stable drain current. This turns out this comes at the
expense of a stable VGS and transconductance (again, not examined here), so this form of bias is not
necessarily the best choice for all applications.

In-Lab
Lab Task1
a) Construct the network of Fig. 12.1. The 10-kΩ resistor in the input circuit is included to protect
the gate circuit if the 9 V battery is applied with the wrong polarity and the potentiometer is set on
its maximum value.
25 V

1 kΩ

100 Ω
5 kΩ
10 kΩ Potentiometer

D
G
1MΩ
9V Potentiometer

Figure 10.2

b) Vary the MΩ potentiometer until VGS=0 V. Recall that ID=IDSS when VGS=0.
c) Set VDS to 8 V by varying the 5 K ohm potentiometer. Measure the voltage VR.
VR(measured)=
d) Calculate the saturation current from IDSS=ID=VR/R
IDSS(measured)=_

e) Maintain VDS at 8 V and reduce VGS until VR drops to 1 mV. At that level ID=VR/R= 1mV/100 =
10 µA. Recall that VP is the voltage VGS that results in ID=0 mA. Record the pinch off voltage
Vp(measured)=__

f) Check with two other groups and record your readings

IDSS(measured)=_

Vp(measured)=__

IDSS(measured)=_

116
 Vp(measured)=__

g) Using the determined values of IDSS and VP sketch the transfer characteristics of the device using
Shockley’s equation. Plot at least 5 points on the curve.

ID= IDSS(1- VGS/VP)2

GRAPH:

Figure 10.3

Lab Task 2: This part of the experiment will determine the ID versus VDS characteristics
for an n-channel JFET. ,
• Use the network of Fig. 10.1, vary tire two potentiometer until VGS = 0 V and V DS = 0
V. Determine ID from ID = VR/R using the measured value of R and record in
Table13.1.
• Maintain V GS =0VandincreaseV DSthrough14V[in one step]and record the calculated
value of ID . Be sure to use the measured value of the 100 ohm resistance in your
calculations.
• Varythe1-MohmpotentiometeruntilVGS=-IV. Maintaining VGS at this level vary VDS through
the levels of Table 10.1 and record the calculated values of ID.
• Repeat step 2(c) Tor the values of V Gs appearing in Table 10.1. Discontinue the
process once VGS exceeds VB.

116
 Table 10.1

VGS(V) 0 -1 -2 -3 -4
VDS (V) ID ID ID ID ID
(mA) (mA) (mA) (mA) (mA)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0

Lab Task 3: Transfer Characteristics

This part of the experiment will-determine the ID vs VGS transfer characteristics frequently used in the
analysis of JFET networks. Ideally, the transfer characteristics as determined by Shockley's equation
assume that the effect of VDS can be ignored and the characteristic curves of Fig. 13.3 for a given V GS are
considered horizontal. The following will show that the transfer curve does vary slightly with V DS but not
to the point where concern should develop about using Shockley's equation.
For this part of the experiment all the data can be obtained from Table10.1.There is no experimental work
in this part.

117
GRAPH:

Figure 10.4

118
Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: ______________________________ Date: ____________________

119
LAB #11: To construct fixed-biased and self-biased common-source circuit and
measure its Q point voltage and current using digital multimeter

Objectives
1. Understand the purpose of biasing a JFET
2. Bias a JFET transistor to a selected quiescent point (Q-point) using the fixed and Self Biasing method
3. Also measure which produces a stable Q point

Pre-Lab
Part 1 – Introduction to the biasing of FETs

The term biasing a JFET means placing the operating point of a JFET used in an amplifier at a desired location
within the drain curve chart. This “operating point” is referred to as the quiescent point or Q-point because this
is the “operating point” when the amplifier is “quiescent” (has no input applied). With input applied (in the
dynamic condition) the output current(ID) “operates” (increases and decreases) around the Q-point as a
function of the gate-to-source voltage(VGS).SeeFigure1.If the Q-point shifts during transistor operation, then
the output current (ID) will not faithfully represent the input voltage VGS and thus distortion will be
introduced to the amplified signal.
In the previous lab, you developed the drain curves and transconductance curve for a 2N4416 JFET from
empirical data. As with a bi-polar junction transistor’s characteristic curves, the JFET’s drain curves provide a
map of where to operate your particular transistor. As is similar to the BJT, there are 3 areas where a JFET can
operate; in the cutoff region, in the Ohmic region, or in the constant current region.
a. In the cutoff region, the drain current (ID), which is the current flowing through the channel (an n-channel in
this case since this an n-channel JFET), consists only of leakage current and therefore the voltage drop across
the drain-to-source (VDS) junction is equal (or very, very nearly equal) to the supply voltage (VDD). When
operating in the cutoff region, the JFET is effectively an open switch. To be in the cutoff region, the gate-to-
source voltage (VGS) must be negative and equal or greater in magnitude to the JFET’s cutoff voltage (VGS(off))

b. In the Ohmic region, the drain current (ID) varies with the drain-to-source voltage (VDS) value in accordance
with Ohm’s law. If the various drain curves for a particular JFET are analyzed, it will be observed that the
slope of the curves in the Ohmic region (ΔID/ΔVDS) represents the conductance of the JFET’s channel for the
applied VGS. Remember, conductance is the inverse of resistance so, if operated in the Ohmic region, a JFET
could be used as a voltage controlled resistor with V GS controlling the resistance. The Ohmic region is defined
by a VDS between VDS = 0 and VDS = pinch-off voltage (VP) and ID = 0 and ID = IDSS.

c. In the constant current region and for a given negative gate-to-source voltage (VGS), the drain current (ID)
remain fairly constant for changing values of VDS. If VDS were to increase beyond a level called the breakdown
voltage, ID would rise dramatically and possibly damage the JFET. When biasing a JFET, generally you want
to place its operating or Q point in the center of the constant current region.

120
Part 2 – Design Methodologies
Determine VDD
In the self biasing scheme, the supply voltage (VDD) is the first parameter to be determined. This is done by
picking an appropriate voltage based on an analysis of transistor’s limitations, circuit limitations, power
supply limitations, and voltage gain required.

Drain Resistor (RD)

The drain resistor is used to set the value of the drain current. Since we know the value of ID and VDS at the
desired bias point, as well as the value of VDD, we can easily compute the value of RD so that the desired bias
point is achieved.

Source Resistor (RS)

To operate a n-channel JFET as an amplifier, the gate junction must be reversed biased i.e. electrically negative
in relation to the source. To negatively bias the gate-to- source junction, a negative voltage source could be
placed between the gate and ground; however, this method is not generally used since it would require addition
of another voltage source to the circuit. A more efficient method to achieve a negative bias between the gate-
to-source junctions is to electrically “raise” the source above ground.
Figure 1 illustrates this method. The JFET’s gate is maintained at ground level through a resistor (RG )
connected directly to ground. Despite the resistor between it and ground, the gate stays at (or extremely close
to) ground potential because the reversed biased drain-to-gate junction current is extremely low and can be
considered non- existent, therefore, no voltage develops across RG. As source current flows through RS from
source to ground, the source side of the resistor is raised above ground in accordance with Ohm’s law. This
action results in a negative bias between the gate which is at 0V or ground potential and the source which is at
(IS*RS) V. This self biasing provides the negative bias for the gate-to-source junction that is required for the
JFET to operate as an amplifier.

VDD

RD

ID
VRD=ID*VD
VG=0
VD=VDD-(ID*VD)
IG=0
VS=IS*RS
RG
IS IS=ID
RS

Figure 11.1 Current and Voltage Bias Points

121
Design Task

1. Design a self bias network using JFET transistor with IDSS =8 mA and VP=-6V to have a Q-point at = 4
𝑚𝐴 using a supply of 14 V. Assume RD= 3RS and use standard values.

In Lab
Lab Task-1: Fixed Biased
With the help of theory explained in the previous and the design equations mentioned in the two biasing
methods as explain below design the fixed and self biased configurations for which find the values of supply
voltage and resistors.

VDD

RD

+
A Am-meter (0-10mA)
-
+
V Voltmeter (0-15V)
-

RG

Figure 11.2 Fixed Bias configuration

Designing Equations:

𝑉𝐺 = 𝐼𝐺𝑅𝐺
𝑉𝐺𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 〈1− 〉2
𝑉𝑃

From the outer loop

+ 𝐼𝐷𝑅𝐷 − 𝑉𝐷𝐷 = 0

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷

122
 Table 11.1

Sr. no. Design Combination of Conditions chosen Values Observed

Values
(Determined)
RD (Ω) VDD (V) IDQ (mA) VDSQ (V) IDQ (mA) VDSQ (V)
1
2
3

Lab Task-2: Self Biased

VDD

RD

+
A Am-meter (0-10mA)
-
+
V Voltmeter (0-15V)
-
Fig 14.2
RG

RS

Figure 11.3 Self Biased configuration

Designing Equations:

The drain voltage

𝑉𝐷 = 𝐼𝐷𝐷 − 𝐼𝐷𝑅𝐷

Drain to source voltage

𝑉𝐷𝑆 = 𝑉𝐷 − 𝑉𝑆

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷 − 𝐼𝐷𝑅𝑆

123
 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼(𝑅𝐷 − 𝑅𝑆)

Gate to source voltage

𝑉𝐺𝑆 = 𝑉𝐺𝐺 − 𝑉𝑠 = 0 − 𝐼𝐷𝑅𝑆 = −𝐼𝐷𝑆

Table 11.2

2Sr. no. Design Values Combination of Conditions chosen Values Observed

(Determined)
RD (Ω) RS (Ω) VDD (V) IDQ (mA) VDSQ (V) IDQ (mA) VDSQ (V)
1
2
3

124
 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: ______________________________ Date: ____________________

125
LAB #12: To construct a voltage-divider biased common-source circuit and
measure its Q point voltage and current using digital multimeter

Objectives
1. Measure the quiescent operating conditions of the voltage-divider-bias FET configurations.
2. Understand the effects of changing configurations on the Q-point stability.

Pre-Lab
Part 1 – Introduction to Voltage Divider Biased Configuration
The figure given below represents another way to bias the JFET by using a voltage division. This biasing
technique can be compared to the biasing of the voltage divider that is used in the bipolar transistors.
VDD

RD

R1

RG
+
VGS
-
R2
+
RS VS
-

Figure 12.1

The voltage which is applied on the gate is: VG=VDD * R2 / (R1+R2)

The voltage VS at the edges of the source resistance RS is VS = VG - VGS, so the drain current will be equal
to ID = (VG - VGS) /RS
If the VG is much bigger than VGS the drain current will be almost stable for every JFET. However, the VGS
can vary enough Volt from one JFET to another, and as a result for the voltage supplies that are used, that the
elimination of the effect of the V GS not to be complete. Therefore, the voltage divider bias
is less effective on the JFET compared to the bipolar transistors.

Design Task
Design a voltage divider bias circuit using JFET with IDSS=10 mA and VP=-4 V to have a Q-point at 𝑰𝑫𝑸 =
𝟐. 𝟓 𝒎𝑨 using a supply of 24 V. In addition, set VG=4 V and use RD=2.5 RS with R1=22 MΩ. Use
standard values.

126
 In-Lab
Lab Task-1
a) Construct the network of given below using the 2N4416 transistor. Insert the measured
value of each resistor.
+16 V

2.1 MΩ 2.4 kΩ

Vo
10 µF
Vi
5 µF

270 kΩ
1.5 kΩ 20 µF

Figure 12.2

R1 (measured) =___

R2 (measured) =___

RD (measured) =__

RS (measured) =__

b) Determine the values of VG, VD, VS, VDS, and VGS using Schokley’s equation and insert it in
table 12.1 below
c) Measure the values of VG, VD, VS, VDS, and VGS using Schokley’s equation and insert it in
table 12.1 below
d) Determine the percentage difference between the calculated and measured values and
record it in table12.1
Table 12.1
VG VD VS VGS VDS
Calculated
Measured
% Difference

127
Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Worst The student did not complete assigned tasks. 1

Instructor Signature: ______________________________ Date: ____________________

128