6.
5 Current mirror OpAmp
Another popular OpAmp when driving only on-chip capacitive loads is the current-mirror
OpAmp. Note that at the Q2 side, more current mirrors needs to be used to provide
current KID2=KID1.
Also, it can be seen that all internal nodes have low impedance except the output node. By
using proper current mirrors with high output impedance, good gain can be achieved.
The overall transfer function of this OpAmp closely approximate dominant-pole operation.
Chapter 6 Figure 21 Chapter 6 Figure 22
It can be seen that larger K increases the unity-gain frequency assuming the load
capacitor dominates the time constants. Larger K also increases the gain. A typical
upper limit for K is 5.
A detailed analysis reveals important nodes for determining the non-dominant poles, at
the drain of Q1 first and drain of Q2 and Q9 secondly. Larger K increases the
capacitances at these nodes while also increases the resistance (assuming a fixed Itotal),
which reduce the non-dominant poles. In this case, then CL has to be increased to
maintain a large phase margin. So, K should not be too large, i.e. K<=2 usually.
During slew rate, all of the bias current Ib of the first stage is diverted through Q1/2 and
amplified by the current mirror gain to the output. The total current to
charge/discharge the load is KIb. So the slew rate is
Due primarily to the larger unity-gain frequency and slew rate, the current-mirror
OpAmp may be preferred over the folded-cascode OpAmp. However, one has to be
careful that the current-mirror OpAmp has larger input noise as well, as its input stage
is biased at a lower portion of the total bias current and therefore a relatively smaller gm
given the same power consumption.
Example 6.11 (page 277)
Veff1 can be estimated to be about 50mV so that
gm1=3.14mA/V is sort of maximized.
Comparing to the previous example on FC-OpAmp with the same power and load, the
current-mirror OpAmp can have better bandwidth and SR if K is made larger.
If 75 degrees of phase margin is used, the unity-gain frequency must be 0.27 times of
or 126MHz , so the CL must be increased from 2.5pF to 5pF to reduce from 255MHz to
126MHz.
If lead compensation is used, then unity-gain frequency can be designed to be 0.7 times of
so that 55 degrees of phase margin is achieved. Then, lead compensation can be used
to achieve another 20 to 30 degrees of phase margin. Also, no additional load capacitance
is necessary, which reduces the circuit area.
6.6 Linear settling time revisited
Recall from Chapter 5 the 3db bandwidth of the closed loop amplifier is the unity-gain
frequency of the loop gain, which is β times the unity-gain frequency of the OpAmp, i.e.
6.6 Linear settling time revisited
Chapter 6 Figure 23
recall from Chapter 5 on negative feedback
The load capacitance is more complicated. Treating
the inverting terminal of OpAmp open, the
effective CL is more than just Cload and Cc, but Chapter 5 Figure 21
This can be verified using the loop gain method introduced in Chapter 5: we can find out
the loop gain first and directly find the unity-gain frequency of the loop gain:
1 C2
Vr g mVt
(C1 C p )C2 C1 C p C2
S[ C L CC ]
C1 C p C2
Example 6.12 (page280)
Chapter 6 Figure 23
6.7 Fully differential amplifiers
The main difference between single-ended amplifiers and fully-differential versions is
that a current mirror load is replaced by two matched current sources in the later. Notice
the power dissipation and slew rate is the same.
However, the voltage swing in fully-
differential version is twice that of the
single-ended version, because they
use the differential voltage at two
circuit nodes instead of one.
Chapter 6 Figure 24
Chapter 6 Figure 25
Why Fully differential amplifiers?
One of the main driving forces behind the use of fully differential amplifiers is to help
reject common-mode noise. The common-mode noise, ncm, appears identically on both
half signals and is therefore cancelled when the difference between them is taken.
Many noise sources, such as power supply noise, bias voltage noise and switches noise
act as common mode noise and can therefore be well rejected in fully-differential
amplifiers.
Ni1 and ni2 in the figure represent random noise sources added to the two outputs, and
the overall signal-to-noise ratio is still better than the single-ended version.
Chapter 6 Figure 26
Why Fully differential amplifiers?
Fully –differential amplifiers have another benefit that if each output is distorted
symmetrically around the common-mode voltage, the differential signal will have only
odd-order distortion, which are often much smaller.
With the above mentioned advantages, most modern analog circuits are realized using
fully differential structures.
One major drawback of using fully-differential OpAmp is that common-mode feedback
circuit (CMFB to be discussed later) must be added to establish the common-mode
output voltage. Another minor overhead is that in practice fully-differential OpAmp
may need some additional power consumption due to CMFB and to producing the two
outputs.
Chapter 6 Figure 27
6.7.1 Fully differential folded-cascode OpAmp
Compared to the singled-ended version, the n-channel current mirror has been replaced by two cascode
current sources of Q7/8 and Q9/10. Also, a CMFB circuit is introduced. The gate voltage Vcntrl is the
output of the CMFB.
Note that when OpAmp is slewing the maximum current for negative slew rate is limited by the bias
current of Q7 or Q9 (as there is no current mirror like the singed-ended one). So, fully-differential FC is
usually designed with bias current in the output stage equal to the bias currents in the input transistors.
Note that each signal path now consists of only one node in addition to the output nodes, which is the
drain nodes of Q1/2. These nodes are responsible for the second pole.
When load capacitance is relatively small
so it is important to push the second pole
away, then one can consider using pMOS
for Q1/2 and nMOS for Q5/6, as the
impedance at the drain of Q1/2 would be
larger that way, resulting in smaller time
constants. However, the tradeoff is DC
gain may be smaller.
Chapter 6 Figure 28
6.7.2 Alternative fully differential OpAmps
The previous singled-ended current mirror OpAmp can be converted to a fully-differential
one as below.
Similarly, the complementary design using pMOS at input stage is possible. Which one to use
depends on whether the load capacitance or second pole are limiting the bandwidth and
whether DC gain or bandwidth is more important. (in the former case, then nMOS input is
preferred. )
For a general-purpose amplifier, this design with large pMOS transistors, a current gain of
K=2 and wide-wing enhanced output-impedance cascode mirrors and current sources may
be a good choice compared to other designs.
Slew rate KIB/2 in each output
Chapter 6 Figure 29
Larger slew rate
In the revised circuit, the current mirrors at the top have been replaced by current mirrors
having two outputs. The first output has a gain of K and goes to the output of the OpAmp as
before. The second output has a gain of one and goes to a new current mirror that has a
current gain of K, where it is mirrored the second time and then goes to the opposite
output.
In this OpAmp, when slewing (suppose a very large input voltage), then the current going to
Vout+ is Kibias, whereas the current sinked from Vout- is also Kibias.
This OpAmp has an improved slew rate at the expense of slower small-signal response
due to addition of extra current mirrors. But it may be worthwhile in some applications.
Chapter 6 Figure 30
Another alternative design to have bi-direction driving capability is to use two singled-ended
output OpAmps with their inputs connected in parallel and each of their output being one
output side of the fully-differential version.
The disadvantage is the additional current mirrors and complexity. (note in the figure, the
CMFB loop is not shown).
Chapter 6 Figure 31
6.7.3 Low supply voltage OpAmps
Low supply voltage complicates the OpAmp design. For the folded-cascode OpAmp, the
input common-mode voltage must be large than Vgs1+Veff in order to keep the tail current
source device in active mode (a typical value is 0.95V which is difficult for 1.2 power supply).
The low-voltage design shown below(CMFB circuit is not shown) makes use of both nMOS
and pMOS in the two differential input pairs. When the input common-mode voltage range
is close to one of the power supply voltages, one of input differential pairs turns off while
the other one remains active. To keep the OpAmp gain relatively constant, the bias currents
of the still-active pair is dynamically increased.
For example, when input common-mode
voltage is close to Vdd, Q3/4 turns off and Q6
conduct all of I2, which go through a current
mirror M1 so that the bias current of I1 is
increased.
Be careful about the input and output polarity!
Chapter 6 Figure 32
Low supply voltage OpAmps
Another challenge of low supply voltage designs is that the signal output swing is very
small, especially for the single-stage folded-cascode OpAmp (referring to the OpAmp in
Fig 6.28, it can be shown that the signal swing is as small as 0.3V if Veff=0.2V for Vdd=1.2V).
One possible design to alleviate that problem is an enhanced two-stage OpAmp with a
folded-cascode first stage and a common-source second stage. The first stage can
provide high gain (small voltage swing for first stage output is not an issue) and the
second stage can provide relatively large signal swing. (note CMFB is not shown and also
the lead compensation is used.)
Polarity
Chapter 6 Figure 33
6.8 Common-mode feedback circuits
From B. Razavi, “Design of Analog CMOS Integrated Circuits”, McGrawHill, 2000.
6.8 Common-mode feedback circuits
From B. Razavi, “Design of Analog CMOS Integrated Circuits”, McGrawHill, 2000.
6.8 Common-mode feedback circuits
6.8 Common-mode feedback circuits
6.8 Common-mode feedback circuits
Typically, a CMFB circuit should have three operations:
1.Sense the common-mode voltage level of the differential output;
2.Compare the common-model voltage to a reference voltage (the desired voltage);
3.Return the error to the amplifier’s bias network to adjust the current and eventually the
output voltage.
The following circuit illustrates the idea.
CMFB circuit design may well be one of the most difficult part of the OpAmp design.
6.8 Common-mode feedback circuits
The one shown below is a continuous one. To illustrate, assume CM output voltage, Vout,CM,
equal to reference voltage Vref,CM, and that Vout+ is equal in magnitude but opposite in sign to
Vout-. Also, assume the two differential pairs Q1/2 and Q3/4 have infinite CMRR (i.e. their
output depend only on their differential voltage).
Since two pairs have the same differential voltages, current in Q1 is equal to current in Q3
and that in Q2 equal to Q4. Denoting the current in Q2 as and current in Q3
is and the current in Q5 is
In the nominal case, when Vout,CM=Vref,CM,
then there will no voltage change for Vcntrl,
which then stays constant.
If Vout,CM>Vref,CM, then the differential voltage
across Q1/2 increases while that for Q3/4
decreases, so the current in Q2 and Q3 will
be larger than before, which increases the
voltage Vcntrl.
Chapter 6 Figure 34
Now this voltage Vcntrl can be the bias voltage that sets the current levels in the nMOS
current sources at the output of the OpAmp (see below), which will bring down the
common-mode output voltage, Vout,CM to decrease toward the nominal Vref,CM.
So, as long as the common-mode loop gain is large enough, and the differential signals are
not so large as to cause either differential pair Q1/2 or Q3/4 to turn off, Vout,CM can be kept
very close to Vref,CM. The later requires that we maximize the Veff for these transistors.
Finally, the IB should be high output impedance cascode current sources to ensure good
CMRR.
Chapter 6 Figure 28 Chapter 6 Figure 29
Another CMFB
This circuit generates the senses the common-mode voltage of the output signals (minus a
DC level shift) at node VA. This voltage is then compared to a reference voltage, Vref, using a
separate amplifier.
One limitation is that the voltage drop across Q1/2 may severely limits the differential
signals that can be processed, which is important in lower supply voltage applications.
Chapter 6 Figure 36
Design considerations of CMFB loop
One important design consideration is that CMFB is part of the negative feedback loop, and
therefore must be well compensated if needed, otherwise the injection of common-mode
signal can cause output ringing and even unstable. Thus, phase margin ( by breaking at Vcntrl
to find loop gain from Chapter 5) and step response (by giving Vref a step input) of the
common-mode loop should be checked.
Often, the common-mode loop is stabilized using the same capacitors used to compensate
the differential loop (for example by connecting two compensation or load capacitors from
outputs to ground).
Also, it is important to maximize the speed
of CMFB loop by having as few nodes in
the design as possible (to prevent high
frequency common-mode noise). For this
reason, the CFMB output is usually used to
control current sources in the output
stage of the OpAmp. For the same reason,
the CM output of each stage in a multi-
stage amplifier is individually
compensated (for example the on in Fig
6.33. ).
Chapter 6 Figure 37
This is an active research area.
Switch-capacitor CMFB circuit
In this approach, Capacitors Cc generates the Vout,CM, which is then used to create control
voltages Vcntrl. The bias voltage Vbias is designed to be equal to the difference between the
desired Vref,CM and the desired Vcntrl used for OpAmp current sources.
This CMFB circuit is mostly used in switched-capacitor circuits since they allow a larger
output signal swing.
Chapter 6 Figure 38
