COA
DMA
In Direct Memory access CPU is idle and peripheral devices manages the
memory buses directly
DMA controller takes over the buses to manage the transfer directly between
I/O devices and memory
DMA transfer is done in 2 ways
Burst Transfer: a block of memory words is transferred in
continuous burst at a time . Used in fast devices like magnetic
disk
Cycle stealing: DMA controller transfers one data word at a time
. After which it return control of the buses to CPU
Working of DMA
DMA controller uses the Bus Request(BR) input to request the CPU to relinquish the
control of the buses
Then CPU terminates the execution of current instruction and places the address bus,
Data bus, read and write lines into a high impedance
state(like open circuit)
CPU activates Bus Grant (BG) signal to inform the DMA that buses are available
DMA takes control of buses and perform memory transfer
When DMA terminates it disable BR signal CPU disables BG signal and
returns to it normal operation
DMA Controller
DMA controller has 3 registers
Address Register: Contains the address to specify desired location
Word Count Register: Specifies the number if words that must be
transferred
Control Register: Specify mode of transfer(Either read or write).
Registers are selected by the CPU by enabling DMA select and register
select input
When BG=0 CPU is communicating with registers.
When BG=1 DMA is communicating with memory
DMA transfer
● I/O Device sends a DMA request
● DMAC activates the BR line
● CPU responds with BG line
● DMAC sends a DMA acknowledge to the I/O device
● I/O device puts a word in the data bus (for memory write) or receives
a word from data bus(For memory read)
● DMAC write a data to the address specified by Address register .
Increment address register
DMA transfer
Word count register ≠ 0 DMAC checks the DMA request from I/O device.
If there is no request DMA disables BR line So that CPU continues to
execute its own program
When peripherals request another transfer, DMA requests buses again.
Word count register = 0 DMA stops further transfer and removes BR .It
inform CPU through EOT interrupt
INPUT OUTPUT PROCESSOR[IOP]
In systems with IOP the computer is divided into three separate modules
the memory unit, the CPU, and the lOP.
Communicate directly with all I/O devices
Fetch and execute its own instruction
IOP instructions are specifically designed to facilitate I/O transfer
Central Processing Unit
M
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Peripheral Devices
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o P P P P
D D D D
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Memory unit y
B
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Input-Output Processor
I O Bus
Input Output Processor
The computer system with IOP can be divided into 3 separate modules:
1. The Memory unit
2. The CPU and
3. one or more IOPS.
● The IOP can fetch and execute its own instructions.
● IOP instructions are specifically designed to facilitate I/O transfers.
● The IOP can also perform other processing tasks, such as arithmetic, logic,
branching, and code translation.
CPU - IOP Communication
Instructions that are read from memory by an lOP are sometimes called commands, to
distinguish them from instructions that are read by the CPU.
● The CPU sends an instruction to test the IOP path.
● The IOP responds by inserting a status word in memory for the CPU to check
.
● The bits of the status word indicate the condition of the IOP and I/O device (IOP overload
condition, device busy with another transfer, or device ready for I/O transfer).
● The CPU refers to the status word in memory to decide what to do next.
● If all is in order, the CPU sends the instruction to start I/O transfer.
● The memory address received with this instruction tells the IOP where to find program.
● The CPU can now continue with another program while the IOP is busy with
the I/O program.
● Both programs refer to memory by means of DMA transfer.
● When the IOP terminates the execution of its program, it sends an interrupt
request to the CPU.
● The CPU responds to the interrupt by issuing an instruction to read the
status from the IOP.
● The IOP responds by placing the contents of its status report into a specified
memory location.
● The status word indicates whether the transfer has been completed or if any
errors occurred during the transfer.
● From inspection of the bits in the status word, the CPU determines if the I/O
operation was completed satisfactorily without errors.
CPU Operations IOP Operations
Send instruction to test Transfer status word to
IOP path memory location
If status OK, send start Access memory for IOP
I/O instruction to IOP program
IOP Program
CPU Program
CPU continues with Conduct I/O transfer using
another program DMA: prepare status report
Request IOP status I/O transfer completed
interrupt CPU
Check status word for Transfer status word to
correct transfer memory location
Continue
Serial communication
Serial communication refers to the process of transmitting data in a sequential manner, one
bit at a time, over a single wire or channel. It is an important aspect of embedded systems,
allowing for the exchange of information between different devices. There are two main
types of serial communication: synchronous, where data is transmitted in sync with a clock
signal, and asynchronous, where data is transmitted without a clock signal.
Serial communication is used for transmitting data over long distances.
Data Transmission:
● Bit-By-Bit: Data is sent sequentially, which simplifies the wiring but can be
slower compared to parallel communication.
● Synchronous vs. Asynchronous:
○ Synchronous: Data is sent with a clock signal, allowing the sender and
receiver to stay in sync.
○ Asynchronous: Data is sent without a clock signal; start and stop bits are
used to indicate the beginning and end of transmission.
Protocols:
● Common serial communication protocols include:
○ UART (Universal Asynchronous Receiver/Transmitter): A widely used
protocol for asynchronous serial communication.
○ SPI (Serial Peripheral Interface): Used for synchronous communication,
often between microcontrollers and peripherals.
○ I2C (Inter-Integrated Circuit): Another synchronous protocol, often used
for communication between chips on the same board.
Advantages:
● Simplicity: Requires fewer wires and can be easier to implement.
● Longer Distances: Better suited for longer distances compared to
parallel communication, as it minimizes issues like crosstalk.
Applications:
● Serial communication is commonly used in embedded systems,
communication between microcontrollers, and in various peripheral
interfaces.
Performance:
● While serial communication can be slower than parallel for short
distances, advances in technology (like USB and high-speed serial
protocols) have made it very efficient for many applications.
Transmission mode - serial communication
Simplex refers to one-way communication technology. There is only one client (the sender or
receiver is active at the same time). If the sender sends it, the receiver can only accept it. Television
communication is a simplex mode, the television station sends and the television receives.
In half-duplex mode, both the sender and the receiver are active, but not active at the
same time, ie if the sender sends, the receiver can accept but not send, and vice versa.
The Internet is a good example. If the laptop sends a request for a web page, the web
server will process the application and send back the information.
Full-duplex mode is widely used in the world for communication. Both the sender
and the receiver can send and receive at the same time. An example is your
smartphone.
I/O Controller
An I/O (Input/Output) controller is a hardware component or chip that manages the
communication between a computer’s central processing unit (CPU) and its input
and output devices, such as keyboards, mouse, and storage peripherals. It functions
by transmitting data between the CPU and connected devices, ensuring efficient and
reliable data transfer.
some key functions and characteristics:
1. Data Management: The I/O controller handles the communication protocols
required for devices to send and receive data efficiently.
2. Buffering: It often includes buffers to temporarily store data during transfers,
helping to manage speed differences between the CPU and peripheral devices.
3. Interrupt Handling: The controller can generate interrupts to alert the CPU that
a device is ready for data transfer, improving overall system efficiency.
4. Device Coordination: It manages multiple devices, ensuring that each
receives the necessary resources and attention from the CPU.
5. Types: There are various types of I/O controllers, such as disk controllers,
network interface cards (NICs), and USB controllers, each tailored to specific
types of devices and communication standards.
There are several types of I/O controllers, each designed to manage different types of
peripherals and data transfer processes
Disk Controllers:
● SATA Controllers: Manage connections to SATA hard drives and SSDs.
● SAS Controllers: Used for connecting Serial Attached SCSI drives, often in enterprise
environments.
● IDE Controllers: Older standard for connecting hard drives and CD-ROMs.
[SATA, or Serial Advanced Technology Attachment, is a standard interface used for connecting hard
drives and SSDs (solid-state drives) to a computer's motherboard.
SAS, or Serial Attached SCSI (Small Computer System Interface), is an interface designed for
connecting storage devices like hard drives and SSDs]
Network Interface Controllers (NICs):
● Facilitate communication over a network, whether wired (Ethernet) or wireless (Wi-Fi).
USB Controllers:
● Manage connections for USB devices like keyboards, mouse, and external storage.
Graphics Controllers:
● Handle the communication between the CPU and the graphics card, managing rendering
tasks.
Audio Controllers:
● Manage audio output and input, allowing for connections to speakers, microphones, and
headphones.
Peripheral Controllers:
● Control other peripherals like printers, scanners, and game controllers.
Serial and Parallel Controllers:
● Manage older interfaces for connecting devices like modems and printers (e.g., RS-232 for
serial and Centronics for parallel).
Human Interface Device (HID) Controllers:
● Designed for devices like keyboards and mouse that provide input to the computer.