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basic_examples_tb.v

E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\3. Dataflow Level Modeling\4. Basic Examples Using Dataflow Level
Modeling\basic_examples_tb.v

1 `timescale 1ns/1ns
2 `include "basic_example.v"
3
4
5 module basic_example_tb;
6
7 // module tb_mux4_to_1
8 reg i0, i1, i2, i3;
9 reg s1, s0;
10 wire out;
11
12 // Instantiate the 4-to-1 MUX module
13 mux4_to_1 uut (out, i0, i1, i2, i3, s1, s0);
14
15 initial begin
16 $monitor("Time=%0t | s1=%b, s0=%b, i0=%b, i1=%b, i2=%b, i3=%b | out=%b",
17 $time, s1, s0, i0, i1, i2, i3, out);
18
19 // Test cases
20 i0 = 1; i1 = 0; i2 = 1; i3 = 0; s1 = 0; s0 = 0; #10;
21 i0 = 1; i1 = 0; i2 = 1; i3 = 0; s1 = 0; s0 = 1; #10;
22 i0 = 1; i1 = 0; i2 = 1; i3 = 0; s1 = 1; s0 = 0; #10;
23 i0 = 1; i1 = 0; i2 = 1; i3 = 0; s1 = 1; s0 = 1; #10;
24 $finish;
25
26 end
27
28 // module tb_multiplexer4_to_1­
29 reg[2:0] i0, i1, i2, i3;
30 reg s1, s0;
31 wire [2:0] out;
32
33 // Instantiate the 4-to-1 MUX module
34 multiplexer4_to_1 uut (out, i0, i1, i2, i3, s1, s0);

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basic_examples_tb.v

35
36 initial begin
37 $monitor("Time=%0t | s1=%b, s0=%b, i0=%b, i1=%b, i2=%b, i3=%b | out=%b",
38 $time, s1, s0, i0, i1, i2, i3, out);
39 // Test cases
40 i0 = 1; i1 = 2; i2 = 3; i3 = 4; s1 = 0; s0 = 0; #10;
41 i0 = 1; i1 = 2; i2 = 3; i3 = 4; s1 = 0; s0 = 1; #10;
42 i0 = 1; i1 = 2; i2 = 3; i3 = 4; s1 = 1; s0 = 0; #10;
43 i0 = 1; i1 = 2; i2 = 3; i3 = 4; s1 = 1; s0 = 1; #10;
44 $finish;
45 end
46
47
48 // module tb_fulladd4
49 reg [3:0] a, b;
50 reg c_in;
51 wire [3:0] sum;
52 wire c_out;
53
54 // Instantiate the 4-bit Full Adder module
55 fulladd4 uut (sum, c_out, a, b, c_in);
56
57 initial begin
58 $monitor("Time=%0t | a=%b, b=%b, c_in=%b | sum=%b, c_out=%b",
59 $time, a, b, c_in, sum, c_out);
60 // Test cases
61 a = 4'b0001; b = 4'b0010; c_in = 0; #10;
62 a = 4'b0101; b = 4'b1010; c_in = 1; #10;
63 a = 4'b1111; b = 4'b0001; c_in = 1; #10;
64 $finish;
65 end
66
67 // module tb_fulladd4_cla
68 reg [3:0] a, b;
69 reg c_in;
70 wire [3:0] sum;
71 wire c_out;

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basic_examples_tb.v

72
73 // Instantiate the 4-bit Full Adder with CLA module
74 fulladd4_cla uut (sum, c_out, a, b, c_in);
75
76 initial begin
77 $monitor("Time=%0t | a=%b, b=%b, c_in=%b | sum=%b, c_out=%b",
78 $time, a, b, c_in, sum, c_out);
79 // Test cases
80 a = 4'b0001; b = 4'b0010; c_in = 0; #10;
81 a = 4'b0101; b = 4'b1010; c_in = 1; #10;
82 a = 4'b1111; b = 4'b0001; c_in = 1; #10;
83 $finish;
84 end
85
86
87
88
89
90 // Testbench for Ripple Counter
91
92 reg CLOCK, CLEAR;
93 wire [3:0] Q;
94 counter c1 (Q, CLOCK, CLEAR);
95
96 initial begin
97 CLEAR = 1'b1;
98 #34 CLEAR = 1'b0;
99 #350 CLEAR = 1'b1;
100 #50 CLEAR = 1'b0;
101 end
102
103 initial begin
104 CLOCK = 1'b0;
105 forever #10 CLOCK = ~CLOCK;
106 end
107
108 initial begin

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basic_examples_tb.v

109 $monitor($time, " Count Q = %b Clear = %b", Q, CLEAR);

110 #400 $finish;
111 end
112
113 initial begin
114 $dumpfile("basic_example.vcd");
115 $dumpvars(0,basic_example_tb);
116
117
118
119
120
121 end
122
123 endmodule
124
125

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chp5_solutions_tb.v

E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\2. GATE Level Modeling\4. Exercise Solutions\chp5_solutions_tb.v

1 `timescale 1ns/1ns
2 `include "chp5_solutions.v"
3
4 module chp5_solutions_tb;
5
6 // Question_1
7 reg A, B;
8 wire AND_OUT, OR_OUT, NOT_OUT;
9
10 // Instantiate gates
11 my_and u1(AND_OUT, A, B);
12 my_or u2(OR_OUT, A, B);
13 my_not u3(NOT_OUT, A);
14
15 initial begin
16
17 $monitor("A=%b B=%b | AND_OUT=%b OR_OUT=%b NOT_OUT=%b", A, B, AND_OUT, OR_OUT, NOT_OUT);
18 A = 0; B = 0; #5;
19 A = 0; B = 1; #5;
20 A = 1; B = 0; #5;
21 A = 1; B = 1; #5;
22
23 $finish;
24
25 end
26
27
28 // Question_2
29
30 reg X, Y;
31 wire Z;
32
33 // Instantiate XOR gate
34 my_xor u1(Z, X, Y);

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chp5_solutions_tb.v

35
36 initial begin
37 $monitor("X=%b Y=%b | Z=%b", X, Y, Z);
38
39 X = 0; Y = 0; #5;
40 X = 0; Y = 1; #5;
41 X = 1; Y = 0; #5;
42 X = 1; Y = 1; #5;
43
44 $finish;
45 end
46
47 // Question_3
48
49 reg A, B, CIN;
50 wire SUM, COUT;
51
52 // Instantiate Full Adder
53 full_adder u1(SUM, COUT, A, B, CIN);
54
55 initial begin
56
57 $monitor("A=%b B=%b CIN=%b | SUM=%b COUT=%b", A, B, CIN, SUM, COUT);
58
59 A = 0; B = 0; CIN = 0; #5;
60 A = 0; B = 0; CIN = 1; #5;
61 A = 0; B = 1; CIN = 0; #5;
62 A = 0; B = 1; CIN = 1; #5;
63 A = 1; B = 0; CIN = 0; #5;
64 A = 1; B = 0; CIN = 1; #5;
65 A = 1; B = 1; CIN = 0; #5;
66 A = 1; B = 1; CIN = 1; #5;
67
68 $finish;
69 end
70
71

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chp5_solutions_tb.v

72 //Question_4
73
74
75 reg R, S;
76 wire Q, QBAR;
77
78 // Instantiate RS Latch
79 rs_latch u1(Q, QBAR, R, S);
80
81 initial begin
82
83 $monitor("R=%b S=%b | Q=%b QBAR=%b, Time : %0t", R, S, Q, QBAR,$time);
84
85 R = 0; S = 0; #5;
86 R = 0; S = 1; #5;
87 R = 1; S = 0; #5;
88 R = 1; S = 1; #5;
89
90 $finish;
91
92
93 end
94
95
96 // Question_5
97
98
99 reg IN0, IN1, S;
100 wire OUT;
101
102 // Instantiate Multiplexer
103 mux_2to1 u1(OUT, IN0, IN1, S);
104
105 initial begin
106
107 $monitor("IN0=%b IN1=%b S=%b | OUT=%b, Time : %0t", IN0, IN1, S, OUT,$time);
108

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chp5_solutions_tb.v

109 IN0 = 0; IN1 = 0; S = 0; #20;

110 IN0 = 0; IN1 = 1; S = 0; #20;
111 IN0 = 1; IN1 = 0; S = 1; #20;
112 IN0 = 1; IN1 = 1; S = 1; #20;
113
114 $finish;
115
116 end
117
118
119
120
121
122
123
124 initial begin
125 $dumpfile("chp5_solutions_tb.vcd");
126 $dumpvars(0,chp5_solutions_tb);
127
128
129
130
131
132
133 end
134 endmodule
135
136

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E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\3. Dataflow Level Modeling\5. Exercise
Solutions\chp6_solutions_tb.v

1 `timescale 1ns/1ns
2 `include "chp6_solutions.v"
3
4 module chp6_solutions_tb;
5
6 // Stimulus module to test the Full Subtractor
7 //Question_1
8 reg x, y, z; // Inputs
9 wire D, B; // Outputs
10
11 initial begin
12 //Question_1
13 $monitor($time, " x=%b, y=%b, z=%b -> D=%b, B=%b", x, y, z, D, B);
14 // Test all 8 possible combinations of inputs
15 x = 0; y = 0; z = 0; #10;
16 x = 0; y = 0; z = 1; #10;
17 x = 0; y = 1; z = 0; #10;
18 x = 0; y = 1; z = 1; #10;
19 x = 1; y = 0; z = 0; #10;
20 x = 1; y = 0; z = 1; #10;
21 x = 1; y = 1; z = 0; #10;
22 x = 1; y = 1; z = 1; #10;
23 end
24
25 // Instantiate the Full Subtractor
26 full_subtractor fs(D, B, x, y, z);
27
28 //Question_2
29
30
31
32 // Stimulus module
33
34 reg [3:0] A, B; // Inputs
35 wire A_gt_B, A_lt_B, A_eq_B; // Outputs
36
37 //Question_2
38 initial begin
39 $monitor($time, " A=%b, B=%b -> A_gt_B=%b, A_lt_B=%b, A_eq_B=%b", A, B, A_gt_B,
A_lt_B, A_eq_B);
40
41 // Test cases
42 A = 4'b1010; B = 4'b1001; #10;
43 A = 4'b1001; B = 4'b1010; #10;
44 A = 4'b1100; B = 4'b1100; #10;
45 A = 4'b0110; B = 4'b1110; #10;
46 end
47
48 // Instantiate the Magnitude Comparator
49 magnitude_comparator­mc(A_gt_B, A_lt_B, A_eq_B, A, B);
50

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51
52 //Question_3
53 // Stimulus Module
54 reg clock, clear, count_enable;
55 wire [3:0] Q;
56
57 // Instantiate the 4-bit synchronous counter
58 sync_counter uut (
59 .Q(Q),
60 .clock(clock),
61 .clear(clear),
62 .count_enable(count_enable)
63 );
64
65 // Clock generation (50% duty cycle, period = 10ns)
66 always #5 clock = ~clock;
67
68 initial begin
69
70
71 // Initialize signals
72 clock = 0;
73 clear = 0; // Apply reset
74 count_enable = 0;
75 #10;
76
77 clear = 1; // Release reset
78 count_enable = 1; // Enable counting
79 #100; // Run for 100 ns
80
81 count_enable = 0; // Disable counting
82 #20;
83
84 count_enable = 1; // Re-enable counting
85 #150 clear = 0;
86
87 #100 $finish; // End simulation
88 end
89
90 // Monitor outputs
91 initial begin
92 $monitor("Time = %t | Q = %b | clear = %b | count_enable = %b", $time, Q, clear,
count_enable);
93 end
94
95
96 // Testbench for Master-Slave JK Flip-Flop
97
98
99 reg j, k, clear, clock;
100 wire q, qbar;
101
102 // Instantiate the JK Flip-Flop module
103 jk_flipflop uut (

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104 .j(j),
105 .k(k),
106 .clear(clear),
107 .clock(clock),
108 .q(q),
109 .qbar(qbar)
110 );
111
112 // Clock generation (50% duty cycle)
113 always #5 clock = ~clock; // Toggle every 5ns
114
115 initial begin
116 // Monitor values
117 $monitor("Time=%0t | J=%b K=%b Clear=%b Clock=%b | Q=%b Qbar=%b",
118 $time, j, k, clear, clock, q, qbar);
119
120 // Initialize inputs
121 clock = 0;
122 clear = 1; j = 0; k = 0; #10;
123
124 clear = 0; #10; // Apply clear signal
125 clear = 1; #10; // Release clear
126
127 // Test all JK Flip-Flop conditions
128 j = 0; k = 0; #10; // No Change
129 j = 0; k = 1; #10; // Reset Q = 0
130 j = 1; k = 0; #10; // Set Q = 1
131 j = 1; k = 1; #10; // Toggle
132
133 // Test with Clear
134 clear = 0; #10; // Force Reset
135 clear = 1; #10; // Release Reset
136
137 $finish;
138 end
139
140
141
142
143
144
145
146
147 initial begin
148 $dumpfile("chp6_solutions_tb.vcd");
149 $dumpvars(0,chp6_solutions_tb);
150
151
152
153 end
154 endmodule
155
156

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chp7_solutions_tb.v

E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\4. Behavioral Level Modeling\8. Exercise

Solutions\chp7_solutions_tb.v

1 `timescale 1ns/1ns
2 `include "chp7_solutions.v"
3
4 module chp7_solutions_tb;
5
6 //Question_1
7 // module tb_oscillate
8 wire oscillate;
9 oscillate_test uut(oscillate);
10 initial begin
11 $monitor("Time = %0d, Oscillate = %b", $time, oscillate);
12 #200 $finish; // Stop simulation after 200 time units
13 end
14
15 //Question_2
16 // module tb_clock;
17 wire clock;
18
19 clock_test uut(clock);
20
21 initial begin
22 $monitor("Time = %0d, Clock = %b", $time, clock);
23 #200 $finish; // Stop simulation after 200 time units //Open GTKwave
24 end
25
26
27 Stimulus for Question 3,4,5 & 6
28 Blocking (#3) and Nonblocking (#4) procedural assignments:
29 Directly run the modules
30
31
32 //Stimulus for Question_7
33
34 reg d, clock, clear;
35 wire q;
36
37 d_ff_sync_clear uut (q, d, clock, clear); // Instance of DFF with synchronous clear
38
39 always #5 clock = ~clock; // Clock generation
40
41 initial begin
42 clock = 0; clear = 0; d = 0;
43 #10 d = 1; clear = 1; // Assert clear
44 #10 clear = 0; // Deassert clear
45 #10 d = 0;
46 #50 $finish; // Stop simulation
47 end
48
49 initial begin
50 $monitor("Time = %0d, d = %b, q = %b, clear = %b", $time, d, q, clear);
51 end

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52
53
54 //Stimulus for Question_8
55
56 reg d, clock, clear;
57 wire q;
58
59 d_ff_async_clear uut (q, d, clock, clear); // Instance of DFF with asynchronous clear
60
61 always #5 clock = ~clock; // Clock generation
62
63 initial begin
64 clock = 0; clear = 0; d = 0;
65 #1 d = 1; clear = 1; // Assert clear, Play around with this
66 #10 clear = 0; // Deassert clear
67 #10 d = 0;
68 #50 $finish; // Stop simulation
69 end
70
71 initial begin
72 $monitor("Time = %0d, d = %b, q = %b, clear = %b", $time, d, q, clear);
73 end
74
75
76 //Stimulus for Question_9
77 // module tb_level_sensitive_l­
atch
78 reg clock, d;
79 wire q;
80
81 latch uut (q, d, clock); // Instance of latch
82
83 always #5 clock = ~clock; // Clock generation
84
85 initial begin
86 clock = 0; d = 0;
87 #10 d = 1;
88 #10 d = 0;
89 #30 $finish; // Stop simulation
90 end
91
92 initial begin
93 $monitor("Time = %0d, d = %b, q = %b, clock = %b", $time, d, q, clock);
94 end
95
96
97 //Stimulus for Question_10
98 // module tb_mux
99
100 reg i0, i1, i2, i3, s1, s0;
101 wire out;
102
103 mux4_to_1 uut (out, i0, i1, i2, i3, s1, s0); // Instance of 4-to-1 MUX
104
105 initial begin

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106 i0 = 0; i1 = 1; i2 = 0; i3 = 1;
107 s1 = 0; s0 = 0;
108 #10 s0 = 1;
109 #10 s1 = 1; s0 = 0;
110 #10 s0 = 1;
111 #10 s1 = 1'bx;
112 #50 $finish; // Stop simulation
113 end
114
115 initial begin
116 $monitor("Time = %0d, s1 = %b, s0 = %b, out = %b", $time, s1, s0, out);
117 end
118
119 //Stimulus for Question_11
120
121
122 // module stimulus;
123 reg CAR_ON_CNTRY_RD; // Car presence on country road
124 reg CLOCK, CLEAR; // Clock and Reset signals
125 wire [1:0] MAIN_SIG, CNTRY_SIG; // Highway and Country signals
126
127 // Instantiate Traffic Signal Controller
128 sig_control SC (
129 .hwy(MAIN_SIG),
130 .cntry(CNTRY_SIG),
131 .X(CAR_ON_CNTRY_RD),
132 .clock(CLOCK),
133 .clear(CLEAR)
134 );
135
136 // Monitor Outputs
137 initial begin
138 $monitor($time, " | HWY: %b | CNTRY: %b | CAR: %b", MAIN_SIG, CNTRY_SIG,
CAR_ON_CNTRY_RD);
139 end
140
141 // Clock Generation
142 initial begin
143 CLOCK = 0;
144 forever #5 CLOCK = ~CLOCK; // 10ns clock cycle
145 end
146
147 // Clear Signal (Reset)
148 initial begin
149 CLEAR = 1; // Activate reset
150 repeat(5) @(negedge CLOCK);
151 CLEAR = 0; // Deactivate reset
152 end
153
154 // Apply Test Cases
155 initial begin
156 CAR_ON_CNTRY_RD = 0; // No car initially
157 repeat(20) @(negedge CLOCK);
158

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159 CAR_ON_CNTRY_RD = 1; // Car appears on country road

160 repeat(10) @(negedge CLOCK);
161
162 CAR_ON_CNTRY_RD = 0; // Car leaves
163 repeat(20) @(negedge CLOCK);
164
165 CAR_ON_CNTRY_RD = 1; // Car appears again
166 repeat(10) @(negedge CLOCK);
167
168 CAR_ON_CNTRY_RD = 0; // Car leaves again
169 repeat(20) @(negedge CLOCK);
170
171 CAR_ON_CNTRY_RD = 1; // Car arrives again
172 repeat(10) @(negedge CLOCK);
173
174 $stop; // End simulation
175 end
176
177
178 //Stimulus for Question_12
179 // module tb_alu
180
181 reg [3:0] a, b;
182 reg [2:0] select;
183 wire [4:0] out;
184
185 alu uut (out, a, b, select); // Instance of ALU
186
187 initial begin
188 a = 4'd5; b = 4'd3; select = 3'b000;
189 $display("Storing a");
190 #10 select = 3'b001;
191 $display("Performing a + b");
192 #10 select = 3'b010;
193 $display("Performing a - b");
194 #10 select = 3'b011;
195 $display("Performing a / b");
196 #10 select = 3'b100;
197 $display("Performing a %% b(remainder)");
198 #10 select = 3'b101;
199 $display("Performing a << b");
200 #10 select = 3'b110;
201 $display("Performing a >> b");
202 #10 select = 3'b111;
203 $display("Magnitude compare (a > b)");
204 #10 select = 3'bz;
205 $display("Invalid ALU Command");
206 #50 $finish; // Stop simulation
207 end
208
209 initial begin
210 $monitor("Time = %0d, a = %d, b = %d, select = %b, out = %d", $time, a, b, select,
out);
211 end

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212
213
214 // Stimulus for Question 13
215
216 wire clock;
217 clock_gen uut(clock);
218 initial begin
219 #0 $monitor("Time : %0t, Clock = %b",$time,clock);
220 #30 $finish;
221 end
222
223 Stimulus for Question 14,15,16,17
224 Directly Run
225
226 // Stimulus for Question 15
227
228 wire clock;
229 clock_gen uut(clock);
230 initial begin
231 #0 $monitor("Time : %0t, Clock = %b",$time,clock);
232 #30 $finish;
233 end
234
235 //Question_18
236 // module tb_counter_test
237 // Stimulus for Question 15
238
239 wire [7:0] counter;
240 counter_test uut(counter);
241 initial begin
242 #0 $monitor("Time : %0t, Counter = %d",$time,counter);
243 #1000 $finish;
244 end
245
246
247
248 initial begin
249 $dumpfile("chp7_solutions_tb.vcd");
250 $dumpvars(0,chp7_solutions_tb);
251
252 end
253 endmodule
254
255

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E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\4. Behavioral Level Modeling\7.
Examples\1. Combinational\Combinational_circuits_examples_tb.v

1 `timescale 1ns/1ns
2 `include "Combinational_circui­
ts_examples.v"
3
4 module Combinational_circui­
ts_examples_tb;
5
6 // stimulus_mux4_to_1;
7 // Declare wires and registers
8 wire out;
9 reg i0, i1, i2, i3;
10 reg s1, s0;
11
12 // Instantiate the multiplexer module
13 mux4_to_1 uut (out, i0, i1, i2, i3, s1, s0);
14
15 // Apply stimulus
16 initial begin
17 // Monitor outputs
18 $monitor($time, " i0=%b, i1=%b, i2=%b, i3=%b, s1=%b, s0=%b, out=%b",
19 i0, i1, i2, i3, s1, s0, out);
20
21 // Initialize inputs
22 i0 = 0; i1 = 0; i2 = 0; i3 = 0; s1 = 0; s0 = 0;
23
24 // Test all select signal combinations
25 #10 i0 = 1; s1 = 0; s0 = 0; // Select i0
26 #10 i1 = 0; s1 = 0; s0 = 1; // Select i1
27 #10 i2 = 1; s1 = 1; s0 = 0; // Select i2
28 #10 i3 = 0; s1 = 1; s0 = 1; // Select i3
29 #10 i0 = 0; i1 = 0; i2 = 0; i3 = 0; s1 = 0; s0 = 0; // Reset inputs
30
31 #10 $finish; // Stop the simulation
32 end
33
34
35
36 // module counter_tb
37
38 reg clock, clear; // Declare clock and clear as registers
39 wire [3:0] Q; // Output of the counter
40
41 // Instantiate the counter module
42 counter uut (
43 .Q(Q),
44 .clock(clock),
45 .clear(clear)
46 );
47
48 // Generate Clock Signal (50% Duty Cycle)
49 initial
50 forever #5 clock = ~clock;
51

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52 // Test Sequence
53 initial begin
54 $monitor($time, " | clock=%b | clear=%b | Q=%d", clock, clear, Q);
55
56 // Initialize signals
57 clock = 0;
58 clear = 1; #10; // Apply reset
59 clear = 0; #50; // Let the counter run
60
61 clear = 1; #10; // Reset again
62 clear = 0; #50; // Let it run again
63
64 $finish; // End simulation
65 end
66
67
68
69
70 // Testbench for 2:1 Multiplexer
71 // module tb_mux_2_1_bh;
72 reg [1:0] I;
73 reg S;
74 wire Y;
75
76 mux_2_1_bh uut (.Y(Y), .I(I), .S(S));
77
78 initial begin
79 $monitor("Time=%0t | S=%b | I[1]=%b | I[0]=%b | Y=%b", $time, S, I[1], I[0], Y);
80 I = 2'b10; S = 0; #10;
81 I = 2'b10; S = 1; #10;
82 I = 2'b01; S = 0; #10;
83 I = 2'b01; S = 1; #10;
84 $finish;
85 end
86
87 // Testbench for 4:1 Multiplexer
88 // module tb_mux_4_1_df;
89 reg [3:0] I;
90 reg [1:0] S;
91 wire Y;
92
93 mux_4_1_df uut (.Y(Y), .I(I), .S(S));
94
95 initial begin
96 $monitor("Time=%0t | S=%b | I=%b | Y=%b", $time, S, I, Y);
97 I = 4'b1010; S = 2'b00; #10;
98 I = 4'b1010; S = 2'b01; #10;
99 I = 4'b1010; S = 2'b10; #10;
100 I = 4'b1010; S = 2'b11; #10;
101 $finish;
102 end
103
104 // Testbench for 2×4 Decoder
105 // module tb_decode_2_4_df;

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106 reg [1:0] I;
107 reg En;
108 wire [3:0] Y;
109
110 decode_2_4_df uut (.Y(Y), .I(I), .En(En));
111
112 initial begin
113 $monitor("Time=%0t | En=%b | I=%b | Y=%b", $time, En, I, Y);
114 En = 1; I = 2'b00; #10;
115 En = 1; I = 2'b01; #10;
116 En = 1; I = 2'b10; #10;
117 En = 1; I = 2'b11; #10;
118 En = 0; I = 2'b10; #10;
119 $finish;
120 end
121
122 // Testbench for 2×4 Decoder
123 // module tb_decode_2_4_bh;
124 reg [1:0] I;
125 reg En;
126 wire [3:0] Y;
127
128 decode_2_4_bh uut (.Y(Y), .I(I), .En(En));
129
130 initial begin
131 $monitor("Time=%0t | En=%b | I=%b | Y=%b", $time, En, I, Y);
132 En = 1; I = 2'b00; #10;
133 En = 1; I = 2'b01; #10;
134 En = 1; I = 2'b10; #10;
135 En = 1; I = 2'b11; #10;
136 En = 0; I = 2'b10; #10;
137 $finish;
138 end
139
140 // Testbench for 3×8 Decoder
141 // module tb_decode_3_8_df;
142 reg [2:0] I;
143 reg En;
144 wire [7:0] Y;
145
146 decode_3_8_df uut (.Y(Y), .I(I), .En(En));
147
148 initial begin
149 $monitor("Time=%0t | En=%b | I=%b | Y=%b", $time, En, I, Y);
150 En = 1; I = 3'b000; #10;
151 En = 1; I = 3'b001; #10;
152 En = 1; I = 3'b010; #10;
153 En = 1; I = 3'b011; #10;
154 En = 1; I = 3'b100; #10;
155 En = 1; I = 3'b101; #10;
156 En = 1; I = 3'b110; #10;
157 En = 1; I = 3'b111; #10;
158 En = 0; I = 3'b100; #10;
159 $finish;

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160 end
161
162
163 // module tb_encode_4_2_df;
164
165 // Inputs
166 reg [3:0] I;
167
168 // Outputs
169 wire [1:0] Y;
170 wire V;
171
172 // Instantiate the Unit Under Test (UUT)
173 encode_4_2_df uut (
174 .Y(Y),
175 .V(V),
176 .I(I)
177 );
178
179 initial begin
180 // Monitor the signals
181 $monitor("Time=%0t | I=%b | Y=%b | V=%b", $time, I, Y, V);
182
183 // Test cases
184 I = 4'b0000; #10;
185 I = 4'b0001; #10;
186 I = 4'b0010; #10;
187 I = 4'b0100; #10;
188 I = 4'b1000; #10;
189 I = 4'b1111; #10;
190
191 $finish;
192 end
193
194
195
196 // module tb_encode_4_2_bh;
197 reg [3:0] I; // Input
198 wire [1:0] Y; // Output
199 wire V; // Valid signal
200
201 // Instantiate the 4x2 Encoder
202 encode_4_2_bh uut(Y, V, I);
203
204 initial begin
205 // Monitor changes in inputs and outputs
206 $monitor("Time = %0t | I = %b | Y = %b | V = %b", $time, I, Y, V);
207
208 // Test cases
209 I = 4'b0001; #10; // Y = 00, V = 1
210 I = 4'b0010; #10; // Y = 01, V = 1
211 I = 4'b0100; #10; // Y = 10, V = 1
212 I = 4'b1000; #10; // Y = 11, V = 1
213 I = 4'b0000; #10; // Y = 00, V = 0 (invalid)

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214
215 $display("4x2 Encoder Test Complete");
216 end
217
218 // module encode_4_2_priority_­
tb
219
220 reg [3:0] I; // Test input
221 wire [1:0] Y; // Encoded output
222 wire V; // Valid signal
223
224 // Instantiate the encoder module
225 encode_4_2_priority_­
df uut (
226 .Y(Y),
227 .V(V),
228 .I(I)
229 );
230
231 // Test sequence
232 initial begin
233 $monitor($time, " | I = %b | V = %b | Y = %b", I, V, Y);
234
235 // Apply test cases
236 I = 4'b0000; #10; // No input set
237 I = 4'b0001; #10; // Lowest priority (I[0])
238 I = 4'b0010; #10; // I[1] set
239 I = 4'b0100; #10; // I[2] set
240 I = 4'b1000; #10; // Highest priority (I[3])
241 I = 4'b1100; #10; // Multiple bits set, highest priority (I[3]) should be encoded
242 I = 4'b1010; #10; // I[3] and I[1] set, I[3] should be encoded
243
244 $finish; // End simulation
245 end
246
247
248
249
250 // module tb_encode_4_2_priori­
ty_bh;
251
252 // Inputs
253 reg [3:0] I;
254
255 // Outputs
256 wire [1:0] Y;
257 wire V;
258
259 // Instantiate the Unit Under Test (UUT)
260 encode_4_2_priority_­
bh uut (
261 .Y(Y),
262 .V(V),
263 .I(I)
264 );
265
266 initial begin
267 // Monitor the signals

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268 $monitor("Time=%0t | I=%b | Y=%b | V=%b", $time, I, Y, V);
269
270 // Test cases
271 I = 4'b0000; #10;
272 I = 4'b0001; #10;
273 I = 4'b0010; #10;
274 I = 4'b0100; #10;
275 I = 4'b1000; #10;
276 I = 4'b1111; #10;
277
278 $finish;
279 end
280
281
282 // module comparator_tb
283
284 reg [3:0] A, B; // Test inputs
285 wire Eq, Gt, Sm; // Outputs
286
287 // Instantiate the comparator module
288 comparator_df1 uut (
289 .Eq(Eq),
290 .Gt(Gt),
291 .Sm(Sm),
292 .A(A),
293 .B(B)
294 );
295
296 // Test sequence
297 initial begin
298 $monitor($time, " | A = %b | B = %b | Eq = %b | Gt = %b | Sm = %b", A, B, Eq, Gt,
Sm);
299
300 // Apply test cases
301 A = 4'b0000; B = 4'b0000; #10; // A == B
302 A = 4'b1010; B = 4'b0101; #10; // A > B
303 A = 4'b0101; B = 4'b1010; #10; // A < B
304 A = 4'b1111; B = 4'b0000; #10; // A > B
305 A = 4'b0000; B = 4'b1111; #10; // A < B
306 A = 4'b0110; B = 4'b0110; #10; // A == B
307 A = 4'b1001; B = 4'b1000; #10; // A > B
308 A = 4'b1000; B = 4'b1001; #10; // A < B
309
310 $finish; // End simulation
311 end
312
313
314
315
316
317
318 // module tb_comparator_df2;
319
320 // Inputs

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321 reg [3:0] A, B;
322
323 // Outputs
324 wire Eq, Gt, Sm;
325
326 // Instantiate the Unit Under Test (UUT)
327 comparator_df2 uut (
328 .Eq(Eq),
329 .Gt(Gt),
330 .Sm(Sm),
331 .A(A),
332 .B(B)
333 );
334
335 initial begin
336 // Monitor the signals
337 $monitor("Time=%0t | A=%b | B=%b | Eq=%b | Gt=%b | Sm=%b", $time, A, B, Eq, Gt, Sm);
338
339 // Apply test cases
340 A = 4'b0000; B = 4'b0000; #10; // A == B
341 A = 4'b1010; B = 4'b0101; #10; // A > B
342 A = 4'b0101; B = 4'b1010; #10; // A < B
343 A = 4'b1111; B = 4'b0000; #10; // A > B
344 A = 4'b0000; B = 4'b1111; #10; // A < B
345 A = 4'b0110; B = 4'b0110; #10; // A == B
346 A = 4'b1001; B = 4'b1000; #10; // A > B
347 A = 4'b1000; B = 4'b1001; #10; // A < B
348
349 $finish; // End simulation
350
351 end
352
353 // module tb_comparator_bh;
354
355 // Inputs
356 reg [3:0] A, B;
357
358 // Outputs
359 wire Eq, Gt, Sm;
360
361 // Instantiate the Unit Under Test (UUT)
362 comparator_bh uut (
363 .Eq(Eq),
364 .Gt(Gt),
365 .Sm(Sm),
366 .A(A),
367 .B(B)
368 );
369
370 initial begin
371 // Monitor the signals
372 $monitor("Time=%0t | A=%b | B=%b | Eq=%b | Gt=%b | Sm=%b", $time, A, B, Eq, Gt, Sm);
373
374 // Apply test cases

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375 A = 4'b0000; B = 4'b0000; #10; // A == B
376 A = 4'b1010; B = 4'b0101; #10; // A > B
377 A = 4'b0101; B = 4'b1010; #10; // A < B
378 A = 4'b1111; B = 4'b0000; #10; // A > B
379 A = 4'b0000; B = 4'b1111; #10; // A < B
380 A = 4'b0110; B = 4'b0110; #10; // A == B
381 A = 4'b1001; B = 4'b1000; #10; // A > B
382 A = 4'b1000; B = 4'b1001; #10; // A < B
383
384 $finish; // End simulation
385 end
386
387 // module tb_barrel_bh;
388
389 // Inputs
390 reg [7:0] In;
391 reg [2:0] n;
392 reg Lr;
393
394 // Outputs
395 wire [7:0] Out;
396
397 // Instantiate the Unit Under Test (UUT)
398 barrel_bh uut (
399 .Out(Out),
400 .In(In),
401 .Lr(Lr),
402 .n(n)
403 );
404
405 initial begin
406 // Monitor the signals
407 $monitor("Time=%0t | In=%b | n=%b | Lr=%b | Out=%b", $time, In, n, Lr, Out);
408
409 // Test cases
410 In = 8'b10101010; n = 3'b001; Lr = 1; #10; // Left shift
411 In = 8'b10101010; n = 3'b010; Lr = 0; #10; // Right shift
412 In = 8'b11001100; n = 3'b100; Lr = 1; #10; // Left shift
413 In = 8'b11110000; n = 3'b011; Lr = 0; #10; // Right shift
414
415 $finish;
416 end
417
418 // module tb_ALU;
419
420 // Inputs
421 reg [3:0] a, b;
422 reg [3:0] opcode;
423
424 // Outputs
425 wire [3:0] x;
426 wire [3:0] y;
427
428 // Instantiate the Unit Under Test (UUT)

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429 ALU uut (
430 .x(x),
431 .y(y),
432 .a(a),
433 .b(b),
434 .opcode(opcode)
435 );
436
437 initial begin
438 // Monitor the signals
439 $monitor("Time=%0t | a=%b | b=%b | opcode=%b | x=%b | y=%b", $time, a, b, opcode, x,
y);
440
441 // Test cases
442 a = 4'b0011; b = 4'b0101; opcode = 4'b1010; #10; // Addition
443 a = 4'b1100; b = 4'b0111; opcode = 4'b1011; #10; // Subtraction
444 a = 4'b0110; b = 4'b0010; opcode = 4'b0100; #10; // OR
445 a = 4'b1101; b = 4'b1011; opcode = 4'b0010; #10; // XOR
446
447 $finish;
448 end
449
450
451
452
453 initial begin
454 ts_examples.vcd");
$dumpfile("Combinational_circui­
455 $dumpvars(0,Combinational_circui­ts_examples_tb);
456
457 end
458
459 endmodule
460
461

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conditional_statements_tb.v

E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\4. Behavioral Level Modeling\3.

Conditional Statements\conditional_statements_tb.v

1 `timescale 1ns/1ns
2 `include "conditional_statemen­
ts.v"
3
4 module conditional_statemen­
ts_tb;
5
6
7 // Stimulus for Simple If Statement
8 reg lock, enable;
9 reg [7:0] data, in;
10 wire [7:0] buffer, out;
11
12 // Instantiate the module
13 simple_if_statements­uut (
14 .lock(lock),
15 .enable(enable),
16 .data(data),
17 .in(in),
18 .buffer(buffer),
19 .out(out)
20 );
21
22 initial begin
23 $display("Test for Simple If Statements");
24 $display("Time\tLock\tEnable\tData\tIn\tBuffer\tOut");
25
26 // Test Case 1: Lock active, enable inactive
27 lock = 1; enable = 0; data = 8'hA5; in = 8'hFF;
28 #10 $display("%0t\t%b\t%b\t%h\t%h\t%h\t%h", $time, lock, enable, data, in, buffer,
out);
29
30 // Test Case 2: Lock inactive, enable active
31 lock = 0; enable = 1; data = 8'hB4; in = 8'hCC;
32 #10 $display("%0t\t%b\t%b\t%h\t%h\t%h\t%h", $time, lock, enable, data, in, buffer,
out);
33
34 // Test Case 3: Both lock and enable active
35 lock = 1; enable = 1; data = 8'h77; in = 8'h88;
36 #10 $display("%0t\t%b\t%b\t%h\t%h\t%h\t%h", $time, lock, enable, data, in, buffer,
out);
37
38 $finish;
39 end
40
41
42 // Stimulus for else If Statement
43 reg [3:0] number_queued, MAX_Q_DEPTH;
44 reg [7:0] data;
45 wire [7:0] data_queue;
46 wire [3:0] next_depth;
47
48 // Instantiate the module

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conditional_statements_tb.v

49 if_else_statements uut (
50 .number_queued(number_queued),
51 .MAX_Q_DEPTH(MAX_Q_DEPTH),
52 .data(data),
53 .data_queue(data_queue),
54 .next_depth(next_depth)
55 );
56
57 initial begin
58 $display("Test for If-Else Statements");
59 $display("Time\tNumber_Queued\tMax_Q_Depth\tData\tData_Queue\tNext_Depth");
60 $monitor("%0t\t%0d\t\t%0d\t\t%0h\t%0h\t\t%0d", $time, number_queued, MAX_Q_DEPTH,
data, data_queue, next_depth);
61 // Test Case 1: Space available in queue
62 number_queued = 4; MAX_Q_DEPTH = 8; data = 8'hAA;
63
64
65 // Test Case 2: Queue full
66 #10 number_queued = 8; MAX_Q_DEPTH = 8; data = 8'hBB;
67
68 #100 $finish;
69 end
70
71
72 // Stimulus for nested If else Statement
73
74 reg [1:0] alu_control;
75 reg [7:0] x, N, Z;
76 wire [7:0] y;
77
78 // Instantiate the module
79 nested_if_else_state­
ments uut (
80 .alu_control(alu_control),
81 .x(x),
82 .N(N),
83 .Z(Z),
84 .y(y)
85 );
86
87 initial begin
88 $display("Test for Nested If-Else-If Statements");
89 $display("Time\tALU_Control\tX\tN\tZ\tY");
90 $monitor("%0t\t%d\t\t%h\t%h\t%h\t%h", $time, alu_control, x, N, Z, y);
91 // Test Case 1: ALU control 0 (Addition)
92 alu_control = 0; x = 8'h10; N = 8'h20; Z = 8'h00;
93 #10 ;
94
95 // Test Case 2: ALU control 1 (Subtraction)
96 alu_control = 1; x = 8'h50; N = 8'h00; Z = 8'h10;
97 #10 ;
98
99 // Test Case 3: ALU control 2 (Multiplication)
100 alu_control = 2; x = 8'h02; N = 8'h00; Z = 8'h04;
101 #10 ;

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conditional_statements_tb.v

102
103 // Test Case 4: Invalid ALU control signal
104 alu_control = 3; x = 8'h00; N = 8'h00; Z = 8'h00;
105 #10 ;
106
107 $finish;
108 end
109
110
111 // module tb_case_example;
112 reg [3:0] value;
113 wire result;
114
115 // Instantiate the module
116 case_example uut (
117 .value(value),
118 .result(result)
119 );
120
121 initial begin
122 $display("Testing Multiway Branching");
123 $display("Time\tValue\tResult");
124
125 value = 4'b10xx; #10 $display("%0t\t%b\t%b", $time, value, result);
126 value = 4'b101z; #10 $display("%0t\t%b\t%b", $time, value, result);
127 value = 4'b1001; #10 $display("%0t\t%b\t%b", $time, value, result);
128 value = 4'b1010; #10 $display("%0t\t%b\t%b", $time, value, result);
129 value = 4'b0001; #10 $display("%0t\t%b\t%b", $time, value, result);
130
131 $finish;
132 end
133
134
135 // module tb_mux4_to_1;
136 reg i0, i1, i2, i3, s1, s0;
137 wire out;
138
139 // Instantiate the module
140 mux4_to_1 uut (
141 .out(out),
142 .i0(i0),
143 .i1(i1),
144 .i2(i2),
145 .i3(i3),
146 .s1(s1),
147 .s0(s0)
148 );
149
150 initial begin
151 $display("Testing 4-to-1 Multiplexer");
152 $display("Time\tS1 S0\tOut");
153
154 i0 = 1; i1 = 0; i2 = 1; i3 = 0;
155 {s1, s0} = 2'b00; #10 $display("%0t\t%b %b\t%b", $time, s1, s0, out);

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conditional_statements_tb.v

156 {s1, s0} = 2'b01; #10 $display("%0t\t%b %b\t%b", $time, s1, s0, out);
157 {s1, s0} = 2'b10; #10 $display("%0t\t%b %b\t%b", $time, s1, s0, out);
158 {s1, s0} = 2'b11; #10 $display("%0t\t%b %b\t%b", $time, s1, s0, out);
159
160 $finish;
161 end
162
163 // module tb_demultiplexer_1_t­
o_4;
164 reg in, s1, s0;
165 wire out0, out1, out2, out3;
166
167 // Instantiate the module
168 demultiplexer_1_to_4­uut (
169 .out0(out0),
170 .out1(out1),
171 .out2(out2),
172 .out3(out3),
173 .in(in),
174 .s1(s1),
175 .s0(s0)
176 );
177
178 initial begin
179 $display("Testing 1-to-4 Demultiplexer");
180 $display("Time\tS1 S0\tOut0\tOut1\tOut2\tOut3");
181
182 in = 1;
183 {s1, s0} = 2'b00; #10 $display("%0t\t%b %b\t%b\t%b\t%b\t%b", $time, s1, s0, out0,
out1, out2, out3);
184 {s1, s0} = 2'b01; #10 $display("%0t\t%b %b\t%b\t%b\t%b\t%b", $time, s1, s0, out0,
out1, out2, out3);
185 {s1, s0} = 2'b10; #10 $display("%0t\t%b %b\t%b\t%b\t%b\t%b", $time, s1, s0, out0,
out1, out2, out3);
186 {s1, s0} = 2'b11; #10 $display("%0t\t%b %b\t%b\t%b\t%b\t%b", $time, s1, s0, out0,
out1, out2, out3);
187
188 $finish;
189 end
190
191
192 // module tb_branching_with_ca­
sex;
193 reg [3:0] encoding;
194 wire [1:0] next_state;
195
196 // Instantiate the module
197 branching_with_casex­uut (
198 .encoding(encoding),
199 .next_state(next_state)
200 );
201
202 initial begin
203 $display("Testing Branching with casex");
204 $display("Time\tEncoding\tNext_State");
205

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206 encoding = 4'b1000; #10 $display("%0t\t%b\t\t%d", $time, encoding, next_state);

207 encoding = 4'b0100; #10 $display("%0t\t%b\t\t%d", $time, encoding, next_state);
208 encoding = 4'b0010; #10 $display("%0t\t%b\t\t%d", $time, encoding, next_state);
209 encoding = 4'b0001; #10 $display("%0t\t%b\t\t%d", $time, encoding, next_state);
210
211 $finish;
212 end
213
214
215 // module tb_action_decoder_ca­
sez;
216 reg [3:0] control_signal; // Input control signal
217 wire [7:0] action; // Output action from the module
218
219 // Instantiate the module
220 action_decoder_casez­uut (
221 .control_signal(control_signal),
222 .action(action)
223 );
224
225 initial begin
226 // Display header for the outputs
227 $display("Time\tControl Signal\tAction");
228
229 // Test cases
230 control_signal = 4'b1000; #10 $display("%0t\t%b\t\t%b", $time, control_signal,
action); // Matches 1zz0
231 control_signal = 4'b1100; #10 $display("%0t\t%b\t\t%b", $time, control_signal,
action); // Matches z10z
232 control_signal = 4'b0001; #10 $display("%0t\t%b\t\t%b", $time, control_signal,
action); // Matches zz01
233 control_signal = 4'b0110; #10 $display("%0t\t%b\t\t%b", $time, control_signal,
action); // Matches z11z
234 control_signal = 4'b1011; #10 $display("%0t\t%b\t\t%b", $time, control_signal,
action); // Default case
235
236 // Testing with wildcard
237 control_signal = 4'bz110; #10 $display("%0t\t%b\t\t%b", $time, control_signal,
action); // Matches z11z
238 control_signal = 4'b1z00; #10 $display("%0t\t%b\t\t%b", $time, control_signal,
action); // Matches 1zz0
239
240 // End simulation
241 $finish;
242 end
243
244
245
246
247
248
249 initial begin
250 #100 $dumpfile("conditional_statemen­
ts.vcd");
251 $dumpvars(0,conditional_statemen­
ts_tb);
252

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253 end
254
255 endmodule
256
257

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continuous_assignments_tb.v

E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\3. Dataflow Level Modeling\1. Continuous Assignments\continuous_assignments_tb.v

1 `timescale 1ns/1ns
2 `include "continuous_assignmen­
ts.v"
3
4
5
6 module continuous_assignmen­
ts_tb;
7
8 // Testbench for continuous_assign_ex­
amples
9 // module test_continuous_assi­
gn_examples
10 reg i1, i2; // Inputs for logical AND
11 reg [15:0] addr1_bits, addr2_bits; // Inputs for XOR operation
12 reg [3:0] a, b; // 4-bit numbers
13 reg c_in; // Carry-in bit
14 wire out; // Output for logical AND
15 wire [15:0] addr; // Output for XOR operation
16 wire [4:0] c_out; // Carry-out
17 wire [3:0] sum; // Sum of 4-bit numbers
18
19 // Instantiate the module
20 continuous_assign_ex­
amples uut (
21 .i1(i1),
22 .i2(i2),
23 .addr1_bits(addr1_bits),
24 .addr2_bits(addr2_bits),
25 .a(a),
26 .b(b),
27 .c_in(c_in),
28 .out(out),
29 .addr(addr),
30 .c_out(c_out),
31 .sum(sum)
32 );
33
34 initial begin

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continuous_assignments_tb.v

35 // Monitor signals
36 $monitor("Time: %0t | Inputs : i1 = %b, i2 = %b, addr1 = %h, addr2 = %h, a = %b, b = %b, c_in = %b | Outputs : out = %b, addr =
%h, c_out = %b, sum = %b",
37 $time, i1, i2, addr1_bits, addr2_bits, a, b, c_in, out, addr, c_out, sum);
38
39 // Test cases
40 i1 = 1; i2 = 0;
41 addr1_bits = 16'hABCD; addr2_bits = 16'h1234;
42 a = 4'b1100; b = 4'b0110; c_in = 1;
43 #10; // Wait 10 time units
44
45 i1 = 1; i2 = 1;
46 addr1_bits = 16'hFFFF; addr2_bits = 16'h0000;
47 a = 4'b1010; b = 4'b0101; c_in = 0;
48 #10;
49
50 $finish; // End simulation
51 end
52
53
54
55 // Testbench for implicit_vs_regular_­
assign
56 // module test_implicit_vs_reg­
ular_assign
57
58 reg i1, i2; // Inputs for AND operation
59 wire out_regular, out_implicit; // Outputs for regular and implicit assignments
60
61 // Instantiate the module
62 implicit_vs_regular_­
assign uut (
63 .i1(i1),
64 .i2(i2),
65 .out_regular(out_regular),
66 .out_implicit(out_implicit)
67 );
68
69 initial begin
70 // Monitor signals

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continuous_assignments_tb.v

71 $monitor("Time: %0t | i1 = %b, i2 = %b | Regular: %b, Implicit: %b",

72 $time, i1, i2, out_regular, out_implicit);
73
74 // Test cases
75 i1 = 0; i2 = 0;
76 #5;
77 i1 = 1; i2 = 0;
78 #5;
79 i1 = 1; i2 = 1;
80 #15;
81
82 $finish; // End simulation
83 end
84
85
86
87 initial begin
88 ts.vcd");
$dumpfile("continuous_assignmen­
89 $dumpvars(0,continuous_assignmen­ts_tb);
90
91
92
93
94
95 end
96
97 endmodule
98
99

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FSM_examples_tb.v

E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\4. Behavioral Level Modeling\7.

Examples\4. FSM\3. Misc\FSM_examples_tb.v

1 `timescale 1ns/1ns
2 `include "FSM_examples.v"
3
4 module FSM_examples_tb;
5
6 // module test_vending_machine­
;
7 // Testbench signals
8 reg clk;
9 reg reset;
10 reg [7:0] insert_cash;
11 reg [7:0] item_price;
12 reg item_available;
13 reg select_item;
14 reg cancel;
15 wire [7:0] dispensed_item;
16 wire [7:0] dispensed_change;
17 wire error;
18
19 // Instantiate the vending machine module
20 vending_machine_meal­
y vm (
21 .clk(clk),
22 .reset(reset),
23 .insert_cash(insert_cash),
24 .item_price(item_price),
25 .item_available(item_available),
26 .select_item(select_item),
27 .cancel(cancel),
28 .dispensed_item(dispensed_item),
29 .dispensed_change(dispensed_change),
30 .error(error)
31 );
32
33 // Clock generation
34 always begin
35 #5 clk = ~clk;
36 end
37
38 // Initial block to run the test cases
39 initial begin
40 // Initialize signals
41 clk = 0;
42 reset = 0;
43 insert_cash = 0;
44 item_price = 0;
45 item_available = 0;
46 select_item = 0;
47 cancel = 0;
48
49
50 // // Reset the machine
51 // #10 reset = 1;

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FSM_examples_tb.v

52 // #10 reset = 0;
53
54 // // Test Case 1: Insert cash and select item
55 // #10 insert_cash = 50; // Insert 50 units of cash
56 // #10 select_item = 1; // Item is selected
57 // item_available = 1; // Item is available //Somehow, Machine is getting input
58 // item_price = 30; // Item price is 30 //Somehow, Machine is getting input
59
60 // #30
61
62 // // Check that item is dispensed and no error
63 // if (dispensed_item != 8'b1 || error != 0)
64 // $display("Test Case 1 Failed");
65 // else $display("Test Case 1 Passed");
66
67
68
69 // // Reset the machine
70 // #10 reset = 1;
71 // #10 reset = 0;
72
73
74 // // Test Case 2: Insufficient cash
75 // insert_cash = 20; // Insert 20 units of cash
76 // #10 select_item = 1; // Item is selected
77 // item_price = 30; // Item price is 30
78 // item_available = 1; // Item is available
79
80 // #30;
81
82 // // Check for error due to insufficient cash
83 // if (error != 1)
84 // $display("Test Case 2 Failed");
85 // else $display("Test Case 2 Passed");
86
87 // // Reset the machine
88 // #10 reset = 1;
89 // #10 reset = 0;
90
91 // // Test Case 3: Cancel the transaction
92 // insert_cash = 40; // Insert 40 units of cash
93 // #10 cancel = 1; // Transaction is canceled
94 // #30;
95
96 // // Check that cash is returned
97 // if (dispensed_change != 40)
98 // $display("Test Case 3 Failed");
99 // else $display("Test Case 3 Passed");
100
101 // Reset the machine
102 #10 reset = 1;
103 #10 reset = 0;
104
105 cancel = 0;

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106 // Test Case 4: Item unavailable

107 insert_cash = 50; // Insert 50 units of cash
108 #10 select_item = 1; // Item is selected
109 item_price = 30; // Item price is 30
110 item_available = 0; // Item is unavailable
111
112 #30;
113
114 // Check for error due to item unavailability
115 if (error != 1)
116 $display("Test Case 4 Failed");
117 else $display("Test Case 4 Passed");
118 #10
119 $finish;
120 end
121
122
123
124 // stimulus Traffic Signal Controller
125
126 wire [1:0] MAIN_SIG, CNTRY_SIG;
127 reg CAR_ON_CNTRY_RD, CLOCK, CLEAR;
128
129 // Instantiate Traffic Signal Controller
130 sig_control SC(MAIN_SIG, CNTRY_SIG, CAR_ON_CNTRY_RD, CLOCK, CLEAR);
131
132 // Monitor signal changes
133 initial begin
134 $monitor("Time=%0t | HWY Signal=%b | CNTRY Signal=%b | CAR_ON_CNTRY_RD=%b",
135 $time, MAIN_SIG, CNTRY_SIG, CAR_ON_CNTRY_RD);
136 end
137
138 // Clock generation
139 initial begin
140 CLOCK = `FALSE;
141 forever #5 CLOCK = ~CLOCK; // Toggle every 5 time units
142 end
143
144 // Control reset signal
145 initial begin
146 CLEAR = `TRUE;
147 repeat (5) @(negedge CLOCK);
148 CLEAR = `FALSE;
149 end
150
151 // Apply test stimulus
152 initial begin
153 CAR_ON_CNTRY_RD = `FALSE;
154 repeat (20) @(negedge CLOCK);
155
156 CAR_ON_CNTRY_RD = `TRUE;
157 repeat (10) @(negedge CLOCK);
158
159 CAR_ON_CNTRY_RD = `FALSE;

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FSM_examples_tb.v

160 repeat (20) @(negedge CLOCK);

161
162 CAR_ON_CNTRY_RD = `TRUE;
163 repeat (10) @(negedge CLOCK);
164
165 CAR_ON_CNTRY_RD = `FALSE;
166 repeat (20) @(negedge CLOCK);
167
168 CAR_ON_CNTRY_RD = `TRUE;
169 repeat (10) @(negedge CLOCK);
170
171 CAR_ON_CNTRY_RD = `FALSE;
172 repeat (10) @(negedge CLOCK);
173
174 $finish;
175 end
176
177
178
179
180 initial begin
181 $dumpfile("FSM_examples.vcd");
182 $dumpvars(0,FSM_examples_tb);
183
184 end
185
186 endmodule
187
188

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gate_delays_tb.v; YT @AnishSaha_

E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\2. GATE Level Modeling\3. Gate Delays\gate_delays_tb.v

1 `timescale 1ns/1ns
2 `include "gate_delays.v"
3
4 module gate_delays_tb;
5
6
7 reg A, B, C;
8 wire OUT;
9 D d1 (OUT, A, B, C);
10
11
12
13
14
15 initial begin
16 $dumpfile("gate_delays.vcd");
17 $dumpvars(0,gate_delays_tb);
18 A = 1'b0; B = 1'b0; C = 1'b0;
19 #10 A = 1'b1; B = 1'b1; C = 1'b1;
20 #10 A = 1'b1; B = 1'b0; C = 1'b0;
21 #20 $finish;
22
23
24 end
25
26 endmodule
27
28

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Lectures ; YT @AnishSaha_
E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\2. GATE Level Modeling\2. Gate Level modelling
examples\gate_level_modeling_examples_tb.v

1 `timescale 1ns/1ns
2 `include "gate_level_modeling_­
examples.v"
3
4 module gate_level_modeling_­
examples_tb;
5
6
7
8 // Set up variables
9 reg [3:0] A, B; // 4-bit input operands
10 reg CIN; // Carry input
11 wire [3:0] SUM; // 4-bit sum output
12 wire COUT; // Carry output
13
14 // Instantiate the 4-bit full adder module
15 fulladd4 FA(SUM, COUT, A, B, CIN);
16
17
18
19
20
21 // Set up monitoring for the signal values
22 initial begin
23 $monitor($time, " A = %b, B = %b, CIN = %b -> COUT = %b, SUM = %b", A, B, CIN, COUT, SUM);
24 end
25
26
27
28
29 initial begin
30 examples.vcd");
$dumpfile("gate_level_modeling_­
31 $dumpvars(0,gate_level_modeling_­examples_tb);
32
33 // Stimulate inputs
34

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Lectures ; YT @AnishSaha_
35 // Initial values
36 A = 4'd0; B = 4'd0; CIN = 1'b0;
37
38 // Stimulate various input combinations with delays
39 #5 A = 4'd3; B = 4'd4; CIN = 1'b0;
40 #5 A = 4'd2; B = 4'd5; CIN = 1'b0;
41 #5 A = 4'd9; B = 4'd9; CIN = 1'b0;
42 #5 A = 4'd10; B = 4'd15; CIN = 1'b0;
43 #5 A = 4'd10; B = 4'd5; CIN = 1'b1;
44
45 // End simulation
46 #5 $finish;
47
48
49 end
50
51 endmodule
52
53

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generate_blocks_tb.v

E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\4. Behavioral Level Modeling\6. Generate

Blocks\generate_blocks_tb.v

1 `timescale 1ns/1ns
2 `include "generate_blocks.v"
3
4 module generate_blocks_tb;
5
6
7 // stimulus_bitwise_xor­
;
8 // Declare wires and registers
9 parameter N = 3; //Default to 4-bit buses for simplicity
10 wire [N-1:0] out;
11 reg [N-1:0] i0, i1;
12
13 // Instantiate the bitwise_xor module
14 bitwise_xor #(.N(N)) uut (out, i0, i1);
15
16 // Apply stimulus
17 initial begin
18 // Monitor outputs
19 $monitor($time, " i0=%0b, i1=%0b, out=%0b, xor_loop.g1 = %0b", i0, i1,
out,uut.out[0]);
20
21 // Apply test cases
22 i0 = 4'b0000; i1 = 4'b0000; #10; // Test with all 0s
23 i0 = 4'b1010; i1 = 4'b0101; #10; // Test with alternating bits
24 i0 = 4'b1111; i1 = 4'b0000; #10; // Test with all 1s and 0s
25 i0 = 4'b1100; i1 = 4'b1010; #10; // Random test case
26
27 $finish; // Stop the simulation
28 end
29
30
31 // stimulus_ripple_adde­
r;
32 // Declare wires and registers
33 parameter N = 4; // Default to 4-bit adder
34 wire [N-1:0] sum;
35 wire co;
36 reg [N-1:0] a0, a1;
37 reg ci;
38
39 // Instantiate the ripple_adder module
40 ripple_adder #(N) uut (co, sum, a0, a1, ci);
41
42 // Apply stimulus
43 initial begin
44 // Monitor outputs
45 $monitor($time, " a0=%0b, a1=%0b, ci=%0b, sum=%0b, co=%0b,carry=%0b,r_loop[1].t1 =
%0b", uut.a0, uut.a1, uut.ci,uut.sum, uut.co,uut.carry,uut.r_loop[2].t1);
46
47
48 // Apply test cases
49 a0 = 4'b0000; a1 = 4'b0000; ci = 0; #10; // Test with all 0s

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generate_blocks_tb.v

50 a0 = 4'b0101; a1 = 4'b1010; ci = 0; #10; // Test with alternating bits

51 a0 = 4'b1111; a1 = 4'b0001; ci = 0; #10; // Test with carry generation
52 a0 = 4'b1111; a1 = 4'b1111; ci = 1; #10; // Test with all 1s and carry-in
53
54 $finish; // Stop the simulation
55 end
56
57
58
59 // module stimulus_multiplier;
60 parameter a0_width = 7; // Play arund with these default value is 8
61 parameter a1_width = 7;
62 localparam product_width = a0_width + a1_width;
63
64 reg [a0_width-1:0] a0; // Input a0
65 reg [a1_width-1:0] a1; // Input a1
66 wire [product_width-1:0] product; // Output product
67
68 // Instantiate the multiplier module
69 multiplier #(a0_width, a1_width) uut (
70 .product(product),
71 .a0(a0),
72 .a1(a1)
73 );
74
75 initial begin
76 $display("Starting simulation for Multiplier module...");
77
78 // Test Case 1
79 a0 = 8'h0F; a1 = 8'h03; #10;
80 $display("Test Case 1: a0 = %0d, a1 = %0d, product = %0d", a0, a1, product);
81
82 // Test Case 2
83 a0 = 8'hA5; a1 = 8'h1C; #10;
84 $display("Test Case 2: a0 = %0d, a1 = %0d, product = %0d", a0, a1, product);
85
86 // Test Case 3
87 a0 = 8'hFF; a1 = 8'hFF; #10;
88 $display("Test Case 3: a0 = %0d, a1 = %0d, product = %0d", a0, a1, product);
89
90 $display("Simulation completed.");
91 $finish;
92 end
93
94
95 // module stimulus_adder;
96 parameter N = 1; // Play around with the parameter
97 reg [N-1:0] a0, a1; // Inputs
98 reg ci; // Carry-in
99 wire [N-1:0] sum; // Sum output
100 wire co; // Carry-out
101
102 // Instantiate the adder module
103 adder #(N) uut (

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generate_blocks_tb.v

104 .co(co),
105 .sum(sum),
106 .a0(a0),
107 .a1(a1),
108 .ci(ci)
109 );
110
111 initial begin
112 $display("Starting simulation for Adder module...");
113
114 // Test Case 1
115 a0 = 4'b0011; a1 = 4'b0101; ci = 1'b0; #10;
116 $display("Test Case 1 in Binary : a0 = %b, a1 = %b, ci = %b, sum = %b, co = %b", a0,
a1, ci, sum, co);
117 $display("Test Case 1 in Decimal: a0 = %0d, a1 = %0d, ci = %0d, sum = %0d, co =
%0d", a0, a1, ci, sum, co);
118
119 // Test Case 2
120 a0 = 4'b1111; a1 = 4'b0001; ci = 1'b1; #10;
121 $display("Test Case 2 in Binary: a0 = %b, a1 = %b, ci = %b, sum = %b, co = %b", a0,
a1, ci, sum, co);
122 $display("Test Case 2 in Decimal: a0 = %0d, a1 = %0d, ci = %0d, sum = %0d, co =
%0d", a0, a1, ci, sum, co);
123 // Test Case 3
124 a0 = 4'b1010; a1 = 4'b0101; ci = 1'b0; #10;
125 $display("Test Case 3 in Binary: a0 = %b, a1 = %b, ci = %b, sum = %b, co = %b", a0,
a1, ci, sum, co);
126 $display("Test Case 3 in Decimal: a0 = %0d, a1 = %0d, ci = %0d, sum = %0d, co =
%0d", a0, a1, ci, sum, co);
127
128 $display("Simulation completed.");
129 $finish;
130 end
131
132
133
134
135 initial begin
136 #100 $dumpfile("generate_blocks.vcd");
137 $dumpvars(0,generate_blocks_tb);
138
139 end
140
141 endmodule
142
143

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initial_always_tb.v

E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\1. Basics of Verilog\5. Initial & always keyword\initial_always_tb.v

1 `timescale 1ns/1ns
2 `include "initial_always.v"
3
4 module initial_always_tb;
5
6
7 // instantiate the design block
8 stimulus mut();
9
10 wire clk;
11 clock_gen mut(clk);
12
13 reg [7:0] s;
14 reg c;
15 wire [7:0] a,b;
16 assign a= 8'd31;
17 assign b= 8'd25;
18
19 temp mut(s,c,a,b);
20
21
22
23
24
25 initial begin
26 $dumpfile("initial_always.vcd");
27 $dumpvars(0,initial_always_tb);
28
29 end
30
31 endmodule
32
33

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loops_tb.v

E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\4. Behavioral Level Modeling\4.

Loops\loops_tb.v

1 `timescale 1ns/1ns
2 `include "loops.v"
3
4 module loops_tb;
5
6 // module tb_while_loop_counte­
r;
7 initial begin
8 $monitor("Simulating While Loop Counter");
9 #10 $finish; // Finish simulation after some time
10 end
11
12 // module tb_while_loop_find_b­
it;
13 initial begin
14 $monitor("Testing While Loop for Finding First '1' Bit");
15 #20 $finish; // Simulation ends after 20 time units
16 end
17
18 // module tb_for_loop_counter;
19 initial begin
20 $monitor("Simulating For Loop Counter");
21 #10 $finish;
22 end
23
24
25 // module tb_for_loop_array_in­
it;
26 initial begin
27 $monitor("Testing For Loop Array Initialization");
28 #10 $finish;
29 end
30
31 // module tb_repeat_loop_count­
er;
32 initial begin
33 $monitor("Simulating Repeat Loop Counter");
34 #10 $finish;
35 end
36
37 // module stimulus_data_buffer­
;
38 reg data_start; // Control signal to start data buffering
39 reg [15:0] data; // Input data
40 reg clock; // Clock signal
41
42 // Instantiate the data buffer module
43 data_buffer db (
44 .data_start(data_start),
45 .data(data),
46 .clock(clock)
47 );
48
49 // Generate the clock signal
50 initial begin
51 clock = 0;

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loops_tb.v

52 forever #5 clock = ~clock; // Toggle clock every 5 time units

53 end
54
55 // Stimulus
56 initial begin
57 data_start = 0; // Start with data_start disabled
58 data = 16'hAAAA; // Initialize data
59 #10;
60
61 $display("Starting data buffering...");
62 data_start = 1; // Enable data_start
63 #10;
64
65 // Provide data inputs for 8 cycles
66 repeat (8) begin
67 @(posedge clock); // Wait for the positive edge of the clock
68 data = data + 16'h0001; // Increment data
69 $display("Cycle %0d: Writing data = %h", $time / 10, data);
70 end
71 data_start = 0; // Disable data_start
72
73 #20;
74 $display("Data buffering complete.");
75 $finish; // End the simulation
76 end
77
78
79
80 // module stimulus_forever_loo­
p_clock_gen;
81 wire clock; // Clock signal output from the module
82
83 // Instantiate the forever loop clock generation module
84 forever_loop_clock_g­
en flcg (
85 .clock(clock)
86 );
87
88 // Monitor clock transitions
89 initial begin
90 $monitor("Time: %0d, Clock = %b", $time, clock);
91 #100; // Run the simulation for 100 time units
92 $finish; // End the simulation
93 end
94
95 // module stimulus_forever_loo­
p_sync;
96 reg clock; // Clock signal
97 reg y; // Input register to synchronize
98 wire x; // Output register synchronized to y
99
100 // Instantiate the forever loop synchronization module
101 forever_loop_sync fls (
102 .clk(clock),
103 .outx(x),
104 .inpy(y)
105 );

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loops_tb.v

106
107 // Generate the clock signal
108 initial begin
109 clock = 0;
110 forever #10 clock = ~clock; // Toggle clock every 10 time units
111 end
112
113 // Stimulus
114 initial begin
115 y = 0; // Initialize y
116 #15;
117
118 $display("Starting synchronization test...");
119 $monitor("Time: %0d, Clock = %b, x = %b, y = %b", $time, clock, x, y);
120
121 #20 y = 1; // Change y after 20 time units
122 #40 y = 0; // Change y again
123 #20 y = 1;
124
125 #50;
126 $display("Synchronization test complete.");
127 $finish; // End the simulation
128 end
129
130
131
132
133 initial begin
134 #100 $dumpfile("loops.vcd");
135 $dumpvars(0,loops_tb);
136
137 end
138
139 endmodule
140
141

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E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\4. Behavioral Level Modeling\7.
Examples\4. FSM\1. Mealy Sequence Detector\Mealy_Sequence_Detector_examples_tb.v

1 `timescale 1ns/1ns
2 `include "Mealy_Sequence_Detec­
tor_examples.v"
3
4 module Mealy_Sequence_Detec­
tor_examples_tb;
5
6
7 // module tb_mealy_101_non_ove­
rlapping;
8 reg x, clk, reset;
9 wire detected;
10
11 // Instantiate the module
12 mealy_101_non_overla­
pping uut (
13 .detected(detected),
14 .x(x),
15 .clk(clk),
16 .reset(reset)
17 );
18
19 // Clock generation
20 always begin
21 #5 clk = ~clk; // 10 time unit clock period
22 end
23
24 // Stimulus
25 initial begin
26 // Initialize signals
27 clk = 0;
28 reset = 0;
29 x = 0;
30
31 // Apply reset
32 #10 reset = 1;
33 #10 reset = 0;
34
35 // Apply test sequence
36 #10 x = 1; // S0 -> S1
37 #10 x = 0; // S1 -> S2
38 #10 x = 1; // S2 -> S1 (detected)
39 #10 x = 1; // S1 -> S1
40 #10 x = 0; // S1 -> S2
41 #10 x = 1; // S2 -> S1 (detected)
42
43 // Monitor outputs
44 #10 $display("Detected = %b", detected);
45
46 // End simulation
47 $finish;
48 end
49
50 // module tb_mealy_011_non_ove­
rlapping;
51 reg x, clk, reset;

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52 wire detected;
53
54 // Instantiate the module
55 mealy_011_non_overla­
pping uut (
56 .detected(detected),
57 .x(x),
58 .clk(clk),
59 .reset(reset)
60 );
61
62 // Clock generation
63 always begin
64 #5 clk = ~clk; // 10 time unit clock period
65 end
66
67 // Stimulus
68 initial begin
69 // Initialize signals
70 clk = 0;
71 reset = 0;
72 x = 0;
73
74 // Apply reset
75 #10 reset = 1;
76 #10 reset = 0;
77
78 // Apply test sequence
79 #10 x = 0; // S0 -> S1
80 #10 x = 1; // S1 -> S2
81 #10 x = 1; // S2 -> S0 (detected)
82 #10 x = 0; // S0 -> S1
83 #10 x = 1; // S1 -> S2
84 #10 x = 1; // S2 -> S0 (detected)
85
86 // Monitor outputs
87 #10 $display("Detected = %b", detected);
88
89 // End simulation
90 $finish;
91 end
92
93 // module tb_mealy_000_non_ove­
rlapping;
94 reg x, clk, reset;
95 wire detected;
96
97 // Instantiate the module
98 mealy_000_non_overla­
pping uut (
99 .detected(detected),
100 .x(x),
101 .clk(clk),
102 .reset(reset)
103 );
104
105 // Clock generation

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106 always begin
107 #5 clk = ~clk; // 10 time unit clock period
108 end
109
110 // Stimulus
111 initial begin
112 // Initialize signals
113 clk = 0;
114 reset = 0;
115 x = 0;
116
117 // Apply reset
118 #10 reset = 1;
119 #10 reset = 0;
120
121 // Apply test sequence
122 #10 x = 0; // S0 -> S1
123 #10 x = 0; // S1 -> S2 (detected)
124 #10 x = 0; // S2 -> S1
125 #10 x = 0; // S1 -> S2 (detected)
126
127 // Monitor outputs
128 #10 $display("Detected = %b", detected);
129
130 // End simulation
131 $finish;
132 end
133
134 // module tb_mealy_0101_non_ov­
erlapping;
135 reg x, clk, reset;
136 wire detected;
137
138 // Instantiate the module
139 mealy_0101_non_overl­
apping uut (
140 .detected(detected),
141 .x(x),
142 .clk(clk),
143 .reset(reset)
144 );
145
146 // Clock generation
147 always begin
148 #5 clk = ~clk; // 10 time unit clock period
149 end
150
151 // Stimulus
152 initial begin
153 // Initialize signals
154 clk = 0;
155 reset = 0;
156 x = 0;
157
158 // Apply reset
159 #10 reset = 1;

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160 #10 reset = 0;
161
162 // Apply test sequence
163 #10 x = 0; // S0 -> S1
164 #10 x = 1; // S1 -> S2
165 #10 x = 0; // S2 -> S3
166 #10 x = 1; // S3 -> S2 (detected)
167 #10 x = 0; // S2 -> S3
168 #10 x = 1; // S3 -> S2 (detected)
169
170 // Monitor outputs
171 #10 $display("Detected = %b", detected);
172
173 // End simulation
174 $finish;
175 end
176
177
178 // module tb_mealy_11011_non_o­
verlapping;
179 reg x, clk, reset;
180 wire detected;
181
182 // Instantiate the module
183 mealy_11011_non_over­
lapping uut (
184 .detected(detected),
185 .x(x),
186 .clk(clk),
187 .reset(reset)
188 );
189
190 // Clock generation
191 always begin
192 #5 clk = ~clk; // 10 time unit clock period
193 end
194
195 // Stimulus
196 initial begin
197 // Initialize signals
198 clk = 0;
199 reset = 0;
200 x = 0;
201
202 // Apply reset
203 #10 reset = 1;
204 #10 reset = 0;
205
206 // Apply test sequence
207 #10 x = 1; // S0 -> S1
208 #10 x = 1; // S1 -> S2
209 #10 x = 0; // S2 -> S3
210 #10 x = 1; // S3 -> S4
211 #10 x = 1; // S4 -> S2 (detected)
212 #10 x = 1; // S2 -> S1 (detected)
213

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214 // Monitor outputs
215 #10 $display("Detected = %b", detected);
216
217 // End simulation
218 $finish;
219 end
220
221 // module tb_mealy_101_overlap­
ping;
222 reg x, clk, reset;
223 wire detected;
224
225 // Instantiate the module
226 mealy_101_overlappin­
g uut (
227 .detected(detected),
228 .x(x),
229 .clk(clk),
230 .reset(reset)
231 );
232
233 // Clock generation
234 always begin
235 #5 clk = ~clk; // 10 time unit clock period
236 end
237
238 // Stimulus
239 initial begin
240 // Initialize signals
241 clk = 0;
242 reset = 0;
243 x = 0;
244
245 // Apply reset
246 #10 reset = 1;
247 #10 reset = 0;
248
249 // Apply test sequence
250 #10 x = 1; // S0 -> S1
251 #10 x = 0; // S1 -> S2
252 #10 x = 1; // S2 -> S1 (detected)
253 #10 x = 1; // S1 -> S1
254 #10 x = 0; // S1 -> S2 (detected)
255
256 // Monitor outputs
257 #10 $display("Detected = %b", detected);
258
259 // End simulation
260 $finish;
261 end
262
263 // module tb_mealy_011_overlap­
ping;
264 reg x, clk, reset;
265 wire detected;
266
267 // Instantiate the module

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268 mealy_011_overlappin­
g uut (
269 .detected(detected),
270 .x(x),
271 .clk(clk),
272 .reset(reset)
273 );
274
275 // Clock generation
276 always begin
277 #5 clk = ~clk; // 10 time unit clock period
278 end
279
280 // Stimulus
281 initial begin
282 // Initialize signals
283 clk = 0;
284 reset = 0;
285 x = 0;
286
287 // Apply reset
288 #10 reset = 1;
289 #10 reset = 0;
290
291 // Apply test sequence
292 #10 x = 0; // S0 -> S1
293 #10 x = 1; // S1 -> S2
294 #10 x = 1; // S2 -> S1 (detected)
295 #10 x = 0; // S1 -> S0
296 #10 x = 1; // S0 -> S1
297
298 // Monitor outputs
299 #10 $display("Detected = %b", detected);
300
301 // End simulation
302 $finish;
303 end
304
305
306 // module tb_mealy_000_overlap­
ping;
307 reg x, clk, reset;
308 wire detected;
309
310 // Instantiate the module
311 mealy_000_overlappin­
g uut (
312 .detected(detected),
313 .x(x),
314 .clk(clk),
315 .reset(reset)
316 );
317
318 // Clock generation
319 always begin
320 #5 clk = ~clk; // 10 time unit clock period
321 end

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322
323 // Stimulus
324 initial begin
325 // Initialize signals
326 clk = 0;
327 reset = 0;
328 x = 0;
329
330 // Apply reset
331 #10 reset = 1;
332 #10 reset = 0;
333
334 // Apply test sequence
335 #10 x = 0; // S0 -> S1
336 #10 x = 0; // S1 -> S2
337 #10 x = 0; // S2 -> S1 (detected)
338 #10 x = 0; // S1 -> S2 (detected)
339
340 // Monitor outputs
341 #10 $display("Detected = %b", detected);
342
343 // End simulation
344 $finish;
345 end
346
347 // module tb_mealy_0101_overla­
pping;
348 reg x, clk, reset;
349 wire detected;
350
351 // Instantiate the module
352 mealy_0101_overlappi­
ng uut (
353 .detected(detected),
354 .x(x),
355 .clk(clk),
356 .reset(reset)
357 );
358
359 // Clock generation
360 always begin
361 #5 clk = ~clk; // 10 time unit clock period
362 end
363
364 // Stimulus
365 initial begin
366 // Initialize signals
367 clk = 0;
368 reset = 0;
369 x = 0;
370
371 // Apply reset
372 #10 reset = 1;
373 #10 reset = 0;
374
375 // Apply test sequence

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376 #10 x = 0; // S0 -> S1
377 #10 x = 1; // S1 -> S2
378 #10 x = 0; // S2 -> S3
379 #10 x = 1; // S3 -> S2 (detected)
380 #10 x = 0; // S2 -> S3
381
382 // Monitor outputs
383 #10 $display("Detected = %b", detected);
384
385 // End simulation
386 $finish;
387 end
388
389 // module tb_mealy_11011_overl­
apping;
390 reg x, clk, reset;
391 wire detected;
392
393 // Instantiate the module
394 mealy_11011_overlapp­
ing uut (
395 .detected(detected),
396 .x(x),
397 .clk(clk),
398 .reset(reset)
399 );
400
401 // Clock generation
402 always begin
403 #5 clk = ~clk; // 10 time unit clock period
404 end
405
406 // Stimulus
407 initial begin
408 // Initialize signals
409 clk = 0;
410 reset = 0;
411 x = 0;
412
413 // Apply reset
414 #10 reset = 1;
415 #10 reset = 0;
416
417 // Apply test sequence
418 #10 x = 1; // S0 -> S1
419 #10 x = 1; // S1 -> S2
420 #10 x = 0; // S2 -> S3
421 #10 x = 1; // S3 -> S4
422 #10 x = 1; // S4 -> S2 (detected)
423
424 // Monitor outputs
425 #10 $display("Detected = %b", detected);
426
427 // End simulation
428 $finish;
429 end

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430
431
432
433 initial begin
434 tor_examples.vcd");
$dumpfile("Mealy_Sequence_Detec­
435 $dumpvars(0,Mealy_Sequence_Detec­
tor_examples_tb);
436
437 end
438
439 endmodule
440
441

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Memories_examples_tb.v

E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\4. Behavioral Level Modeling\7.

Examples\3. Memories\Memories_examples_tb.v

6 // module tb_FIFO;
7 reg clk, rst, wr_en, rd_en;
8 reg [7:0] buf_in;
9 wire [7:0] buf_out;
10 wire buf_empty, buf_full;
11 wire [7:0] fifo_counter;
12
13 // Instantiate the FIFO module
14 FIFO uut (.clk(clk), .rst(rst), .buf_in(buf_in), .buf_out(buf_out), .wr_en(wr_en),
.rd_en(rd_en), .buf_empty(buf_empty), .buf_full(buf_full), .fifo_counter(fifo_counter));
15
16 // Clock generation
17 always begin
18 #5 clk = ~clk; // Generate clock with 10 time units period
19 end
20
21 // Stimulus
22 initial begin
23 // Initialize signals
24 clk = 0;
25 rst = 0;
26 wr_en = 0;
27 rd_en = 0;
28 buf_in = 8'd0;
29
30 // Apply reset
31 rst = 1;
32 #10;
33 rst = 0;
34
35 // Write to FIFO
36 wr_en = 1;
37 buf_in = 8'd25;
38 #10;
39 wr_en = 0;
40
41 // Read from FIFO
42 rd_en = 1;
43 #10;
44 rd_en = 0;
45
46 // End simulation
47 $finish;
48 end
49
50
51 // module tb_FIFO;
52 reg clk_r, clk_w, rst, wr_en, rd_en;
53 reg [7:0] buf_in;
54 wire [7:0] buf_out;
55 wire buf_empty, buf_full;

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Memories_examples_tb.v

56 wire [3:0] fifo_counter;

57
58 // Instantiate the FIFO Dual Clock module
59 FIFO uut (
60 .clk_r(clk_r), .clk_w(clk_w), .rst(rst), .buf_in(buf_in),
61 .buf_out(buf_out), .wr_en(wr_en), .rd_en(rd_en),
62 .buf_empty(buf_empty), .buf_full(buf_full), .fifo_counter(fifo_counter)
63 );
64
65 // Clock generation for read and write clocks
66 always begin
67 #5 clk_w = ~clk_w; // Write clock (10 time units period)
68 end
69
70 always begin
71 #7 clk_r = ~clk_r; // Read clock (14 time units period)
72 end
73
74 // Stimulus for testing FIFO functionality
75 initial begin
76 // Initialize signals
77 clk_w = 0;
78 clk_r = 0;
79 rst = 0;
80 wr_en = 0;
81 rd_en = 0;
82 buf_in = 8'd0;
83
84 // Apply reset
85 rst = 1;
86 #10;
87 rst = 0;
88
89 // Write data into FIFO
90 wr_en = 1;
91 buf_in = 8'd25;
92 #10;
93 wr_en = 0;
94
95 // Read data from FIFO
96 rd_en = 1;
97 #10;
98 rd_en = 0;
99
100 // Test FIFO overflow and underflow
101 wr_en = 1;
102 buf_in = 8'd50;
103 #10;
104 wr_en = 0;
105
106 // End simulation
107 $finish;
108 end

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E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\4. Behavioral Level Modeling\7.
Examples\4. FSM\2. Moore Sequence Detector\Moore_Sequence_Detector_examples_tb.v

1 `timescale 1ns/1ns
2 `include "Moore_Sequence_Detec­
tor_examples.v"
3
4 module Moore_Sequence_Detec­
tor_examples_tb;
5
6
7 // module tb_moore_101_non_ove­
rlapping;
8 reg x, clk, reset;
9 wire detected;
10
11 // Instantiate the Moore Sequence Detector
12 moore_101_non_overla­
pping uut (
13 .detected(detected),
14 .x(x),
15 .clk(clk),
16 .reset(reset)
17 );
18
19 // Clock generation
20 always begin
21 #5 clk = ~clk; // Clock period = 10 units
22 end
23
24 // Stimulus
25 initial begin
26 // Initialize signals
27 clk = 0;
28 reset = 0;
29 x = 0;
30
31 // Apply reset
32 #10 reset = 1;
33 #10 reset = 0;
34
35 // Apply test sequence
36 #10 x = 1; // S0 -> S1
37 #10 x = 0; // S1 -> S2
38 #10 x = 1; // S2 -> S0 (detected)
39
40 // Monitor output
41 #10 $monitor("Time = %0t | x = %b | Detected = %b", $time, x, detected);
42
43 // End simulation
44 #30 $finish;
45 end
46
47
48 // module tb_moore_010_non_ove­
rlapping;
49 reg x, clk, reset;
50 wire detected;
51

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52 // Instantiate the Moore Sequence Detector
53 moore_010_non_overla­
pping uut (
54 .detected(detected),
55 .x(x),
56 .clk(clk),
57 .reset(reset)
58 );
59
60 // Clock generation
61 always begin
62 #5 clk = ~clk; // Clock period = 10 units
63 end
64
65 // Stimulus
66 initial begin
67 // Initialize signals
68 clk = 0;
69 reset = 0;
70 x = 0;
71
72 // Apply reset
73 #10 reset = 1;
74 #10 reset = 0;
75
76 // Apply test sequence
77 #10 x = 0; // S0 -> S1
78 #10 x = 1; // S1 -> S2
79 #10 x = 0; // S2 -> S0 (detected)
80
81 // Monitor output
82 #10 $monitor("Time = %0t | x = %b | Detected = %b", $time, x, detected);
83
84 // End simulation
85 #30 $finish;
86 end
87
88 // module tb_moore_0101_non_ov­
erlapping;
89 reg x, clk, reset;
90 wire detected;
91
92 // Instantiate the Moore Sequence Detector
93 moore_0101_non_overl­
apping uut (
94 .detected(detected),
95 .x(x),
96 .clk(clk),
97 .reset(reset)
98 );
99
100 // Clock generation
101 always begin
102 #5 clk = ~clk; // Clock period = 10 units
103 end
104
105 // Stimulus

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106 initial begin
107 // Initialize signals
108 clk = 0;
109 reset = 0;
110 x = 0;
111
112 // Apply reset
113 #10 reset = 1;
114 #10 reset = 0;
115
116 // Apply test sequence
117 #10 x = 0; // S0 -> S1
118 #10 x = 1; // S1 -> S2
119 #10 x = 0; // S2 -> S3
120 #10 x = 1; // S3 -> S0 (detected)
121
122 // Monitor output
123 #10 $monitor("Time = %0t | x = %b | Detected = %b", $time, x, detected);
124
125 // End simulation
126 #30 $finish;
127 end
128
129 // module tb_moore_101_overlap­
ping;
130 reg x, clk, reset;
131 wire detected;
132
133 // Instantiate the Moore Sequence Detector
134 moore_101_overlappin­
g uut (
135 .detected(detected),
136 .x(x),
137 .clk(clk),
138 .reset(reset)
139 );
140
141 // Clock generation
142 always begin
143 #5 clk = ~clk; // Clock period = 10 units
144 end
145
146 // Stimulus
147 initial begin
148 // Initialize signals
149 clk = 0;
150 reset = 0;
151 x = 0;
152
153 // Apply reset
154 #10 reset = 1;
155 #10 reset = 0;
156
157 // Apply test sequence
158 #10 x = 1; // S0 -> S1
159 #10 x = 0; // S1 -> S2

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160 #10 x = 1; // S2 -> S1 (detected)
161
162 // Monitor output
163 #10 $monitor("Time = %0t | x = %b | Detected = %b", $time, x, detected);
164
165 // End simulation
166 #30 $finish;
167 end
168
169 // module tb_moore_010_overlap­
ping;
170 reg x, clk, reset;
171 wire detected;
172
173 // Instantiate the Moore Sequence Detector
174 moore_010_overlappin­
g uut (
175 .detected(detected),
176 .x(x),
177 .clk(clk),
178 .reset(reset)
179 );
180
181 // Clock generation
182 always begin
183 #5 clk = ~clk; // Clock period = 10 units
184 end
185
186 // Stimulus
187 initial begin
188 // Initialize signals
189 clk = 0;
190 reset = 0;
191 x = 0;
192
193 // Apply reset
194 #10 reset = 1;
195 #10 reset = 0;
196
197 // Apply test sequence
198 #10 x = 0; // S0 -> S1
199 #10 x = 1; // S1 -> S2
200 #10 x = 0; // S2 -> S0 (detected)
201
202 // Monitor output
203 #10 $monitor("Time = %0t | x = %b | Detected = %b", $time, x, detected);
204
205 // End simulation
206 #30 $finish;
207 end
208
209 // module tb_moore_0101_overla­
pping;
210 reg x, clk, reset;
211 wire detected;
212
213 // Instantiate the Moore Sequence Detector

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214 moore_0101_overlappi­
ng uut (
215 .detected(detected),
216 .x(x),
217 .clk(clk),
218 .reset(reset)
219 );
220
221 // Clock generation
222 always begin
223 #5 clk = ~clk; // Clock period = 10 units
224 end
225
226 // Stimulus
227 initial begin
228 // Initialize signals
229 clk = 0;
230 reset = 0;
231 x = 0;
232
233 // Apply reset
234 #10 reset = 1;
235 #10 reset = 0;
236
237 // Apply test sequence
238 #10 x = 0; // S0 -> S1
239 #10 x = 1; // S1 -> S2
240 #10 x = 0; // S2 -> S3
241 #10 x = 1; // S3 -> S2 (detected)
242
243 // Monitor output
244 #10 $monitor("Time = %0t | x = %b | Detected = %b", $time, x, detected);
245
246 // End simulation
247 #30 $finish;
248 end
249
250
251
252
253
254
255 initial begin
256 $dumpfile("Moore_Sequence_Detec­
tor_examples.vcd");
257 $dumpvars(0,Moore_Sequence_Detec­tor_examples_tb);
258
259 end
260
261 endmodule
262
263

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operators_tb.v ; YT @AnishSaha_

E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\3. Dataflow Level Modeling\2. Different Types of Operators\operators_tb.v

1 `timescale 1ns/1ns
2 `include "operators.v"
3
4
5
6 module operators_tb;
7
8 // Testbench for arithmetic_operation­
s
9 // module test_arithmetic_oper­
ations, directly run it.
10
11
12 // module tb_unary_ops, directly run it.
13
14
15 // module tb_logical_ops, directly run it.
16
17
18 // tb_relational_ops
19
20 reg [3:0] A, B, X, Y;
21 wire A_leq_B, A_gt_B, Y_geq_X, Y_lt_X;
22
23 relational_ops uut (
24 .A(A),
25 .B(B),
26 .X(X),
27 .Y(Y),
28 .A_leq_B(A_leq_B),
29 .A_gt_B(A_gt_B),
30 .Y_geq_X(Y_geq_X),
31 .Y_lt_X(Y_lt_X)
32 );
33
34 initial begin

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35 $monitor("Time=%0t | A = %0d , B = %0d, X = %b, Y = %b | A <= B = %b, A > B = %b, Y >= X = %b, Y < X =%b",
36 $time, A, B, X, Y, A_leq_B, A_gt_B, Y_geq_X, Y_lt_X);
37
38 // Test Cases
39 A = 4; B = 3; X = 4'b1010; Y = 4'b1101; #10; // Initial case
40 A = 2; B = 5; X = 4'b1110; Y = 4'b1001; #10; // Another case
41 A = 6; B = 6; X = 4'b0001; Y = 4'b0100; #10; // Edge case
42 A = 4'b1x01; B = 4'b1010; X = 4'b0z01; Y = 4'b0100; #10; // Edge case
43 end
44
45
46 // module tb_case_eq
47 reg [3:0] A, B;
48 wire logic_eq, case_eq,nlogic_eq, ncase_eq;
49
50 case_eq uut(.A(A), .B(B), .logic_eq(logic_eq), .case_eq(case_eq), .nlogic_eq(nlogic_eq), .ncase_eq(ncase_eq));
51
52 initial begin
53 $monitor("Time=%0t A=%b B=%b | Logical EQ=%b Case EQ=%b | Logical NEQ=%b Case NEQ=%b", $time, A, B, logic_eq, case_eq,nlogic_eq,
ncase_eq);
54 A = 4'b1010; B = 4'b1010; #10;
55 A = 4'b1x10; B = 4'b1010; #10;
56 A = 4'b1x10; B = 4'b1x10; #10;
57 end
58
59
60 // module tb_bitwise_ops
61 reg [3:0] X, Y;
62 wire [3:0] notX, andXY, orXY, xorXY,xnorXY;
63
64 bitwise_ops uut(.X(X), .Y(Y), .notX(notX), .andXY(andXY), .orXY(orXY), .xorXY(xorXY), .xnorXY(xnorXY));
65
66 initial begin
67 $monitor("Time=%t X=%b Y=%b | ~X= %b X & Y= %b X|Y=%b X ^ Y= %b, X ^~ Y=%b", $time, X, Y, notX, andXY, orXY, xorXY,xnorXY);
68 X = 4'b1010; Y = 4'b1100; #10;
69 X = 4'b0101; Y = 4'b0011; #10;
70 end

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71
72 // module tb_reduction_ops
73 reg [3:0] X; // Input vector
74 wire and_result, or_result, xor_result;
75
76 // Instantiate the module
77 reduction_ops uut (
78 .X(X),
79 .and_result(and_result),
80 .or_result(or_result),
81 .xor_result(xor_result)
82 );
83
84 initial begin
85 $monitor("Time=%0t | X=%b | Reduction AND=%b | Reduction OR=%b | Reduction XOR=%b",
86 $time, X, and_result, or_result, xor_result);
87
88 // Test Cases
89 X = 4'b1010; #10; // Case 1: Even parity
90 X = 4'b1111; #10; // Case 2: All bits set
91 X = 4'b0000; #10; // Case 3: All bits clear
92 X = 4'b1001; #10; // Case 4: Odd parity
93 X = 4'b0101; #10; // Case 5: Alternating bits
94 end
95
96 // module tb_shifting_ops
97 reg [3:0] X; // Input 4-bit vector
98 wire [3:0] y_logical_right, y_logical_left_1, y_logical_left_2;
99
100 // Instantiate the shifting_ops module
101 shifting_ops uut (
102 .X(X),
103 .y_logical_right(y_logical_right),
104 .y_logical_left_1(y_logical_left_1),
105 .y_logical_left_2(y_logical_left_2)
106 );
107

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108 initial begin

109 $monitor("Time=%0t |X in binary X=%b | X in decimal X=%0d | Y (Logical Right Shift 1) in binary =%b | in decimal = %0d | Y
(Logical Left Shift 1)=%b | Y (Logical Left Shift 2)=%b",
110 $time, X,X, y_logical_right,y_logical_right, y_logical_left_1, y_logical_left_2);
111
112 // Test Cases
113 X = 4'b1100; #10; // Test Case 1
114 X = 4'b0110; #10; // Test Case 2
115 X = 4'b1001; #10; // Test Case 3
116 X = 4'b0000; #10; // Test Case 4
117 X = -2; #10; // Test Case 5
118
119 end
120
121
122 // module tb_arithmetic_shift, directly run it.
123
124
125
126
127
128 // module tb_tristate_buffer
129 reg drive_enable;
130 reg [35:0] addr_out;
131 wire [35:0] addr_bus;
132
133 tristate_buffer uut (
134 .drive_enable(drive_enable),
135 .addr_out(addr_out),
136 .addr_bus(addr_bus)
137 );
138
139 initial begin
140 $monitor("Time=%t | drive_enable=%b addr_out=%h addr_bus=%h", $time, drive_enable, addr_out, addr_bus);
141
142 // Test Cases
143 addr_out = 36'h123456789; drive_enable = 1; #10; // Drive enable ON

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144 addr_out = 36'hABCDEFFF0; drive_enable = 0; #10; // Drive enable OFF (High-Z)

145 end
146
147
148
149 initial begin
150 $dumpfile("operators.vcd");
151 $dumpvars(0,operators_tb);
152
153
154
155
156
157 end
158
159 endmodule
160
161

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ripple_carry_counter_tb.v

E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\1. Basics of Verilog\6. ripple_carry_counter\ripple_carry_counter_tb.v

1 `timescale 1ns/1ns
2 `include "ripple_carry_counter­
.v"
3
4 module ripple_carry_counter­
_tb;
5 reg clk;
6 reg reset;
7 wire[3:0] q;
8 // instantiate the design block
9 ripple_carry_counter­mut(q, clk, reset);
10 // Control the clk signal that drives the design block. Cycle time = 10
11 initial
12 clk = 1'b0; //set clk to 0
13 always
14 #5 clk = ~clk; //toggle clk every 5 time units
15 initial begin
16 $dumpfile("ripple_carry_counter­
_tb.vcd");
17 $dumpvars(0,ripple_carry_counter­_tb);
18 // Control the reset signal that drives the design block
19 // reset is asserted from 0 to 20 and from 200 to 220.
20 reset = 1'b1;
21 #15 reset = 1'b0;
22 #180 reset = 1'b1;
23 #10 reset = 1'b0;
24 $display("Test Complete");
25 #20 $finish; //terminate the simulation
26 end
27 initial
28 $monitor("At time : %0t", $time, " Output q = %0d, clk - %0d, Reset : %0d", q,clk,reset);
29 endmodule
30

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Sequential_circuits_examples_tb.v

E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\4. Behavioral Level Modeling\7.

Examples\2. Sequential\Sequential_circuits_examples_tb.v

1 `timescale 1ns/1ns
2 `include "Sequential_circuits_­
examples.v"
3
4 module Sequential_circuits_­
examples_tb;
5
6
7
8 // // module tb_dlatch_df;
9
10 // Inputs
11 reg d, en;
12
13 // Outputs
14 wire q;
15
16 // Instantiate the Unit Under Test (UUT)
17 dlatch_df uut (
18 .q(q),
19 .d(d),
20 .en(en)
21 );
22
23 initial begin
24 // Monitor signals
25 $monitor("Time=%0t | d=%b | en=%b | q=%b", $time, d, en, q);
26
27 // Test sequences
28 d = 0; en = 0; #10; // Test when enable is off (q should not change)
29 d = 1; en = 0; #10; // Test when enable is off (q should still hold previous value)
30 d = 1; en = 1; #10; // Test when enable is on (q should follow d)
31 d = 0; en = 1; #10; // Test when enable is on (q should follow d)
32
33 $finish;
34 end
35
36 // module tb_dlatch_bh;
37
38 // Inputs
39 reg d, en;
40
41 // Outputs
42 wire q;
43
44 // Instantiate the Unit Under Test (UUT)
45 dlatch_bh uut (
46 .q(q),
47 .d(d),
48 .en(en)
49 );
50
51 initial begin

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Sequential_circuits_examples_tb.v

52 // Monitor signals
53 $monitor("Time=%0t | d=%b | en=%b | q=%b", $time, d, en, q);
54
55 // Test sequences
56 d = 0; en = 0; #10; // Test when enable is off (q should not change)
57 d = 1; en = 0; #10; // Test when enable is off (q should still hold previous value)
58 d = 1; en = 1; #10; // Test when enable is on (q should follow d)
59 d = 0; en = 1; #10; // Test when enable is on (q should follow d)
60
61 $finish;
62 end
63
64
65 // module tb_dlatch_bh_reset;
66
67 // Inputs
68 reg d, en, rst;
69
70 // Outputs
71 wire q;
72
73 // Instantiate the Unit Under Test (UUT)
74 dlatch_bh uut (
75 .q(q),
76 .d(d),
77 .en(en),
78 .rst(rst)
79 );
80
81 initial begin
82 // Monitor signals
83 $monitor("Time=%0t | d=%b | en=%b | rst=%b | q=%b", $time, d, en, rst, q);
84
85 // Test sequences
86 rst = 1; d = 0; en = 0; #10; // Test reset (q should be 0)
87 rst = 0; d = 1; en = 1; #10; // Test with enable on (q should follow d)
88 d = 0; en = 1; #10; // Test with enable on (q should follow d)
89 rst = 1; #10; // Test reset again (q should be 0)
90
91 $finish;
92 end
93
94 // module tb_dffb;
95
96 // Inputs
97 reg d, clk;
98
99 // Outputs
100 wire q;
101
102 // Instantiate the Unit Under Test (UUT)
103 dffb uut (
104 .q(q),
105 .d(d),

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Sequential_circuits_examples_tb.v

106 .clk(clk)
107 );
108
109 // Clock generation
110 initial begin
111 clk = 0;
112 forever #5 clk = ~clk; // Toggle clock every 5 time units
113 end
114
115 initial begin
116 // Monitor signals
117 $monitor("Time=%0t | d=%b | clk=%b | q=%b", $time, d, clk, q);
118
119 // Test sequences
120 d = 0; #10; // d = 0, q should follow on clk rising edge
121 d = 1; #10; // d = 1, q should follow on clk rising edge
122 d = 0; #10; // d = 0, q should follow on clk rising edge
123
124 $finish;
125 end
126
127 // module tb_dff_Pe_Ar;
128
129 // Inputs
130 reg d, clk, rst;
131
132 // Outputs
133 wire q;
134
135 // Instantiate the Unit Under Test (UUT)
136 dff_Pe_Ar uut (
137 .q(q),
138 .d(d),
139 .clk(clk),
140 .rst(rst)
141 );
142
143 // Clock generation
144 initial begin
145 clk = 0;
146 forever #5 clk = ~clk; // Toggle clock every 5 time units
147 end
148
149 initial begin
150 // Monitor signals
151 $monitor("Time=%0t | d=%b | clk=%b | rst=%b | q=%b", $time, d, clk, rst, q);
152
153 // Test sequences
154 rst = 1; d = 0; #10; // Test reset (q should be 0)
155 rst = 0; d = 1; #10; // Test with reset off (q should follow d)
156 rst = 1; #10; // Test reset again (q should be 0)
157 rst = 0; d = 0; #10; // Test with reset off (q should follow d)
158
159 $finish;

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160 end
161
162
163 // module tb_dff_Ne_Ar;
164
165 // Inputs
166 reg d, clk, rst;
167
168 // Outputs
169 wire q;
170
171 // Instantiate the Unit Under Test (UUT)
172 dff_Ne_Ar uut (
173 .q(q),
174 .d(d),
175 .clk(clk),
176 .rst(rst)
177 );
178
179 // Clock generation
180 initial begin
181 clk = 0;
182 forever #5 clk = ~clk; // Toggle clock every 5 time units
183 end
184
185 initial begin
186 // Monitor signals
187 $monitor("Time=%0t | d=%b | clk=%b | rst=%b | q=%b", $time, d, clk, rst, q);
188
189 // Test sequences
190 rst = 1; d = 0; #10; // Test reset (q should be 0)
191 rst = 0; d = 1; #10; // Test with reset off (q should follow d on neg edge)
192 rst = 1; #10; // Test reset again (q should be 0)
193 rst = 0; d = 0; #10; // Test with reset off (q should follow d on neg edge)
194
195 $finish;
196 end
197
198
199 // module tb_dff_Pe_ALr;
200
201 // Inputs
202 reg d, clk, rst;
203
204 // Outputs
205 wire q;
206
207 // Instantiate the Unit Under Test (UUT)
208 dff_Pe_ALr uut (
209 .q(q),
210 .d(d),
211 .clk(clk),
212 .rst(rst)
213 );

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Sequential_circuits_examples_tb.v

214
215 // Clock generation
216 initial begin
217 clk = 0;
218 forever #5 clk = ~clk; // Toggle clock every 5 time units
219 end
220
221 initial begin
222 // Monitor signals
223 $monitor("Time=%0t | d=%b | clk=%b | rst=%b | q=%b", $time, d, clk, rst, q);
224
225 // Test sequences
226 rst = 0; d = 0; #10; // Test reset (q should be 0)
227 rst = 1; d = 1; #10; // Test with reset off (q should follow d)
228 rst = 0; #10; // Test reset again (q should be 0)
229 rst = 1; d = 0; #10; // Test with reset off (q should follow d)
230
231 $finish;
232 end
233
234 // module tb_dff_Pe_Alr_Ahs;
235
236 // Inputs
237 reg d, clk, rst, set;
238
239 // Outputs
240 wire q;
241
242 // Instantiate the Unit Under Test (UUT)
243 dff_Pe_Alr_Ahs uut (
244 .q(q),
245 .d(d),
246 .clk(clk),
247 .rst(rst),
248 .set(set)
249 );
250
251 // Clock generation
252 initial begin
253 clk = 0;
254 forever #5 clk = ~clk; // Toggle clock every 5 time units
255 end
256
257 initial begin
258 // Monitor signals
259 $monitor("Time=%0t | d=%b | clk=%b | rst=%b | set=%b | q=%b", $time, d, clk, rst,
set, q);
260
261 // Test sequences
262 rst = 0; set = 0; d = 0; #10; // Test reset (q should be 0)
263 rst = 1; set = 1; d = 1; #10; // Test set (q should be 1)
264 rst = 0; set = 0; #10; // Test reset (q should be 0)
265 rst = 1; set = 1; d = 0; #10; // Test set (q should be 1)
266

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267 $finish;
268 end
269
270
271 // module tb_dff_Sr;
272
273 // Inputs
274 reg d, clk, rst;
275
276 // Outputs
277 wire q;
278
279 // Instantiate the Unit Under Test (UUT)
280 dff_Sr uut (
281 .q(q),
282 .d(d),
283 .clk(clk),
284 .rst(rst)
285 );
286
287 // Clock generation
288 initial begin
289 clk = 0;
290 forever #5 clk = ~clk; // Toggle clock every 5 time units
291 end
292
293 initial begin
294 // Monitor signals
295 $monitor("Time=%0t | d=%b | clk=%b | rst=%b | q=%b", $time, d, clk, rst, q);
296
297 // Test sequences
298 rst = 1; d = 0; #10; // Test reset (q should be 0)
299 rst = 0; d = 1; #10; // Test with reset off (q should follow d)
300 rst = 1; #10; // Test reset again (q should be 0)
301 rst = 0; d = 0; #10; // Test with reset off (q should follow d)
302
303 $finish;
304 end
305
306 // module tb_dff_Slr;
307
308 // Inputs
309 reg d, clk, rst;
310
311 // Outputs
312 wire q;
313
314 // Instantiate the Unit Under Test (UUT)
315 dff_Slr uut (
316 .q(q),
317 .d(d),
318 .clk(clk),
319 .rst(rst)
320 );

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321
322 // Clock generation
323 initial begin
324 clk = 0;
325 forever #5 clk = ~clk; // Toggle clock every 5 time units
326 end
327
328 initial begin
329 // Monitor signals
330 $monitor("Time=%0t | d=%b | clk=%b | rst=%b | q=%b", $time, d, clk, rst, q);
331
332 // Test sequences
333 rst = 1; d = 0; #10; // Test reset (q should be 0)
334 rst = 0; d = 1; #10; // Test with reset off (q should follow d)
335 rst = 1; #10; // Test reset again (q should be 0)
336 rst = 0; d = 0; #10; // Test with reset off (q should follow d)
337
338 $finish;
339 end
340
341
342 // module tb_dff_Slr_Ahs;
343
344 // Inputs
345 reg d, clk, rst, set;
346
347 // Outputs
348 wire q;
349
350 // Instantiate the Unit Under Test (UUT)
351 dff_Slr_Ahs uut (
352 .q(q),
353 .d(d),
354 .clk(clk),
355 .rst(rst),
356 .set(set)
357 );
358
359 // Clock generation
360 initial begin
361 clk = 0;
362 forever #5 clk = ~clk; // Toggle clock every 5 time units
363 end
364
365 initial begin
366 // Monitor signals
367 $monitor("Time=%0t | d=%b | clk=%b | rst=%b | set=%b | q=%b", $time, d, clk, rst,
set, q);
368
369 // Test sequences
370 rst = 1; set = 0; d = 0; #10; // Test reset (q should be 0)
371 rst = 0; set = 1; d = 1; #10; // Test set (q should be 1)
372 rst = 1; set = 0; #10; // Test reset (q should be 0)
373 rst = 0; set = 1; d = 0; #10; // Test set (q should be 1)

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374
375 $finish;
376 end
377
378
379 // module tb_Reg_set;
380 reg clk, rst;
381 reg [7:0] D1, D2;
382 wire [7:0] Q1, Q2;
383
384 // Instantiate the Reg_set module
385 Reg_set uut (.Q1(Q1), .Q2(Q2), .clk(clk), .rst(rst), .D1(D1), .D2(D2));
386
387 // Clock generation
388 always begin
389 #5 clk = ~clk; // Generate clock with 10 time units period
390 end
391
392 // Stimulus
393 initial begin
394 // Initialize signals
395 clk = 0;
396 rst = 0;
397 D1 = 8'd100;
398 D2 = 8'd200;
399
400 // Apply reset
401 rst = 1;
402 #10;
403 rst = 0;
404
405 // Check after reset
406 #10;
407 $display("Q1 = %d, Q2 = %d", Q1, Q2);
408
409 // Apply data
410 D1 = 8'd50;
411 D2 = 8'd150;
412 #10;
413 $display("Q1 = %d, Q2 = %d", Q1, Q2);
414
415 // Change data
416 D1 = 8'd30;
417 D2 = 8'd130;
418 #10;
419 $display("Q1 = %d, Q2 = %d", Q1, Q2);
420
421 // End simulation
422 $finish;
423 end
424
425 // module tb_SR_LR;
426 reg clk, rst, SI;
427 wire SO;

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428
429 // Instantiate the shift register module
430 SR_LR uut (.SO(SO), .clk(clk), .rst(rst), .SI(SI));
431
432 // Clock generation
433 always begin
434 #5 clk = ~clk; // Generate clock with 10 time units period
435 end
436
437 // Stimulus
438 initial begin
439 // Initialize signals
440 clk = 0;
441 rst = 0;
442 SI = 0;
443
444 // Apply reset
445 rst = 1;
446 #10;
447 rst = 0;
448
449 // Shift values
450 SI = 1;
451 #10;
452 $display("SO = %d", SO);
453
454 SI = 0;
455 #10;
456 $display("SO = %d", SO);
457
458 SI = 1;
459 #10;
460 $display("SO = %d", SO);
461
462 // End simulation
463 $finish;
464 end
465
466 // module tb_USR;
467 reg clk, rst;
468 reg [4:0] PI;
469 reg [1:0] sel;
470 reg SI;
471 wire [4:0] PO;
472 wire SO;
473
474 // Instantiate the Universal Shift Register module
475 USR uut (.PO(PO),.SO(SO) , .PI(PI), .sel(sel), .clk(clk), .rst(rst), .SI(SI));
476
477 // Clock generation
478 always begin
479 #5 clk = ~clk; // Generate clock with 10 time units period
480 end
481

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Sequential_circuits_examples_tb.v

482 // Stimulus
483 initial begin
484 // Initialize signals
485 clk = 0;
486 rst = 0;
487 SI = 0;
488 PI = 5'b11001;
489 sel = 2'b00;
490 $monitor("Time = %0t | rst = %b | SI = %b | PI = %b | sel = %b | PO = %b,SO =
%b",$time,rst,SI,PI,sel,PO,SO);
491
492 // Apply reset
493 rst = 1;
494 #10;
495 rst = 0;
496
497 // Test shifting left (sel = 01)
498 sel = 2'b01;
499 SI = 1;
500 #10;
501 SI = 0;
502 #10
503 SI = 1;
504 #10
505 SI = 0;
506 #80
507
508 // Test shifting right (sel = 10)
509 sel = 2'b10;
510 SI = 1;
511 #80;
512
513
514 // Test loading parallel input (sel = 11)
515 sel = 2'b11;
516 #80;
517
518
519 // End simulation
520 $finish;
521 end
522
523
524
525
526 // module tb_freq_div_by_2;
527 reg clk, rst;
528 wire clk_out;
529
530 // Instantiate the frequency divider module
531 freq_div_by_2 uut (.clk_out(clk_out), .clk(clk), .rst(rst));
532
533 // Clock generation
534 always begin

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535 #5 clk = ~clk; // Generate clock with 10 time units period

536 end
537
538 // Stimulus
539 initial begin
540 // Initialize signals
541 clk = 0;
542 rst = 0;
543
544 // Apply reset
545 rst = 1;
546 #10;
547 rst = 0;
548
549 // Observe the output clock toggling
550 #50;
551 $display("clk_out = %b", clk_out);
552
553 // End simulation
554 $finish;
555 end
556
557 // module tb_freq_div_by_4;
558 reg clk, rst;
559 wire clk_out;
560
561 // Instantiate the module
562 freq_div_by_4 uut (
563 .clk_out(clk_out),
564 .clk(clk),
565 .rst(rst)
566 );
567
568 // Generate clock signal
569 always #5 clk = ~clk; // Clock period = 10 units
570
571 // Test stimulus
572 initial begin
573 // Initialize signals
574 clk = 0;
575 rst = 1;
576 #10 rst = 0;
577
578 // Monitor outputs
579 $monitor("Time = %0t | clk = %b | rst = %b | clk_out = %b",
580 $time, clk, rst, clk_out);
581
582 // Run simulation
583 #100 $finish;
584 end
585
586 // module tb_freq_div_by_3;
587 reg clk, reset;
588 wire clk_out;

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589
590 // Instantiate the module
591 freq_div_by_3 uut (
592 .clk(clk),
593 .reset(reset),
594 .clk_out(clk_out)
595 );
596
597 // Generate clock signal
598 always #5 clk = ~clk; // Clock period = 10 units
599
600 // Test stimulus
601 initial begin
602 // Initialize signals
603 clk = 0;
604 reset = 1;
605 #10 reset = 0;
606
607 // Monitor outputs
608 $monitor("Time = %0t | clk = %b | reset = %b | clk_out = %b",
609 $time, clk, reset, clk_out);
610
611 // Run simulation
612 #100 $finish;
613 end
614
615
616
617
618
619
620 initial begin
621 examples.vcd");
$dumpfile("Sequential_circuits_­
622 $dumpvars(0,Sequential_circuits_­examples_tb);
623
624 end
625
626 endmodule
627
628

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sequential_parallel_blocks_tb.v

E:\Youtube - Anish Saha\PrepFusion\Verilog\Verilog Codes\4. Behavioral Level Modeling\5.

Sequential and Parallel Blocks\sequential_parallel_blocks_tb.v

7 // module stimulus_sequential_­
no_delay;
8 reg x, y, z, w;
9
10 sequential_no_delay uut();
11
12 initial begin
13 #1; // Wait for initial block to complete
14 $monitor("%t: x=%b, y=%b, z=%b, w=%b", $time, uut.x, uut.y, uut.z, uut.w);
15 #10; // Wait to observe the output
16 $finish; // End simulation
17 end
18
19
20
21 // module stimulus_sequential_­
with_delay;
22 reg x, y, z, w;
23
24 sequential_with_dela­
y uut();
25
26 initial begin
27 $monitor("%t: x=%b, y=%b, z=%b, w=%b", $time, uut.x, uut.y, uut.z, uut.w);
28 #50; // Wait to observe all delays
29 $finish; // End simulation
30 end
31
32
33 // module stimulus_parallel_wi­
th_delay;
34 reg x, y, z, w;
35
36 parallel_with_delay uut();
37
38 initial begin
39 $monitor("%t: x=%b, y=%b, z=%b, w=%b", $time, uut.x, uut.y, uut.z, uut.w);
40 #25; // Wait to observe all parallel assignments
41 $finish; // End simulation
42 end
43
44
45 // module stimulus_parallel_ra­
ce_condition;
46 reg x, y; // Single-bit registers
47 reg [1:0] z, w; // Two-bit registers
48
49 initial begin
50 // Monitor signals for race condition
51 $monitor("%t: x=%b, y=%b, z=%b, w=%b", $time, x, y, z, w);
52
53 // Parallel execution of assignments
54 fork
55 x = 1'b0; // Set x to 0
56 y = 1'b1; // Set y to 1
57 z = {x, y}; // Assign z as {x, y}

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sequential_parallel_blocks_tb.v

58 w = {y, x}; // Assign w as {y, x}

59 join
60
61 // Delay for observation
62 #5;
63 $finish;
64 end
65
66 // module stimulus_nested_bloc­
ks;
67 reg x, y, z, w;
68
69 nested_blocks uut();
70
71 initial begin
72 $monitor("%t: x=%b, y=%b, z=%b, w=%b", $time, uut.x, uut.y, uut.z, uut.w);
73 #100; // Wait to observe all outputs
74 $finish; // End simulation
75 end
76
77 // module stimulus_named_block­
s;
78 // Instantiate the named_blocks module
79 named_blocks nb();
80
81 initial begin
82 // Display a message when simulation starts
83 $display("Simulation for Named Blocks Example begins at time %0t", $time);
84
85 // Wait for 10 time units before ending the simulation
86 #10 $display("Simulation ends at time %0t", $time);
87 $finish;
88 end

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