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➢ ASM chart elements
➢ Types of binary information
➢ Digital systems
➢ ASM design steps
➢ Sheet problem 1: n-bit Binary Divider
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▪ ASM more suitable for larger systems design than FSM.
▪ ASM consists of some steps to specify the solution of the problem.
▪ The verbal description is translate into ASM chart to specify the
sequence of operations and conditions of their execution.
➢Solve the sheet by hand!
➢Pay attention to lecture examples and understand them well!
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▪ State box
▪ Decision box
▪ Conditional box
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▪ Block: state box with its
corresponding decision and
conditional boxes
▪ Block specifies the operations
which will be performed during
one clock cycle
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Data info Control info
•Register operation or • Provides command signals to
output signals changes data section
•Controls sequence of operation
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Datapath circuit Control circuit
Performs data processing
Determines sequence of
inside the states and
the operation
conditional boxes
Uses elements as muxes,
Changes from one state to
adders, registers,
another
decoders and counters
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➢The control circuit is sequential circuit whose internal states give
the control commands for the system
➢At any time, the control state starts a defined set of commands →
checks state conditions and external inputs → go to next state to
start another operation
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1. Get the ASM chart from verbal description or pseudo code
2. Specify the data information
3. Draw data path circuit
4. Get ASM chart for control signals
5. Draw control circuit
6. Write VHDL code for circuit from verbal description from step 1
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▪ Given two unsigned n-bit number A and B, design a circuit that produces two n-bit outputs Q
and R, where Q is the quotient A/B and R is the remainder. The procedure is illustrated and the
algorithm is described using pseudo-code. The notation R||A is used to represent a 2n-bit shift
register formed using R as the left-most n bits and A as the right-most n bits.
a) Find the ASM chart for the divider
b) Find the data-path circuit for the divider
c) Find the ASM chart for the divider control circuit
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▪ Reg Q: 1. Q=0 at reset / loaded with zeros
2. Q(0)=‘0’ / Q(0)=‘1’ shift new quotient bit
▪ Reg R: 1. R=0 at reset / loaded with zeros
2. SHL R||A shift left R
3. R=R – B load new remainder
▪ Reg C: 1. C=n – 1 load C with number of bits – 1
2. C=C – 1 count down to bit 0
▪ Reg A: 1. load A
2. SHL R||A shift left A
▪ Reg B: 1. load B
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Entity divider is
Port (clk, reset, s: in STD_LOGIC;
A, B: in STD_LOGIC_VECTOR(7 downto 0);
Q, R: out STD_LOGIC_VECTOR(7 downto 0));
end divider;
Architecture Behavioural of divider is
type state_type is (S0,S1,S2);
signal current_state: state_type;
signal A_reg, B_reg: STD_LOGIC_VECTOR(7 downto 0);
signal R_reg, Q_reg: STD_LOGIC_VECTOR(7 downto 0);
signal C: integer range 0 to 7;
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begin
Process(clk, reset) --State Transition Process
begin
if(reset = '1')then current_state <=S0;
elsif(clk='1' and clk'event)then
case(current_state)is
when S0 =>if(s = “1")then current_state <= S1;
else S<=S0; end if;
when S1 => current_state <= S2;
when S2 =>if(C = “0")then current_state <= S0;
else currnt_state <= S1; end if;
end case; end if; end process;
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Process(clk) --Output Process
begin
if(clk='1' and clk'event)then
case(current_state)is
when S0 => R_reg <= (other =>‘0’);
Q_reg <= (other =‘0’); C<= 7;
if(s = “0")then
A_reg <=A; B_reg <=B; end if;
when S1 => R_reg <=R_reg(6 downto 0)& A_reg(7);
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when S2 => C <= C-1;
if(R_reg>= B_reg)then
Q_reg <= Q_reg(6 downto 0)&’1’;
R_reg <= R_reg - B_reg;
else Q_reg <= Q_reg(6 downto 0)&’0’;
end if;
end case; end if;
end process;
Q<= Q_reg; R<= R_reg;
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end Behavioural; 25
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