Module - 1

Introduction to ASICs: Full custom, Semi -custom and Programmable ASICs, ASIC Design flow, ASIC cell libraries.
CMOS Logic: Data path Logic Cells: Data Path Elements, Adders: Carry skip, Carry bypass, Carry save, Carry select,
Conditional sum, Multiplier (Booth encoding), Data path Operators, I/O cells, Cell Compilers.

Introduction to ASICs:
Discuss the following ASICS.
i) Full custom ASICS
ii) Standard Cell based ASICS

Full custom ASICS:

A Full-Custom ASIC involves designing specific logic cells, circuits, or layout tailored for a particular ASIC. This
means that the designer creates custom logic cells or layout rather than using pretested and precharacterized cells.

In a Full-Custom ASIC:

 Some or all logic cells are customized.

 All mask layers are customized.
 Designers spend significant time optimizing the chip's space and functionality by hand.
 Customizing all features allows for the inclusion of analog circuits, optimized memory cells, or specialized
structures on the ASIC.
 Full-Custom ASICs are the most expensive to manufacture and design.
 The manufacturing lead time for a Full-Custom ASIC is typically around eight weeks.
 Full-Custom ASICs are often intended for specific applications where customization is crucial for
performance and efficiency.

Designing a Full-Custom ASIC requires meticulous attention to detail and expertise to create a highly specialized
integrated circuit tailored to meet the specific requirements of the intended application.

Standard Cell based ASICS

In a Standard Cell-based ASIC (Application-Specific Integrated Circuit), predefined and precharacterized circuits
known as standard cells are used to build the design. These standard cells are constructed using full-custom design
methods but can be integrated into the design without needing full-custom design work by the designer.

Key points about Standard Cell-based ASICs include:

 Standard cells are designed to fit together like bricks in a wall, allowing for efficient and flexible design
implementation.
 Power and ground buses run horizontally inside the standard cells on metal lines, providing necessary
connections for the circuits.
 Each standard cell in the library can be optimized individually during the design process to maximize speed
or minimize area.
 Groups of standard cells can be assembled horizontally to form rows, which can then be stacked vertically
to create flexible rectangular blocks.
 These flexible blocks can be reshaped during design and connected to other standard-cell blocks or full-
custom logic blocks as needed.
 Standard-cell design enables the automation of the ASIC assembly process, reducing design time and risk
while maintaining performance and flexibility advantages.
 Transistor sizes in standard cells can be adjusted to optimize speed, offering additional customization
options.
Overall, Standard Cell-based ASIC design provides a balance between customization and efficiency by leveraging
pre-designed standard cells to streamline the design process and meet specific performance requirements.
With neat sketches, explain the following :
i) Programmable logic devices
ii) Structured gate arrays.

Programmable logic devices:

Programmable Logic Devices (PLDs) are standard integrated circuits available in predefined configurations from a
catalog of parts and are sold in high volume to various customers. While they come in standard configurations,
PLDs can be configured or programmed to create a customized part for a specific application, making them a part
of the ASIC family.

Key features of Programmable Logic Devices (PLDs) include:

 They do not require customized mask layers or logic cells, offering flexibility in design.
 PLDs enable a fast design turnaround, making them efficient for prototyping and quick iterations.
 They consist of a single large block of programmable interconnect, allowing for versatile connectivity
between different components.

PLDs utilize various technologies for programming the device, such as programmable AND logic arrays (AND
plane) followed by programmable OR logic arrays (OR plane). Depending on the programming method, PLDs can
be categorized as erasable PLDs (EPLD) or mask-programmed PLDs.

Overall, Programmable Logic Devices offer a cost-effective and flexible solution for customizing integrated
circuits to meet specific application requirements without the need for full-custom design work.

Structured gate arrays:

Structured gate arrays, also known as embedded gate arrays, combine features of cell-based ICs and traditional
gate arrays. In a structured gate array design, a portion of the IC area is dedicated to specific functions, such as
memory cells or complete circuit blocks like microcontrollers. This customization allows for more efficient and
tailored designs within the gate array structure.

One key advantage of structured gate arrays is the ability to set aside a portion of the IC area for a specific
function. This embedded area can contain different base cells more suitable for building memory cells or even
complete circuit blocks like microcontrollers. By incorporating these custom blocks within the gate array structure,
designers can overcome limitations posed by fixed gate-array base cells and efficiently implement specialized
functions.
Structured gate arrays offer a versatile solution that blends the benefits of both cell-based ICs and gate arrays,
providing opportunities for enhanced customization and optimized performance in integrated circuit design.

Structured gate arrays are a type of gate array design that incorporates custom blocks within the array structure.
There are two main types of structured gate arrays:

1. Channeled Gate Array:

o In a channeled gate array, space is intentionally left between rows of transistors for wiring purposes.
o Only the interconnect, which includes predefined spaces between rows of base cells, is customized
in this design.
o Manufacturing lead time for channeled gate arrays typically ranges from two days to two weeks.
2. Channelless Gate Array:
o In a channelless gate array, there are no predefined areas reserved for routing between cells.
o Routing is done over the top of the gate-array devices, customized through the contact layer that
defines connections between metal layers and transistors.
o The logic density, or the amount of logic that can be implemented in a given silicon area, is usually
higher in channelless gate arrays compared to channeled gate arrays due to the customized contact
mask.

Additionally, a structured gate array, also known as an embedded gate array, combines features of both cell-based
ICs and gate arrays. In this design, a portion of the IC area is dedicated to specific functions such as memory cells
or complete circuit blocks like microcontrollers, allowing for more efficient and tailored designs within the gate
array structure.

What are gate – array – based ASICS? Explain the different types of gate – array –
based ASICs with diagrams

Gate – array – based ASICS

Gate-array-based ASICs, also known as gate array ASICs, are Application-Specific Integrated Circuits where the
transistors are predefined on the silicon wafer. The predefined pattern of transistors on a gate array is called the
base array, and the smallest element that is replicated to create the base array is known as the base cell or primitive
cell. In gate array ASICs, only the top few layers of metal that define the interconnect between transistors are
customized by the designer using custom masks.
In a gate array-based ASIC, designers choose from a library of pre-designed and pre-characterized logic cells,
often referred to as macros. These logic cells have a consistent base-cell layout, and only the interconnect inside
cells and between cells is customized. This customization allows for flexibility in designing the interconnections
while utilizing the predefined transistor layout on the silicon wafer.

There are different types of gate-array-based ASICs, including channeled gate arrays and channelless gate arrays.
These variations offer designers options in terms of interconnect architecture and customization levels within the
gate array structure. Gate-array-based ASICs provide a cost-effective solution by sharing the initial fabrication
costs among different customers and reducing the time needed for manufacturing, making them a popular choice
for certain types of integrated circuit designs.

 Channeled Gate Arrays:

 Channelless Gate Arrays:
 Structured gate arrays.

1. Channeled Gate Arrays:

o Channeled gate arrays are a type of gate array design
where space is intentionally left between rows of
transistors for wiring purposes.
o Channeled gate arrays may use gate isolation or oxide
isolation to isolate transistors from each other.
o The metal interconnect spacing determines the
separation of the transistors in channeled gate arrays.
o In a channeled gate array, space is intentionally left
between rows of transistors for wiring purposes.
o Only the interconnect, which includes predefined
spaces between rows of base cells, is customized in this
design.
o Manufacturing lead time for channeled gate arrays typically ranges from two days to two weeks.

2. Channelless Gate Arrays:

o Channelless gate arrays do not have predefined areas
reserved for routing between cells.
o Routing is done over the top of the gate-array
devices, customized through the contact layer that
defines connections between metal layers and
transistors.
o Channelless gate arrays offer higher logic density
compared to channeled gate arrays due to
customized contact masks and interconnect design.
o The logic density, or the amount of logic that can be
implemented in a given silicon area, is usually
higher in channelless gate arrays compared to
channeled gate arrays due to the customized contact mask.

These two types of gate-array-based ASICs, channeled gate arrays, and channelless gate arrays, provide designers
with options in terms of interconnect architecture and customization levels within the gate array structure, allowing
for flexibility and optimization in integrated circuit design.
 3. Structured gate arrays:
Structure gate array combine features of cell-based ICs CBIC and traditional gate arrays MGA
Only the interconnect is customized
Custom blocks (the same for each design) can be embedded
Manufacturing lead time is between two days and two weeks

Explain FPGA

Field-Programmable Gate Arrays (FPGAs) are programmable ASICs that offer designers the flexibility to program
the chip themselves. Unlike traditional ASICs that are custom-designed and manufactured for a specific
application, FPGAs come with certain connections missing, allowing designers to program these connections
based on their design requirements.

All FPGAs share common elements:

1. Regular array of basic logic cells: These cells can be configured using a specific programming technology
tailored to each FPGA architecture.
2. Special I/O logic cells: Different from basic logic cells, these handle chip inputs and outputs.
3. Programmable interconnect scheme: Forms the wiring between basic logic cells and I/O logic cells.
4. Custom software: Designers use software specific to the programming technology and FPGA architecture
to implement the programmable connections.
FPGAs are popular for prototyping systems or low-volume production due to their flexibility and ease of
programming. They bridge the gap between traditional TTL and PLD design and modern, complex ASICs. The
ability to program FPGAs without the need for customization at the mask level makes them cost-effective for
various applications.

Explain in detail steps involved in ASIC Design flow.

With neat flow chart, explain ASIC design flow

With neat flow diagram, explain the steps involved in ASIC design

The ASIC design flow involves several key steps as outlined in the document you provided:

1. Design Entry: The process begins by entering the design into an ASIC design system using a hardware
description language (HDL) or schematic entry.
2. Logic Synthesis: Using an HDL such as VHDL or Verilog along with a logic synthesis tool to generate a
netlist, which describes the logic cells and their connections.
3. System Partitioning: Large systems are divided into ASIC-sized pieces for more manageable design and
implementation.
4. Prelayout Simulation: This step involves checking the design to ensure proper functionality before moving
forward.
5. Floorplanning: Blocks of the netlist are arranged on the chip, determining the physical layout of the design.
6. Placement: Deciding the locations of cells within a block to optimize performance and connectivity.
7. Routing: The final step involves creating the physical wiring connections between the placed cells to
complete the design.
CMOS Logic:
CMOS Logic: Data path Logic Cells: Data Path Elements, Adders: Carry skip, Carry bypass, Carry save, Carry
select, Conditional sum, Multiplier (Booth encoding), Data path Operators, I/O cells, Cell Compilers.

Explain barrel shifter, leading one detector and priority encoder with examples
A barrel shifter is a digital circuit that can shift a data word by a specified number of bit positions in one clock
cycle. It can shift the input data left or right, allowing for fast multiplication or division by powers of two.
For example, if we have a 4-bit binary number 1010 and we want to shift it right by 2 positions using a barrel
shifter, the output will be 0010.
A leading one detector is a circuit that detects the most significant (leftmost) '1' bit in a binary number. It is
commonly used in conjunction with a barrel shifter to determine the number of shifts needed when performing a
logical or arithmetic shift.
For instance, if we have the binary number 11010100 and we apply a leading one detector to it, the output will
be 11000000, indicating that the leading '1' is located at the 6th bit position.
A priority encoder is a digital circuit that converts multiple input lines into a single output line based on the
priority of the inputs. It encodes the highest priority active input into a binary code.
For example, if we have 4 inputs but only input 3 is active, the output of a priority encoder will be 11 (assuming a
binary encoding scheme), indicating that input 3 has the highest priority.

1. Barrel Shifter:
o A barrel shifter is a digital circuit that can shift the input data by a specified number of bit positions
in a single clock cycle.
o It can perform logical shifts (left or right) or rotations on binary numbers.
o For example, if you have an input of '1111 0000' and you specify a right shift of '0001 0000', the
output would be '0001 1110'.
o Barrel shifters are commonly used in arithmetic operations and can have variable shift amounts and
directions.
2. Leading One Detector:
o A leading-one detector is used to identify the position of the most significant '1' bit in a binary
input.
o It outputs a binary pattern with a single '1' at the position of the leading '1' in the input.
o For instance, if the input is '0000 0101', the output of the leading-one detector would be '0000 0100',
indicating the position of the leading '1'.
o Leading-one detectors are utilized in floating-point arithmetic to normalize numbers by aligning the
mantissas.
3. Priority Encoder:
o A priority encoder is a combinational circuit that encodes the priority of multiple binary inputs.
o It outputs a binary-encoded position representing the highest priority '1' in the input.
o For example, with an input of '0000 0101', the output of a 4-bit priority encoder would be '0011' (3),
indicating the position of the leading '1'.
o Priority encoders are useful in applications where multiple inputs need to be prioritized based on
their significance.

These components play crucial roles in digital circuit design, enabling operations such as data manipulation,
normalization, and encoding based on specific criteria within the circuitry.

Describe three state bidirectional output buffer with neat circuit diagram

A three-state bidirectional output buffer functions as follows:

  When the output enable (OE) signal is high, the buffer operates as a noninverting buffer, transferring the
value from the input data (DATAin) to the I/O pad.
 In contrast, when the OE signal is low, the output transistors or drivers (M1 and M2) get disconnected,
allowing multiple drivers to connect to a bus without contention issues.
 To prevent floating buses, a bus keeper or bus-hold cell can be employed, maintaining the last logic state
on the bus.
 The circuit includes large off-chip drivers (M1 and M2) capable of handling significant loads, ensuring
efficient signal transmission.

With a relevant cell diagram and equations. Explain 4 bit Carry Look Ahead adder (CLA).

a 4-bit Carry Look Ahead Adder (CLA) can be explained as follows:

 A 4-bit CLA utilizes a carry-lookahead generator cell (CLG) to efficiently compute the carry signals in
parallel rather than sequentially, reducing propagation delays.
 The carry signals for each bit position (C[0] to C[3]) are generated using a combination of the generate (G)
and propagate (P) signals.
 The CLA architecture allows for faster addition by calculating the carry signals based on the input bits,
improving performance compared to ripple-carry adders.
 By implementing lookahead logic, the CLA reduces the time required to determine carry bits, enhancing
the overall speed of addition operations in digital circuits.

Equations such as C[2] = G[2] + P[2] · G[1] + P[2] · P[1] · G[0] and C[3] = G[3] + P[2] · G[2] + P[2] · P[1] · G[1]
+ P[3] · P[2] · P[1] · G[0] are used to calculate the carry signals efficiently in a 4-bit CLA.

The implementation of a 4-bit CLA with lookahead logic enhances the speed and efficiency of addition operations
in digital systems, making it a valuable component in arithmetic circuits.

Explain the functioning and limitation of conventional Ripple carry adder (RCA), with
relevant logic equation and cell diagram

The conventional Ripple Carry Adder (RCA) is a simple form of adder that calculates the sum of two binary
numbers by cascading full adder cells together, with each full adder's carry output connected to the next full
adder's carry input. Here's how it functions and its limitations based on the provided context:

Functioning of Ripple Carry Adder (RCA):

 In an n-bit RCA, each full adder cell receives input bits A, B, and the carry-in (CIN) from the previous
stage and produces the sum output (S) and the carry-out (COUT).
 The sum (S) output is the XOR of the three inputs (A, B, and CIN), while the carry-out (COUT) is the
majority function (1 if two or more inputs are 1) of the three inputs.
 By connecting multiple full adder cells in series, the RCA computes the sum of two n-bit binary numbers,
propagating the carry bit from one stage to the next.

Limitations of Ripple Carry Adder (RCA):

 The main limitation of an RCA is its inherent delay in calculating the carry bit. Each full adder's carry
decision depends on the carry-out from the previous full adder, causing a cumulative delay as the carry
signal ripples through the adder.
  This sequential carry calculation results in a significant propagation delay, especially in adders with a large
number of bits, impacting the overall speed of addition.
 As a result, the RCA is not ideal for high-speed applications where fast arithmetic operations are required
due to the carry propagation delay.

By understanding the functioning and limitations of the conventional Ripple Carry Adder, designers can make
informed choices about the type of adder to use based on the speed requirements and performance considerations
of the digital circuit.

With relevant diagram and equations, explain the Conventional Ripple Carry Adder.
Mention its limitations

The conventional Ripple Carry Adder has some limitations, such as:

1. Propagation Delay: The Ripple Carry Adder has a linear carry propagation delay, which means that the carry bit
ripples through each stage, resulting in longer delay times for larger numbers of bits.
2. Limited Parallelism: Due to the carry propagation mechanism, the Ripple Carry Adder cannot perform addition
of multiple-bit numbers in parallel, which limits its speed and efficiency compared to other adder architectures.
3. High Power Consumption: The Ripple Carry Adder requires a large number of gates and transistors to implement
the carry propagation logic, leading to higher power consumption compared to other adder designs.
4. Limited Scalability: As the number of bits in the operands increases, the Ripple Carry Adder becomes slower and
less efficient due to the cascading carry propagation delays.
5. Not suitable for high-performance applications: Due to its limitations in speed, power consumption, and
scalability, the Ripple Carry Adder is not the best choice for high-performance applications that require fast and
efficient arithmetic operations.

What are the limitations of Ripple Carry Adder. How this problem is overcome in carry
save adder. Illustrate with neat circuit diagram

In a carry-save adder, the Ripple Carry Adder problem is overcome by initially adding all the bits in parallel
instead of sequentially. This allows for a significant reduction in propagation delays, as carry signals can be
generated independently and then merged together efficiently. Additionally, the carry-save adder separates the sum
and carry outputs, reducing the number of critical paths in the circuit and improving overall performance.

Draw the circuit for a conventional Ripple Carry Adder (RCA). Write the equations for the
carry signal.

Explain carry select adder and how it is extended to form n-bit conditional sum adder

With a neat diagram, explain the working of a conditional sum adder

Explain Wallace Tree Multiplier

A Wallace Tree Multiplier is a parallel multiplier algorithm used for performing multiplication of two numbers. It
is an efficient way to multiply numbers by breaking down the multiplication operation into a series of partial
products and then adding these partial products together to get the final result.
The Wallace Tree Multiplier uses a tree structure to compute the partial products and sum them in a more efficient
way than traditional multipliers. This method reduces the number of partial products that need to be added
together, resulting in faster multiplication without significantly increasing the hardware complexity.

Overall, the Wallace Tree Multiplier is known for its speed and efficiency in performing multiplication operations,
making it a popular choice in digital circuit design for applications that require fast and efficient multiplication.

Write a short note on :

i) I/O cells
ii) Cell compilers.

Cell compilers are tools that are used to automatically generate optimized code for specific hardware
configurations from high-level descriptions of computations. These compilers take in high-level code written in
languages such as TensorFlow or PyTorch and translate it into efficient code that can run on specialized hardware
like GPUs, TPUs, or FPGAs. By doing so, cell compilers can significantly speed up the execution of machine
learning models and deep learning algorithms on various platforms.