VERIFICATION OF AND GATE USING UVM
DESIGNING PART OF AND-GATE:-
AND gate is used to perform logical Multiplication of binary input. The Output state of the AND gate will
be high(1) if both the input are high (1),else the output state will be low(0) if any of the input is low(0).
a b y module and_gate(a,b,y);
0 0 0 input a, b;
a y
output y;
y 0 1 0
assign y=a&b;
b 1 0 0 endmodule
1 1 1
VERIFICATION PART:-
1. Interface:
An interface in System Verilog is a construct that groups related signals (like clock, reset, read/write
controls) and optionally includes clocking blocks, mod ports, or tasks/functions.
interface intf();
bit a;
bit b;
bit y;
endinterface
2. UVM Sequence Item/Transaction:
A uvm_sequence_item represents a single transaction or operation to be driven on the DUT interface.
It is a class that defines the fields (such as address, data, control signals) used in communication and is
extended to model protocol-specific operations like AXI read/write or APB transfers. It’s the core element
passed from sequence → sequencer → driver.
class tx extends uvm_sequence_item;
`uvm_object_utils(tx)
function new(string name="");
super.new(name);
endfunction //factory registration
//properties
rand bit a; //inputs declared as rand keyword rand bit b;
bit y; // output come from design no need of
randomizing
endclass
Cognitive Learner’s
VERIFICATION OF AND GATE USING UVM
3. UVM Sequence:
A UVM Sequence is an object that contains a behavior for generating stimulus.
class and_sequence extends uvm_sequence#(tx);
//fcatory registrtion
`uvm_object_utils(and_sequence) function new(string name="");
super.new(name);
endfunction
//need to genrate 10 time random values task body();
repeat(10)begin
`uvm_do(req);//10 time randomize
end
endtask
endclass
4. UVM Sequencer:
The UVM Sequencer serves as an arbiter for controlling transaction flow from multiple
stimulus sequences.
class and_sequencer extends uvm_sequencer#(tx);
//factory registration
`uvm_component_utils(and_sequencer)
function new(string name="", uvm_componentparent=null);
super.new(name,parent);
endfunction
endclass
Cognitive Learner’s
VERIFICATION OF AND GATE USING UVM
5. UVM Driver:
The UVM Driver receives individual UVM Sequence Item transactions from the UVM
Sequencer and applies (drives) it on the DUT Interface.
class and_driver extends uvm_driver#(tx);
//fcatory registrtion
`uvm_component_utils(and_driver)
function new(string name="", uvm_component parent=null);
super.new(name,parent);
endfunction
//we need to get pointed virtual interface from top module
virtual intf nvif;
function void build_phase(uvm_phase phase);
super.build_phase(phase);
uvm_config_db#(virtualintf)::get(this,"*","vif",nvif);
endfunction
task run_phase(uvm_phase phase);
super.run_phase(phase);
repeat(10)begin
//TLM mainly used to get the data in uvm
seq_item_port.get_next_item(req);
$display("inside bfm a=%d b=%d y=%d",t.a,t.b,t.y);
nvif.a=req.a; //scope resolution operator
nvif.b=req.b;
#1;
//body method is fixed, built in method no need to call automaticaly will executed
seq_item_port.item_done;
//send response to sequencer end
end
endtask
endclass
Cognitive Learner’s
VERIFICATION OF AND GATE USING UVM
6. UVM Monitor:
The UVM Monitor samples the DUT interface and captures the information there in transactions that are
sent out to the rest of the UVM Testbench for further analysis.
class and_monitor extends uvm_monitor;
`uvm_component_utils(and_monitor) function new(string name="",
uvm_component parent=null);
super.new(name,parent);
endfunction
//virtual interface
virtual intf nvif;
//tlm handel creation
uvm_analysis_port#(tx) ap_mon;
//object creation
function void build_phase(uvm_phase phase);
super.build_phase(phase); ap_mon=new("ap_mon",this);
uvm_config_db#(virtualintf)::get(this,"*","vif",nvif);
endfunction
tx t;
task run_phase(uvm_phase phase);
super.run_phase(phase);
t=new();
repeat(10)begin
t.a=nvif.a;
t.b=nvif.b;
t.y=nvif.y;
//common::mon2sco.put(t);
ap_mon.write(t);
//common::mon2cov.put(t);
$display("inside monitor a=%d b=%d y=%d",t.a,t.b,t.y);
#1;
end
endtask
endclass
Cognitive Learner’s
VERIFICATION OF AND GATE USING UVM
7. UVM Scoreboard:
The UVM Scoreboard’s main function is to check the behavior of a certain DUT.
class and_scoreboard extends uvm_scoreboard;
`uvm_component_utils(and_scoreboard);
function new(string name="",
uvm_component parent=null);
super.new(name,parent);
endfunction
//handel creation tlm
uvm_tlm_analysis_fifo#(tx) sco_fifo;
//object tlm
function void build_phase(uvm_phasephase);
super.build_phase(phase);
sco_fifo=new("sco_fifo",this);
endfunction
8. Coverage:
tx t,s;
Coveragetaskisrun_phase(uvm_phase phase);
used to measure and track howsuper.run_phase(phase); repeat(10)begin
thoroughly a testbench has exercised the DUT’s
t=new();
functionality. s=new();
sco_fifo.get(t);
class and_coverage
//t.a and t.b to s.a and extends
s.b uvm_subscriber#(tx);
`uvm_component_utils(and_coverage) tx t1;
//expected data
covergroup cg; s.y= t.a && t.b;
A: coverpoint t1.a; if(s.y == t.y)
B:$display("scoreboard
coverpoint t1.b; pass expected=%0d actual=%0d",s.y,t.y);
Y: coverpoint t1.y; else
endgroup
$display("scoreboard fail expected=%0d actual=%0d",s.y,t.y);
end endtask
endclass function new(string name="", uvm_component parent=null);
super.new(name,parent);
cg=new();
endfunction
function void write(tx t);
//get data from monitor
t1=t; cg.sample();
endfunction
endclass
Cognitive Learner’s
VERIFICATION OF AND GATE USING UVM
9. UVM Agent:
The UVM Agent is a hierarchical component that groups together other verification
components that are dealing with a specific DUT interface
class and_agent extends uvm_agent;
`uvm_component_utils(and_agent)
function new(string name="",uvm_component parent=null);
super.new(name,parent); endfunction
//need to include and_sequencer and and_driver
//handel creation
and_sequencer and_seqr;
and_driver and_drv;
and_monitor and_mon;
//object creation
function void build_phase(uvm_phase phase);
super.build_phase(phase);
and_seqr=and_sequencer::type_id::create("and_ seqr",this);
and_drv=and_driver::type_id::create("and_drv",t his);
and_mon=and_monitor::type_id::create("and_m on",this);
endfunction
//connet sequencer to driver
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
and_drv.seq_item_port.connect(and_seqr.seq_item_export);
endfunction
endclass
10. UVM Environment:
The UVM Environment is a hierarchical component that groups together other verification
components that are interrelated.
Cognitive Learner’s
VERIFICATION OF AND GATE USING UVM
class and_env extends uvm_env;
//factory registration
`uvm_component_utils(and_env) function new(string name="",
uvm_component parent=null);
super.new(name,parent);
endfunction
//include agent class and_agent agent;
and_coverage and_cov; and_scoreboard and_sco;
function void build_phase(uvm_phase phase);
super.build_phase(phase);
agent=and_agent::type_id::create("agent",this);
and_cov=and_coverage::type_id::create("and_cov",t his);
and_sco=and_scoreboard::type_id::create("and_sco ",this);
endfunction
function void connect_phase(uvm_phasephase);
super.connect_phase(phase);
agent.and_mon.ap_mon.connect(and_cov.analysis_ export);
//mon to sco
agent.and_mon.ap_mon.connect(and_sco.sco_fifo.a nalysis_export);
endfunction
endclass
11. UVM Test:
The UVM Test is the top-level UVM Component in the UVM Testbench.
class and_test extends uvm_test;
`uvm_component_utils(and_test)function new(string name="",
uvm_component parent=null);
super.new(name,parent);
endfunction
//include env class and_env env;
function void build_phase(uvm_phase phase);
super.build_phase(phase);
env=and_env::type_id::create("env",this);
endfunction
Cognitive Learner’s
//need to connect sequence to sequencer
task run_phase(uvm_phase phase);
//no need to super.run_phase
VERIFICATION OF AND GATE USING UVM
//object creation of sequence
seq=and_sequence::type_id::create("seq");
//connet sequence to sequencer
phase.raise_objection(this); seq.start(env.agent.and_seqr);
//connecting from sequence to sequencer
phase.drop_objection(this); endtask
endclass
12. UVM Testbench/ Top Module: The UVM Testbench typically instantiates the Design under Test
(DUT) module and the UVM Test class, and configures the connections between them.
module top;
//declare physical interface intf n();
//connect design with tb
and_gate dut(.a(n.a),.b(n.b),.y(n.y));
//include test class initial begin
run_test("and_test"); end
initial begin
uvm_config_db#(virtual intf)::set(null,"*","vif",n);
//poitning from physical interface to virtual interface
end
endmodule
Cognitive Learner’s
VERIFICATION OF AND GATE USING UVM
OUTPUT :-
Scoreboard and Monitor Report:-
Coverage Report:-
Cognitive Learner’s
