Clock Tree Synthesis
Simplified
Akella Madhav
VLSI Design
Problem Formulation
Specialized algorithms are required for clock and power nets due to strict specifications for routing such nets.
What makes them special?
• Complicated nets
• Designing takes care of area optimization, but chip performance (mainly power and speed) improvement is
dependent on these two net distribution schemes.
• Chip performance directly proportional to clock frequency.
As chip operating frequency and voltage levels scale down due to the reduction in feature size, Clock and power
routing becomes a harder challenge.
Clock Routing
• Data transfer between functional elements is synchronized by clock.
• Clock synchronization is one of the most critical considerations in designing high-
performance VLSI circuits.
• The clock signal is typically generated external to the chip. Each functional unit which needs
the clock is connected to clock pin by the clock net.
Skew
The time taken by Clock signal to reach from clock source to the clock pin of a particular flip flop is called as
Clock latency.
Clock Skew is the time difference between arrival of the same edge of a clock signal at the Clock pin of the
capture flop and launch flop.
Clock skew can also be termed as the difference between the capture flop latency and the launch flop latency.
Work it out:
Positive skew, negative skew, Effect of each on
setup and hold slacks/violation.
Causes and Impacts of Skew.
Causes:
• Unequal lengths of wire from clock source to clock ports of sequential elements.
• Absence of proper clock distribution strategy
• Variations in the delays of buffers.
• Process dependent transistors
• Unequal capacitive loads at outputs.
Impacts
• Setup and Hold Violations
• Inability to operate the chip in desired operating frequency for accounting uncertainties.
• Complications and possibly complete failure of chip.
Modern day ICs cannot tolerate a clock skew of more than 10% of the system clock period.
– A good clock distribution strategy is necessary.
– Also, a requirement for designing high-performance circuits.
Buffering
• Routing schemes are simply arrangements of interconnecting wires which contribute for the
interconnect delays.
• Goal is to minimize the interconnect delay.
• The delay caused by long wires (in case of clocks) is due to their capacitances and
resistances.
• Long wires have large capacitive loads and large resistances.
• RC delay cannot be reduced by making the wires wider.
– Resistance reduces, but capacitance increases.
• Solution:
Use buffers along the path
Why buffers:
• Buffers act as waveform repeaters, thereby restroring the strength of the signal for transversing long distances.
• Reduction in RC delay.
• How?
Clock Buffering: Approach 1: Use a big, centralized buffer.
Clock Buffering: Approach 2: Distribute buffers in the branches of the clock tree.
Use identical buffers so that the delay introduced by the
buffers is equal in all branches.
a) Centralised Buffer
b) Distributed buffer Tree
Clock Routing Algorithms
GOAL: Minimize clock uncertainty especially skew
How to minimize skew?
Distribute the clock signal in such a way that the interconnections carrying the clock
signal to functional sub-blocks are equal in length.
Some of the popular clock routing algorithms:
• H tree based algorithm
• X tree based algorithm
• MMM algorithm
• Geometric Matching based algorithm
• Weighted center algorithm
• Exact zero skew algorithm
• Mesh algorithm
In (a), all points are exactly 7 units from the point P0, and hence the skew is zero.
This ensures minimum-delay routing as well.
• P0 and P3 are at a distance 7 (rectilinear distance).
• Can be generalized to n points, where n is a power of 4.
Algorithm Steps:
1) Root clock insertion
2) Recursive branching
3) Buffer Insertion
4) Load balancing
Basic principle of the construction of H tree based algorithm:
1) Top down approach
2) Finding the centroids of the sink nodes
3) The overall area containing the sink nodes is recursively divided into smaller regions. Typically,
this division is done by bisecting the area along its horizontal and vertical axes.
▪ If routing is not restricted to being rectilinear X tree
algorithm can be used.
▪ Similar to H-tree but the connections are not
rectilinear in the X tree-based approach.
▪ Undesirable as they may cause crosstalk due to close
proximity of wires.
▪ H tree clock lines do not produce corners sharper than
90 degrees, and no two clock lines in an H tree are ever
in close proximity.
Thank You
