Module-II

ARM Architecture
M Naresh Kumar
Asst.Prof., Dept.of EECE
GITAM (Deemed to be Univeesity)

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CISC vs RISC

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 RISC Design policy
• The ARM core uses a RISC architecture.

• RISC is a design philosophy aimed at delivering simple

but powerful instructions that execute within a single
cycle at a high clock speed

• The RISC philosophy concentrates on reducing the

complexity of instructions performed by the hardware
because it is easier to provide greater flexibility and
intelligence in software rather than hardware.

• RISC design places greater demands on the compiler

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RISC Design policy

CISC relies more on the hardware for instruction

functionality, and consequently the CISC instructions are
more complicated

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RISC Design policy
The RISC philosophy is implemented with four major
design rules:

1. Instructions
2. Pipelines
3. Registers
4. Load-store architecture

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RISC Design policy
1. Instructions:
• RISC processors have a reduced number of instruction
classes.
• These classes provide simple operations that can each
execute in a single cycle.
• The compiler synthesizes complicated operations by
combining several simple instructions.
• Each instruction is a fixed length to allow the pipeline to
fetch future instructions before decoding the current
instruction
• CISC processors the instructions are often of variable size
and take many cycles to execute.
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RISC Design policy

2. Pipelines
• The processing of instructions is broken down into
smaller units that can be executed in parallel by
pipelines.

• Ideally the pipeline advances by one step on each

cycle for maximum throughput.

• Instructions can be decoded in one pipeline stage

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RISC Design policy

2. Pipelines
• The processing of instructions is broken down into
smaller units that can be executed in parallel by
pipelines.

• Ideally the pipeline advances by one step on each

cycle for maximum throughput.

• Instructions can be decoded in one pipeline stage

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RISC Design policy

3. Registers

• RISC machines have a large general-purpose

register set.
• Any register can contain either data or an address.
• Registers act as the fast local memory store for all
data processing operations.
• In contrast, CISC processors have dedicated
registers for specific purposes.

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RISC Design policy

4. Load-store architecture
• The processor operates on data held in registers.
• Separate load and store instructions transfer data
between the register bank and external memory.
• Memory accesses are costly, so separating memory
accesses from data processing provides an advantage
because you can use data items held in the register
bank multiple times without needing multiple memory
accesses.
• In contrast, with a CISC design the data processing
operations can act on memory directly.

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The ARM Design Philosophy
Number of physical features
1.Portable embedded systems require some form of battery
power.

The ARM processor has been specifically designed to be small

to reduce power consumption and extend battery operation—
Mobile phones and personal digital assistants (PDAs).

2. High code density is another major requirement since

embedded systems have limited memory due to cost and/or
physical size restrictions.

High code density is useful for applications that have limited on-
board memory, such as mobile phones and mass storage devices.

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The ARM Design Philosophy
3. Embedded systems are price sensitive and use slow and
low-cost memory devices.
For high-volume applications like digital cameras, every
cent must be accounted for in the design.

4. Important requirement is to reduce the area of the die

taken up by the embedded processor
The smaller the area used by the embedded processor, the
more available space for specialized peripherals.

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The ARM Design Philosophy
Classification of embedded system
5. ARM has incorporated hardware debug technology
within the processor so that software engineers can view
what is happening while the processor is executing code.

Software engineers can resolve issues faster, which has a

direct effect on the time to market and reduces overall
development costs.

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The General-Purpose Registers (GPR’s) in the ARM

• CPUs use registers to store data temporarily.

• To program in Assembly language, we must understand the
registers and architecture of a given CPU and the role they
play in processing data.

• That information could be a byte of data to be processed, or

an address pointing to the data to be fetched
The 32 bits of a register are shown below

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The General-Purpose Registers (GPR’s) in the ARM

Classification of embedded system

• The 32-bit data size of the ARM is often referred as word
• In ARM there are 13 general purpose registers. They are
R0–R12

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The General-Purpose Registers (GPR’s) in the ARM

Classification of embedded system

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The General-Purpose Registers (GPR’s) in the ARM

Classification of embedded system

• The general-purpose registers in ARM are the same as the
accumulator in other Microprocessors.
• They can be used by all arithmetic and logic instructions.
• The ARM core has three special function registers of R13, R14, and
R15.

ARM Instruction Format

• The ARM CPU uses the tri-part instruction format for most
instructions. One of the
instruction destination,source1,source2
• Depending on the instruction the source2 can be a register,
immediate (constant) value, or memory. The destination is often a
register or read/write memory.
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Contd…
Classification of embedded system
MOV instruction:
• Simply stated, the MOV instruction copies data into register or from
register to register. It has the following formats:
• MOV Rn,Op2 ;load Rn register with Op2 (Operand2). Op2 can be
immediate
• Op2 can be an immediate (constant) number #K which is an 8-bit
value that can be 0–255 in decimal, (00–FF in hex). Op2 can also be
a register Rm. Rn or Rm are any of the registers R0 to R15. If we
see the word “immediate”, we are dealing with a constant value that
must be provided right there with the instruction. Notice the # before
immediate values.
• The following instruction loads the R2 register with a value of 0x25
(25 in hex).
• MOV R2,#0x25 ;load R2 with 0x25 (R2 = 0x25)
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Contd…
Classification of embedded system
MOV instruction:
•MOV R1,#0x87 ;copy 0x87 into R1 (R1 = 0x87)
•The following instruction loads R5 with the value
of R7.
•MOV R5,R7 ;copy contents of R7 into R5 (R5 = R7)

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Contd…
Classification of embedded system
MOV instruction:
• When programming the registers of the ARM microcontroller with
an immediate value, the following points should be noted:
1. We put # in front of every immediate value.
2. If we want to present a number in hex, we put a 0x in front of it. If
we put nothing in front of a number, it is in decimal. For example, in
“MOV R1,#50”, R1 is loaded with 50 in decimal, whereas in “MOV
R1,#0x50”, R1 is loaded with 50 in hex ( 80 in decimal).
3. If values 0 to FF are moved into a 32-bit register, the rest of the bits
are assumed to be all zeros. For example, in “MOV R1,#0x5” the
result will be R1=0x00000005; that is,
R1=00000000000000000000000000000101 in binary.
4. Moving an immediate value larger than 255 (FF in hex) into the
register will cause an error.
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Contd…
Classification of embedded system
MOV instruction:
• Note!
• We cannot load values larger than 0xFF (255) into
registers R0 to R12 using the MOV instruction. For
example, the following instruction is not valid:
• MOV R5,#0x999999 ;invalid instruction
• The reason is the fact that although the ARM instruction
is 32-bit wide, only 8 bits of MOV instruction can be used
as an immediate value which can take values not larger
than 0xFF (255).

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Contd…
Classification of embedded system
ADD instruction:
• The ADD instruction has the following format:
• ADD Rd,Rn,Op2 ;ADD Rn to Op2 and store the result in Rd;Op2 can
be Immediate value #K (K is between 0 and 255) ;or Register Rm
• Example:
• MOV R1,#0x25 ;copy 0x25 into R1 (R1 = 0x25)
• MOV R7,#0x34 ;copy 0x34 into R1 (R7 = 0x34)
• ADD R5,R1,R7 ;add value R7 to R1 and put it in R5
• ;(R5 = R1 + R7)
• or
• MOV R1,#0x25 ;load (copy) 0x25 into R1 (R1 = 0x25)
• ADD R5,R1,#0x34 ;add 0x34 to R1 and put it in R5
• ;(R5 = R1 + 0x34)
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ARM registers and ALU:
Classification of embedded system

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ALU Instructions using GPRs:
Classification of embedded system

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Contd…
Classification of embedded system

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CPSR(Current Program Status Register)
Classification of embedded system
• Like all other microprocessors, the ARM has a flag
register to indicate arithmetic conditions such as the
carry bit. The flag register in the ARM is called the
current program status register (CPSR).

• In this section, we discuss various bits of this register

and provide some examples of how it is altered

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CPSR(Current Program Status Register)
Classification of embedded system
• The status register is a 32-bit register. See Figure for the bits of the
status register. The bits C, Z, N, and V are called conditional flags,
meaning that they indicate some conditions that result after an
instruction is executed. Each of the conditional flags can be used to
perform a conditional branch (jump).

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CPSR(Current Program Status Register)
Classification of embedded system
C, the carry flag
This flag is set whenever there is a carry out from the D31 bit. This
flag bit is affected after a 32-bit addition or subtraction. Chapter 4
shows how the carry flag is used.

Z, the zero flag

The zero flag reflects the result of an arithmetic or logic operation. If
the result is zero, then Z = 1. Therefore, Z = 0 if the result is not zero.
See Chapter 4 to see how we use the Z flag for looping.

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CPSR(Current Program Status Register)
Classification
N: The negative flag of embedded system
• Binary representation of signed numbers uses D31 as the sign bit.
• The negative flag reflects the result of an arithmetic operation.
• If the D31 bit of the result is zero, then N = 0 and the result is
positive.
• If the D31 bit is one, then N = 1 and the result is negative. The
negative and V flag bits are used for the signed number
arithmetic operations.
V: The overflow flag
• This flag is set whenever the result of a signed number operation
is too large, causing the high-order bit to overflow into the sign
bit.
• In general, the carry flag is used to detect errors in unsigned
arithmetic operations while the overflow flag is used to detect
errors in signed arithmetic operations. The V and N flag bits are
used for signed number arithmetic operations.
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CPSR(Current Program Status Register)
Classification
• The T flag bit isof embedded
used to indicatesystem
the ARM is in Thumb
state.
• The I and F flags are used to enable or disable the
interrupt.

S: Suffix and the status register

• Most of ARM instructions can affect the status bits of
CPSR according to the result.
• If we need an instruction to update the value of status
bits in CPSR, we have to put S suffix at the end of
instructions. That means, for example, ADDS instead of
ADD is used.
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CPSR(Current Program Status Register)-Example:

Classification of embedded system

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CPSR(Current Program Status Register)
Solution:

1) C = 1 because there is a carry beyond the D31 bit.

Classification
Z = 1 because theof
R2embedded
(the result) hassystem
value 0 in it after the
addition.

2) C = 1 because there is a carry beyond the D31 bit.

Z = 0 because the R2 (the result) does not have value 0 in it
after the addition.
(R2=0x00000005)

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CPSR(Current Program Status Register)
Example:

Classification of embedded system

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CPSR(Current Program Status Register)

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ARM Family & Architecture

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