VISVESVARAYA TECHNOLOGICAL UNIVERSITY
BELAGAVI – 590 018
Course Project Report
on
Advanced VLSI
21EC71
Topic: System Verilog Struct Data Type
Submitted by
1.ABHISHEK G D 4BD21EC004
2.ARUN KUMAR U 4BD21EC014
3.GURUKIRAN P M 4BD21EC033
4.JEETENDRA M 4BD21EC041
Smt.Savithri G R Dr. G S SUNITHA
M.Tech, , MISTE, MIE, MIETE M.Tech (DEAC), Ph.D., MISTE, FIETE, FIE
Course Instructor Program Coordinator
Bapuji Educational Association®
Bapuji Institute of Engineering and Technology Davangere-577 004
Department of Electronics & Communication Engineering
2024-2025
CONTENTS
1. Introduction about EDA Playground 1
2. System Verilog Struct Data Type 2
3. SystemVerilog Packed Struct 3
4. SystemVerilog UnPacked Struct 5
5. Conclusion 6
6. References 7
Introduction about EDA Playground:
EDA Playground is an online platform designed for exploring and experimenting
with various hardware description languages (HDLs) such as Verilog, VHDL, and
SystemVerilog. It provides a simple and accessible interface for users to write,
simulate, and test their code without needing to install complex software or
hardware tools. The platform aims to cater to both beginners and experienced
developers by offering a quick setup for small projects or educational exercises.
EDA Playground is widely used in academia and the industry for quick
prototyping, learning, and validating designs.
One of the key features of EDA Playground is its ability to integrate multiple
simulators like ModelSim, XSIM, and other simulation engines directly within
the platform. Users can select the desired simulator based on their needs and
preferences, allowing for a flexible and customizable simulation environment. It
also supports multiple languages and includes code examples and templates to
assist in the learning process. This flexibility makes EDA Playground a valuable
resource for developers working on digital design and verification.
Additionally, EDA Playground fosters collaboration by allowing users to share
their code and results with others through direct links or by creating public
projects. This community aspect enhances the learning experience, as users can
seek help, explore others' projects, and share knowledge. With its cloud-based
nature, EDA Playground also eliminates the need for costly software licenses or
complex setups, making it an accessible tool for students, educators, and
professionals working in digital design and verification.
1
System Verilog Struct Data Type :
SystemVerilog’s struct data type allows users to define complex data structures
by grouping together variables of different types under a single entity. This allows
for better organization of related data and makes it easier to manage and
manipulate multiple variables that belong together. Structs are similar to struct
types in other programming languages like C, and they provide a way to group
multiple elements into one logical unit. This feature is especially useful in
hardware design, where structured data is often needed.
To define a struct, SystemVerilog uses the struct keyword followed by the type
name and the elements that belong to the struct. Each element can be of any data
type, whether primitive types like int or more complex types like arrays or other
structs. The endstruct keyword is used to terminate the definition. This structure
provides a clean and understandable way to group related variables, making code
easier to read and maintain.
A key benefit of using structs in SystemVerilog is their ability to hold different
data types under a single name, which simplifies code management. For example,
a struct might hold both a signal value and its associated status, or a combination
of control and status registers. This organization is especially valuable in
hardware verification, where different components may need to be tested together
as part of a single testbench scenario. It allows for easy reference to all related
data at once, reducing the chance of errors.
Structs in SystemVerilog also support operations like initialization, assignment,
and passing between modules. They can be assigned directly to other structs of
the same type or passed around as function arguments. This feature provides
flexibility when working with large systems or when modeling complex
behaviors, as struct members can be accessed directly using the dot (.) operator.
The ability to work with these complex structures seamlessly is a major advantage
in hardware design and simulation.
Another important aspect of SystemVerilog structs is their compatibility with
randomization and constraints. This allows structs to be randomized when used
in testbenches to simulate various scenarios. Constraints can be applied to
individual struct members to control their values, ensuring that the struct behaves
according to the desired specification. This makes structs not only useful for
organizing data but also for creating flexible and randomized test scenarios in
verification environments.
2
SystemVerilog Packed Struct :
Struct defined with the keyword Packed is referred as packed struct
Only packed data types and integer data types are allowed with in the packed
struct
In SystemVerilog, a packed struct is a type of struct that stores its data elements
without any padding between them, making the struct more memory-efficient. By
default, SystemVerilog structs are packed, meaning the elements are placed in a
contiguous block of memory, which is crucial in hardware design where memory
efficiency is often a concern. Packed structs are particularly useful when working
with bit-level operations, as they allow for tighter control over the layout of data.
This is especially important when designing hardware or working with registers
in digital systems.
The definition of a packed struct is similar to a regular struct, but the packed
keyword is explicitly added. The packed struct allows SystemVerilog to tightly
pack the bits, meaning the total number of bits used is minimized and the struct’s
size matches the exact number of bits required by the individual elements. This
feature is often used for bit-fields, registers, or other compact data representations
where every bit counts. It ensures that no unnecessary memory space is wasted.
Packed structs are highly effective in scenarios where data needs to be mapped
directly to hardware registers or memory. In digital design, a packed struct can be
used to represent a group of control signals, status flags, or packed arrays of bits,
all of which need to be stored without extra overhead. By packing the data
elements together, the designer can ensure that each bit in the struct corresponds
exactly to a signal in the hardware. This direct mapping reduces the complexity
when interacting with hardware.
One significant advantage of packed structs in SystemVerilog is their support for
bit-select and part-select operations. Users can access or modify specific bits or
ranges of bits within a packed struct using the [] operator, which provides fine-
grained control over individual bits. This capability is vital in hardware design
when dealing with specific control registers or signals that need to be manipulated
at the bit level. It simplifies operations like masking or shifting bits directly in the
struct.
By applying constraints to specific bits or fields within the struct, designers can
control the values during simulation, enabling targeted and efficient testing of
hardware designs.
3
PACKED STRUC T EXAMPL E
module struct_tb;
typedef struct packed {
bit [7:0] addr;
bit valid;
bit [31:0] data;
} mem_pkt;
mem_pkt pkt;
initial begin
// Initializing Struct
pkt = '{8'h6, 1'b1, 32'hC001_0FAB};
$display ("pkt = %p", pkt);
// Change the struct field value
pkt.addr = 8'h8;
$display ("pkt = %p", pkt);
// Change the struct field value
pkt.data = 32'hFFF0_0FFF;
$display ("pkt = %p", pkt);
end
endmodule
OUTPUT :
4
SystemVerilog UnPacked Struct :
In SystemVerilog, an unpacked struct is a type of struct where the data elements
are not packed together in a contiguous block of memory. Unlike packed structs,
where each member is tightly packed without gaps, an unpacked struct allows the
members to have padding or gaps between them. This type of struct is more
flexible and suitable for cases where memory alignment or readability is a
concern. Unpacked structs are particularly useful in high-level simulations and
verification environments, where the size and alignment of data elements matter
more than memory efficiency.
Unpacked structs in SystemVerilog are defined similarly to packed structs, but
they don’t use the packed keyword. The members of an unpacked struct are
typically aligned based on their data type, which can introduce gaps or padding to
ensure proper alignment. This makes unpacked structs ideal for representing real-
world data structures that require proper alignment for efficient memory access
or interfacing with hardware. Unpacked structs provide a clear, readable layout
with more control over how the data is accessed in a simulation environment.
One of the main uses of unpacked structs is in modeling more complex data
structures that do not need to be packed into a tightly bound memory space. For
example, an unpacked struct can represent different components of a system, such
as registers, control signals, or configurations, where each element may have
different data types and sizes. The freedom to have padding between members
allows designers to more closely model the behavior of real-world hardware,
especially in situations where precise alignment of data is critical for correct
operation.
Another advantage of unpacked structs is their ability to support arrays and
dynamic arrays as members. Unlike packed structs, which typically restrict the
use of arrays to a simple packed structure, unpacked structs can easily contain
arrays of varying lengths or multidimensional arrays. This flexibility makes
unpacked structs suitable for representing more complex data, like arrays of
control registers or status values, which can grow or change in size depending on
the design requirements. It allows for more dynamic and adaptable modeling.
While unpacked structs are not as memory-efficient as packed structs, they
provide a more convenient way to model real-world, non-bit-level data structures.
They are especially useful in verification and simulation contexts where the focus
is on functional behavior rather than precise memory layout. Unpacked structs
can also be randomized and constrained, which is essential for creating effective
testbenches.
5
Conclusion :
In conclusion, EDA Playground is a powerful tool for digital designers and
students, offering an accessible platform to experiment with hardware description
languages like Verilog, VHDL, and SystemVerilog. Its cloud-based nature allows
users to write, simulate, and share code without needing to install heavy software,
making it perfect for quick prototyping and learning. The platform’s user-friendly
interface ensures that both beginners and professionals can take advantage of its
features with ease.
The ability to integrate multiple simulation engines, like ModelSim and XSIM,
further enhances EDA Playground's versatility, providing users with the freedom
to choose the tools that best suit their needs. It also fosters a collaborative
environment where users can share their projects and learn from one another,
creating a community of digital design enthusiasts. This collaborative feature
makes it an ideal space for educational purposes and industry professionals alike.
Overall, EDA Playground serves as an invaluable resource for anyone working in
digital design and verification. It simplifies the process of exploring and testing
hardware designs, enabling faster development cycles and better learning
outcomes. Whether you're a student learning the basics or a professional testing
complex systems, EDA Playground provides the tools to make the process more
efficient and engaging.
6
References :
https://verificationguide.com/systemverilog/systemverilog-tutorial.
Spear, C., SystemVerilog for Verification – A Guide to Learning the
Testbench Language, 2nd ed., Springer, 2010.
