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HEF4013B Dual D-type Flip-Flop Data Sheet

Cmos d type flip flop

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0% found this document useful (0 votes)
51 views14 pages

HEF4013B Dual D-type Flip-Flop Data Sheet

Cmos d type flip flop

Uploaded by

mo.salah.sol1976
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

HEF4013B

Dual D-type flip-flop


Rev. 12 — 24 July 2024 Product data sheet

1. General description
The HEF4013B is a dual D-type flip-flop with set and reset; positive-edge trigger. Inputs include
clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VDD. Schmitt-trigger action on the clock input makes the circuit highly tolerant of slower
clock rise and fall times.

2. Features and benefits


• Wide supply voltage range from 3.0 V to 15.0 V
• CMOS low power dissipation
• High noise immunity
• Tolerant of slow clock rise and fall times
• Fully static operation
• 5 V, 10 V, and 15 V parametric ratings
• Standardized symmetrical output characteristics
• Specified from -40 °C to +125 °C
• Complies with JEDEC standard JESD 13-B
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

3. Applications
• Counters and dividers
• Registers
• Toggle flip-flops

4. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
HEF4013BT -40 °C to +125 °C SO14 plastic small outline package; 14 leads; SOT108-1
body width 3.9 mm
HEF4013BTT -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; SOT402-1
14 leads; body width 4.4 mm
Nexperia HEF4013B
Dual D-type flip-flop

5. Functional diagram

6
1SD
SD
5 1
1D D Q 1Q

FF1
3 2
1CP CP Q 1Q
CD
4
1CD
8
2SD
SD
9 13
2D D Q 2Q

FF2
11 12
2CP CP Q 2Q
CD
10
2CD
001aag084

Fig. 1. Functional diagram

CP C

C Q
C C

C
C
C C

D
Q

C C

SD

CD

aaa-035288

Fig. 2. Logic diagram (one flip-flop)

HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 12 — 24 July 2024 2 / 14


Nexperia HEF4013B
Dual D-type flip-flop

6. Pinning information

6.1. Pinning

T package
SOT108-1 (SO14)

1Q 1 14 VDD TT package
SOT402-1 (TSSOP14)
1Q 2 13 2Q

1CP 3 12 2Q 1Q 1 14 VDD
1Q 2 13 2Q
1CD 4 11 2CP
1CP 3 12 2Q
1D 5 10 2CD 1CD 4 11 2CP
1D 5 10 2CD
1SD 6 9 2D
1SD 6 9 2D
VSS 7 8 2SD VSS 7 8 2SD

aaa-039618 aaa-039634

6.2. Pin description


Table 2. Pin description
Symbol Pin Description
1Q, 2Q 1, 13 true output
1Q, 2Q 2, 12 complement output
1CP, 2CP 3, 11 clock input (LOW to HIGH edge-triggered)
1CD, 2CD 4, 10 asynchronous clear-direct input (active HIGH)
1D, 2D 5, 9 data input
1SD, 2SD 6, 8 asynchronous set-direct input (active HIGH)
VSS 7 ground (0 V)
VDD 14 supply voltage

7. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition.
Control Input Output
nSD nCD nCP nD nQ nQ
H L X X H L
L H X X L H
H H X X H H
L L ↑ L L H
L L ↑ H H L

HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 12 — 24 July 2024 3 / 14


Nexperia HEF4013B
Dual D-type flip-flop

8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage -0.5 +18 V
IIK input clamping current VI < -0.5 V or VI > VDD + 0.5 V - ±10 mA
VI input voltage -0.5 VDD + 0.5 V
IOK output clamping current VO < -0.5 V or VO > VDD + 0.5 V - ±10 mA
II/O input/output current - ±10 mA
IDD supply current - 50 mA
Tstg storage temperature -65 +150 °C
Tamb ambient temperature -40 +125 °C
Ptot total power dissipation Tamb = -40 °C to +125 °C [1] - 500 mW
P power dissipation per output - 100 mW

[1] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C.
For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C.

9. Recommended operating conditions


Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 3 15 V
VI input voltage 0 VDD V
Tamb ambient temperature -40 +125 °C
Δt/ΔV input transition rise and fall rate nCP, nCD, nD, nSD inputs
VDD = 5 V - 3.75 μs/V
VDD = 10 V - 0.5 μs/V
VDD = 15 V - 0.08 μs/V

HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 12 — 24 July 2024 4 / 14


Nexperia HEF4013B
Dual D-type flip-flop

10. Static characteristics


Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit
Min Max Min Max Min Max Min Max
VIH HIGH-level |IO| < 1 μA 5V 3.5 - 3.5 - 3.5 - 3.5 - V
input voltage 10 V 7.0 - 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - 11.0 - V
VIL LOW-level input |IO| < 1 μA 5V - 1.5 - 1.5 - 1.5 - 1.5 V
voltage 10 V - 3.0 - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 - 4.0 V
VOH HIGH-level |IO| < 1 μA 5V 4.95 - 4.95 - 4.95 - 4.95 - V
output voltage 10 V 9.95 - 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - 14.95 - V
VOL LOW-level |IO| < 1 μA 5V - 0.05 - 0.05 - 0.05 - 0.05 V
output voltage 10 V - 0.05 - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 - 0.05 V
IOH HIGH-level VO = 2.5 V 5V - -1.7 - -1.4 - -1.1 - -1.1 mA
output current VO = 4.6 V 5V - -0.64 - -0.5 - -0.36 - -0.36 mA
VO = 9.5 V 10 V - -1.6 - -1.3 - -0.9 - -0.9 mA
VO = 13.5 V 15 V - -4.2 - -3.4 - -2.4 - -2.4 mA
IOL LOW-level VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA
output current VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA
VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA
II input leakage 15 V - ±0.1 - ±0.1 - ±1.0 - ±1.0 μA
current
IDD supply current all valid input 5V - 1.0 - 1.0 - 30 - 30 μA
combinations; 10 V - 2.0 - 2.0 - 60 - 60 μA
|IO| = 0 A
15 V - 4.0 - 4.0 - 120 - 120 μA
CI input - - - - 7.5 - - - - pF
capacitance

HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 12 — 24 July 2024 5 / 14


Nexperia HEF4013B
Dual D-type flip-flop

11. Dynamic characteristics


Table 7. Dynamic characteristics
Tamb = 25 °C, unless otherwise specified. For test circuit see Fig. 5.
Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit
tPHL HIGH to LOW nCP to nQ, nQ; 5V [1] 83 + 0.55 × CL - 110 220 ns
propagation delay see Fig. 3 10 V 34 + 0.23 × CL - 45 90 ns
15 V 22 + 0.16 × CL - 30 60 ns
nSD to nQ 5V [1] 73 + 0.55 × CL - 100 200 ns
10 V 29 + 0.23 × CL - 40 80 ns
15 V 22 + 0.16 × CL - 30 60 ns
nCD to nQ 5V [1] 73 + 0.55 × CL - 100 200 ns
10 V 29 + 0.23 × CL - 40 80 ns
15 V 22 + 0.16 × CL - 30 60 ns
tPLH LOW to HIGH nCP to nQ, nQ; 5V [1] 68 + 0.55 × CL - 95 190 ns
propagation delay see Fig. 3 10 V 29 + 0.23 × CL - 40 80 ns
15 V 22 + 0.16 × CL - 30 60 ns
nSD to nQ 5V [1] 48 + 0.55 × CL - 75 150 ns
10 V 24 + 0.23 × CL - 35 70 ns
15 V 17 + 0.16 × CL - 25 50 ns
nCD to nQ 5V [1] 33 + 0.55 × CL - 60 120 ns
10 V 19 + 0.23 × CL - 30 60 ns
15 V 12 + 0.16 × CL - 20 40 ns
tt transition time see Fig. 3 5V [1] 10 + 1.00 × CL - 60 120 ns
10 V 9 + 0.42 × CL - 30 60 ns
15 V 6 + 0.28 × CL - 20 40 ns
tsu set-up time nD to nCP; see Fig. 3 5 V 40 20 - ns
10 V 25 10 - ns
15 V 15 5 - ns
th hold time nD to nCP; see Fig. 3 5 V 20 0 - ns
10 V 20 0 - ns
15 V 15 0 - ns
tW pulse width nCP input LOW; 5V 60 30 - ns
see Fig. 3 10 V 30 15 - ns
15 V 20 10 - ns
nSD input HIGH; 5V 50 25 - ns
see Fig. 4 10 V 24 12 - ns
15 V 20 10 - ns
nCD input HIGH; 5V 50 25 - ns
see Fig. 4 10 V 24 12 - ns
15 V 20 10 - ns

HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 12 — 24 July 2024 6 / 14


Nexperia HEF4013B
Dual D-type flip-flop

Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit
trec recovery time nSD input; see Fig. 4 5V +15 -5 - ns
10 V 15 0 - ns
15 V 15 0 - ns
nCD input; see Fig. 4 5V 40 25 - ns
10 V 25 10 - ns
15 V 25 10 - ns
fclk(max) maximum clock see Fig. 3 5V 7 14 - MHz
frequency 10 V 14 28 - MHz
15 V 20 40 - MHz

[1] Typical values of the propagation delays and output transition times can be calculated with the extrapolation formulas (CL in pF).

Table 8. Dynamic power dissipation


VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol Parameter VDD Typical formula Where
2
PD dynamic power dissipation 5 V PD = 850 × fi + Σ(fo × CL) × VDD μW fi = input frequency in MHz;
10 V PD = 3600 × fi + Σ(fo × CL) × VDD μW
2 fo = output frequency in MHz;
2
CL = output load capacitance in pF;
15 V PD = 9000 × fi + Σ(fo × CL) × VDD μW Σ(fo × CL) = sum of the outputs;
VDD = supply voltage in V.

11.1. Waveforms and test circuit


1/fclk(max) tW
VI

input nCP VM

0V
tsu tsu
tf tr
th th
VI

input nD VM

0V
tPLH tPHL
tt tt
VOH
VY
output nQ VM

VOL VX
001aah016

Set-up and hold times are shown as positive values but may be specified as negative values.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Measurement points are given in Table 9.
Fig. 3. Set-up time, hold time, minimum clock pulse width, propagation delays and transition times

HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 12 — 24 July 2024 7 / 14


Nexperia HEF4013B
Dual D-type flip-flop

VI
input nCP VM
0V
trec trec
VI
input nSD VM
0V tW
VI
input nCD VM
0V tW
VOH
output nQ
VOL 001aag088

Recovery times are shown as positive values but may be specified as negative values.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Measurement points are given in Table 9.
Fig. 4. nSD, nCD recovery time and pulse width

Table 9. Measurement points


Supply voltage Input Output
VDD VM VM VX VY
5 V to 15 V 0.5VDD 0.5VDD 0.1VDD 0.9VDD

VDD

VI VO
G DUT

RT CL

001aag182

Test and measurement data is given in Table 10;


Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator;
CL = Load capacitance including jig and probe capacitance.
Fig. 5. Test circuit for measuring switching times

Table 10. Test data


Supply voltage Input Load
VDD VI tr, tf CL
5 V to 15 V VSS or VDD ≤ 20 ns 50 pF

HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 12 — 24 July 2024 8 / 14


Nexperia HEF4013B
Dual D-type flip-flop

12. Application information

D D Q D Q D Q Q

FF FF FF
1 2 n

CP Q CP Q CP Q

clock 001aag089

Fig. 6. N-stage shift register

D Q D Q D Q Q

FF FF FF
1 2 n

clock CP Q CP Q CP Q

T-type flip-flop 001aag090

n
Fig. 7. Binary ripple up-counter; divide-by-2

D Q D Q D Q Q

FF FF FF
1 2 n

CP Q CP Q CP Q

clock

001aag091

Fig. 8. Modified ring counter; divide-by-(n + 1)

HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 12 — 24 July 2024 9 / 14


Nexperia HEF4013B
Dual D-type flip-flop

13. Package outline


SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

D E A
X

c
y HE v M A

14 8

A2
A3 A
A1
pin 1 index
θ
Lp

1 7 L

e w M detail X
bp

0 5 mm
scale

Dimensions (inch dimensions are derived from the original mm dimensions)

Unit A A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y θ

max 1.75 0.25 0.51 0.25 8.75 4.0 6.2 1.27 8°


mm nom 0.25 1.27 1.05 0.2 0.25 0.1
min 0.10 1.25 0.31 0.10 8.55 3.8 5.8 0.4 0°
max 0.069 0.010 0.020 0.010 0.344 0.16 0.244 0.05 8°
inches nom 0.01 0.05 0.041 0.008 0.01 0.004
min 0.004 0.049 0.012 0.004 0.337 0.15 0.228 0.016 0°
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. sot108-1_po

Outline References European


Issue date
version IEC JEDEC JEITA projection
03-02-19
SOT108-1 MS-012
23-10-27

Fig. 9. Package outline SOT108-1 (SO14)

HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 12 — 24 July 2024 10 / 14


Nexperia HEF4013B
Dual D-type flip-flop

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

D E A
X

y HE v M A

14 8

A2 A3
A
A1
pin 1 index

θ
Lp
L
1 7
detail X
w M
e bp

0 5 mm

scale

Dimensions (mm are the original dimensions)

Unit A A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y θ


max 1.20 0.15 1.05 0.30 0.2 5.1 4.5 6.6 0.75 8°
mm nom 0.25 0.65 1 0.2 0.1 0.1
min 0.05 0.80 0.19 0.09 4.9 4.3 6.2 0.45 0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. sot402-1_po

Outline References European


Issue date
version IEC JEDEC JEITA projection
03-02-18
SOT402-1 MO-153
23-10-27

Fig. 10. Package outline SOT402-1 (TSSOP14)

HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 12 — 24 July 2024 11 / 14


Nexperia HEF4013B
Dual D-type flip-flop

14. Abbreviations
Table 11. Abbreviations
Acronym Description
ANSI American National Standards Institute
CDM Charged Device Model
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
ESDA ElectroStatic Discharge Association
HBM Human Body Model
JEDEC Joint Electron Device Engineering Council

15. Revision history


Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4013B v.12 20240724 Product data sheet - HEF4013B v.11
Modifications: • Section 2: ESD specification updated according to the latest JEDEC standard.
• Fig. 9, Fig. 10: Aligned SO and TSSOP package outline drawings to JEDEC MS-012
and MO-153
HEF4013B v.11 20230309 Product data sheet - HEF4013B v.10
Modifications: • Section 1 updated
• Fig. 2: Schmitt-trigger symbol removed (errata).
HEF4013B v.10 20211123 Product data sheet - HEF4013B v.9
Modifications: • The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
• Section 1 and Section 2 updated.
• Table 4: Derating values for Ptot total power dissipation updated.
HEF4013B v.9 20151210 Product data sheet - HEF4013B v.8
Modifications: • Type number HEF4013BP (SOT27-1) removed.
HEF4013B v.8 20111121 Product data sheet - HEF4013B v.7
Modifications: • Legal pages updated.
• Changes in "General description", "Features and benefits" and "Applications".
HEF4013B v.7 20110913 Product data sheet - HEF4013B v.6
HEF4013B v.6 20091027 Product data sheet - HEF4013B v.5
HEF4013B v.5 20090619 Product data sheet - HEF4013B v.4
HEF4013B v.4 20080515 Product data sheet - HEF4013B_CNV v.3
HEF4013B_CNV v.3 19950101 Product specification - HEF4013B_CNV v.2
HEF4013B_CNV v.2 19950101 Product specification - -

HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 12 — 24 July 2024 12 / 14


Nexperia HEF4013B
Dual D-type flip-flop
injury, death or severe property or environmental damage. Nexperia and its

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such equipment or applications and therefore such inclusion and/or use is at
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Quick reference data — The Quick reference data is an extract of the
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document, and as such is not complete, exhaustive or legally binding.
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[1][2] status [3] products are for illustrative purposes only. Nexperia makes no representation
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data sheet the objective specification for without further testing or modification.
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and products using Nexperia products, and Nexperia accepts no liability for
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HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 12 — 24 July 2024 13 / 14


Nexperia HEF4013B
Dual D-type flip-flop

Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................1
5. Functional diagram.......................................................2
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description............................................................. 3
7. Functional description................................................. 3
8. Limiting values............................................................. 4
9. Recommended operating conditions..........................4
10. Static characteristics..................................................5
11. Dynamic characteristics.............................................6
11.1. Waveforms and test circuit........................................ 7
12. Application information............................................. 9
13. Package outline........................................................ 10
14. Abbreviations............................................................ 12
15. Revision history........................................................12
16. Legal information......................................................13

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Date of release: 24 July 2024

HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. All rights reserved

Product data sheet Rev. 12 — 24 July 2024 14 / 14

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