Introduction to
EE303 Digital System Design
Youngsoo Shin
KAIST
Fall 2025
EE303
• Lectures: 2:30pm~4pm on Tue/Thu
– Classroom lecture (recorded video whenever the instructor has a
schedule conflict, potentially on 9/9 ~ 9/30)
• Instructor: Prof. Youngsoo Shin (신영수)
• TA: 김경진, 김서현, 김태영, 김희상, 고민정, 김민재, 박선우, 임경록
EE building E3-2,
#5219
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EE303
• Course web page:
http://klms.kaist.ac.kr/
• Textbook: Fundamentals of Logic Design,
7th Ed.
– Older editions are also ok, but reference (e.g.
problems) will be based on 7th edition
– Lecture note sometimes contains materials
not in your textbook, which should be
considered equally important
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Chapters We Will Cover
• 1: Number systems
• 2 & 3: Boolean algebra Stores numbers (010 for 2) or
• 4: Minterm and maxterm expansions symbols (010 for red; 101 for ADD)
• 5: Karnaugh maps
• 6: Quine-McCluskey method
• 7: Multi-level circuits, NAND/NOR gates Memory
• 8: Combinational circuit design
• 9: Multiplexers, decoders, and PLDs
• 10: Introduction to VHDL Control
• 11: Latches and flip-flops
Unit
• 12: Registers and counters Functional
• 13: Analysis of clocked sequential circuits Unit
• 14: Derivation of state graphs and tables
• 15: State minimization & state encoding
• 16: Sequential circuit design
• 17: VHDL for sequential logic
Governing mathematics:
• 18: Circuits for arithmetic operations
Boolean Algebra
• 19: State machine design with SM charts
• 20: VHDL for digital system design
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Grading
• Attendance: 5%
• Lab: 10%
• Homework: 20%
• Midterm exam: 30% (Oct. 23rd)
• Final exam: 35% (Dec. 18th)
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Homework
• There will be 6 HW assignments
– Posted at course webpage
– Have to be turned in through KLMS by 10pm on the day
they are due (HWs that are turned in late will NOT be
accepted)
• Academic dishonesty
– HW must be done by yourself (even though you may
“discuss” with your classmates)
– Any cheating (e.g. identical HW) will be penalized with 0
points on that assignment
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Labs
• You will perform a set of 3 labs & turn in a report for
each (through KLMS)
– Design of an example digital IC: “Verilog” coding (Lab1)
and test input generation using LLMs (Lab2)
– Logic- & physical-synthesis through OpenLane flow and
tools (Lab3, https://github.com/The-OpenROAD-Project/OpenLane)
– All will be done right on your computer
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HWs, Labs, Exams: Schedule
Why Digital Systems?
• They are everywhere these days
– Cell phones, PCs, tablets, digital cameras, digital TVs
– ABS, airbags, aircraft controllers and navigators, robotic
arms, ATMs, credit card readers, home security systems
– Computer networks, modems, scanners, photocopiers
– Hearing aids, pacemakers, ventilators
• Digital system is central in
– Big data (e.g. google, facebook, twitter, instagram, linkedin,
kakao talk), AI (e.g. siri, Watson, TensorFlow, AlphaGo)
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Why “Digital Integrated Circuits”?
• Recent trend
– Digital devices are getting smaller & slimmer
– They are getting faster
– More functions are integrated (e.g. cell phone:
phone call, SMS, internet, mp3, game, now almost
PC!)
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Digital IC Design
11, 12
14
1, 18, 9, 16
Design using HDL
2&3, 4, 5, 6,
Logic 7, 8, 13, 15
Synthesis
Physical
Synthesis
Layout Not covered here, Netlist
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Covered in EE574
