MUTHAYAMMAL COLLEGE OF ARTS AND SCIENCE, (Autonomous)

RASIPURAM-637408
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Balakrishnan, M.Sc., M.Phil.,

Staff Name: I.Balakrishnan, Class: III-B.Sc (E&C) Paper Code: 19UELE01
19UEL

ler and interfacing

Paper Name: 8051 Microcontroller Unit: I
UNIT-I : 8051 Microcontroller
Definition of Microcontroller:
A microcontroller is a chip optimized to control electronic devices. It is stored in a single
integrated circuit which is dedicated to performing
performing a particular task and execute one specific
application.
Simply a microcontroller is a complete microcomputer system built in a single integrated circuit
for a specific application.
Comparison of Microprocessors and Microcontrollers:
S.No Microproces
Microprocessor Microcontroller
Microprocessor is the heart of Computer Micro Controller is the heart of an embedded
1
system. system.
It is only a processor, so memory and I/O Micro Controller has a processor along with
2
components need to be connected externally internal memory and I/O components.
Memory and I/O has to be connected Memory and I/O are already present, and the
3
externally, so the circuit becomes large. internal circuit is small.
4 You can’t use it in compact systems You can use it in compact systems.
syst
5 Cost of the entire system is high Cost of the entire system is low
Power Consumption is high due to external Power consumption is low due to internal
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components components
Most of the microprocessors do not have Most of the microcontrollers offer power-
power
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power saving features. saving mode.
It is used mainly in a washing machine, MP3
8 It is mainly used in personal computers.
players, and embedded systems.
Microprocessor has a smaller number of
Microcontroller has more register. Hence the
9 registers, so more operations are memory-
memory
programs are easier to write.
based.
Microprocessors are based on Von Neumann Micro controllers are based on Harvard
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model architecture
It has no RAM, ROM, Input-Output
Output units, It has a CPU along with RAM, ROM, and other
11
timers, and other peripherals on the
t chip. peripherals embedded on a single chip.
It uses an external bus to interface to RAM,
12 It uses an internal controlling bus.
ROM, and other peripherals.
Microprocessor-based
based systems can run at a Microcontroller based systems run up to
13 very high speed because of the technology 200MHz or more depending on the
involved. architecture.

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 It’s complex and expensive, with a large It’s simple and inexpensive with less number of
14
number of instructions to process. instructions to process.
Features of 8051 Microcontroller:
8-bit CPU optimized for control applications.
4K bytes of on-chip Program Memory(ROM)
128 bytes of on-chip Data Memory (RAM)
64K External Program Memory / Data Memory address space
32 bidirectional and individually addressable I/O lines
Two 16-bit Timer/Counters
A full duplex Serial Port (UART)
5-vector interrupt structure with two priority levels
On-chip clock oscillator.
Power full Instruction set.
40 Pin DIP IC with the operating voltage of +5V DC.
Pin Diagram of 8051:
The 8051 is packaged in a 40-pin DIP.
The Figure shows the pin diagram of 8051. It is important to note that many pins of 8051 are
used for more than one function.
The alternative functions of pins are shown in brackets.
The 8051 has 32 I/O pins configured as four eight-bit parallel ports (PO, P1, P2 and P3).
All the four ports are bidirectional i.e. each pin will be configured as input or output (or both).
All port-pins are multiplexed except the pins of
Port1.
Each port consists of a latch, an output driver
and an input buffer.
Port o (Pins 32 - 39):
Port 0 pins can be used as I/O pins.
The output drives and input buffers of port 0 are
used to access external memory.
Port 0 outputs the low order byte of the external
memory address, time multiplexed with the data
being written or read.
Thus, port 0 can be used as a multiplexed
address/data bus.
Port 1 (Pins 1 - 8):
Port 1 pins can be used only as I/O pins.
Port 2 (Pins 21 - 28):
The output drives of port 2 are used to access
external memory.
Port 2 outputs the high order byte of the
external memory address when the address is
Figure 1( Pin Details od 8051)
16 bits wide.
Otherwise, port 2 is used as an I/O port.
Port 3 (Pins 10 - 17):
All port pins of port 3 are multifunctional.

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 Therefore, each pin of port 3 can be programmed to use as I/O or as one of the alternate
function.
They have special functions as shown below including two external interrupts, two counter
inputs, two special data lines and two timing control strobes.
Pin Signal Alternate Function
P3.0 RXD Receive Serial Data
P3.1 TXD Transmit Serial Data
P3.2 0 External Hardware Interrupt 0
P3.3 1 External Hardware Interrupt 1
P3.4 T0 Timer 0 Clock Input
P3.5 T1 Timer 1 Clock Input
P3.6 Write Strobe for external memory
P3.7 Read Strobe for external memory
Power-supply :
Pins Vcc (Pin 40) and GND (Pin 20).
8051 operates on DC power supply of +5 V with respect to ground.
The +5 V is to be connected to pin +VCC and ground to pin GND with rated power supply
current of 125 mA.
Oscillator:
Pins XTAL2 (Pin 18) and XTAL1 (Pin 19).
For generating an internal clock signal, the external oscillator is connected at these two pins.
ALE (Pin 30):
ALE-Address Latch Enable.
AD0 to AD7 lines are multiplexed for lower order address and Data.
To demultiplex these lines and for obtaining lower half of an address, an external latch and
ALE signal of 8051 is used.
RST (Pin 9):
RST- Reset input.
This pin is used to reset 8051.
For proper reset operation, reset signal must be held high at least for two machine cycles,
while oscillator is running.
(Pin 29):
-Program Store Enable,
It is the active low output control signal used to activate the enable signal of the external ROM/
EPROM.
It is activated every six oscillator periods while reading the external memory.
Thus, this signal acts as the read strobe to external program memory.
(Pin 31):
: External Access.
When the pin is high (connected to VCC), program fetches to addresses 0000H through
OFFFH are directed to the internal ROM and program fetches to addresses 1000H through
FFFFH are directed to external ROM/EPROM.
When is low (grounded), all addresses (0000H to FFFFH) fetched by program are directed
to the external ROM/EPROM.

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Architecture of 8051:
The Figure shows the internal block diagram of 8051. It consists of a CPU, data memory - RAM
and program memory - EPROM/ROM, Input/ Output ports, special function registers and
control logic needed for a timer / counter serial port and interrupt functions.
These elements communicate through an eight bit data bus which runs throughout the chip
referred as internal data bus.
This bus is buffered to the outside world through an I/O port when memory or I/O expansion
is desired.

Figure 2( Internal Architecture of 8051)

Central Processing Unit (CPU):

The CPU of 8051 consists of eight-bit arithmetic and logic unit with associated registers like A,
B, PSW, SP, the sixteen bit program counter and “Data pointer” (DPTR) registers.
Along with these registers it has a set of special function registers.
The unique feature of the 8051 architecture is that the ALU can also manipulate one bit as well
as eight-bit data types.
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A and B- CPU Registers
Register A (Accumulator):
It is an 8-bit register called accumulator.
It holds a source operand and receives the result of the arithmetic instructions (addition,
subtraction, multiplication and division).
Several functions apply exclusively to the accumulator such as Rotate, parity computation,
testing for zero and so on.
Register B:
In addition to accumulator, an 8-bit B-register is available as a general purpose register.
It is used for the hardware multiply/divide operation.
Data Pointer (DPTR):
The data pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL).
Its function is to hold a 16-bit address of external data memory.
It may be manipulated as a 16-bit data register or as two independent 8-bit registers.
It serves as a Memory base register in indirect jumps, lookup table Address instructions and
external data transfer.
The DPTR does not have a single internal address; DPH (83H) and DPL (82H) have separate
internal addresses.
The Program Counter:
The 8051 has a 16-bit program counter.
It is used to hold the address of memory location from which the next instruction is to be
fetched.
8051 Flag Bits and the PSW Register:
The Figure shows the bit pattern of program status word (PSW) of 8051.
PSW is also known as flag register.
There are instructions in 8051, that tests the condition of flags in the PSW register and make
decision based on the status of flags.
Thus, programmer uses these flags to perform some arithmetic operations which involves
carry or borrow, or to change the program control (using conditional branching).
The programmer can select register bank by setting corresponding bits in PSW.

PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0

CY AC F0 RS1 RS2 OV - P

CY-Carry Flag :
This flag is set if there is an overflow out of bit 7.
The carry flag also serves as a borrow flag for subtraction.
AC-Auxiliary Carry Flag:
This flag is set if there is an overflow out of bit 3 i.e., carry from lower nibble to higher nibble
(D3 bit to D4 bit).
This flag is set while BCD operations take place in ALU.
FO- User Defined Flag:
Available for user for general purpose.
RS1 - RSO (Register Bank Select) :
They select the working register bank as follows:
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 RS1 RSO Bank Selection
0 0 00H - 07H Bank 0
0 1 08H - 0FH Bank 1
1 0 10H - 17H Bank 2
1 1 18H - 1FH Bank 3
OV-Over Flow Flag:
This flag is set whenever the result of a signed number operation is too large, causing the high-
order bit to overflow into the sign bit.
P-Parity Flag:
Parity is defined by the number of 1’s present in the accumulator.
P = 0, if number of 1’s are even and P = 1, if number of 1’s are odd.
Example :
The status of CY, AC and P flags after the addition of
9BH and 65H is as follows:
CY = 1, AC = 1 and P = 0
Stack Pointer (SP):
The Stack Pointer Register is 8 bits wide.
It is incremented before data is stored during PUSH and CALL executions.
While the stack may reside anywhere in on chip RAM, the Stack Pointer is initialized to 07H
after a reset.
This causes the stack to begin at location 08H.
Ports 0 TO 3:
P0,Pl, P2 andP3 are the SFR latches of Ports 0,1,2 and 3, respectively.
Serial Data Buffer:
The Serial Data Buffer actually two separate registers, a transmit buffer and a receive buffer
register.
When a data is moved to SBUF, it goes to the transmit buffer where it is held for serial
transmission. (Moving a byte to SBUF is what initiate a the transmission.)
When data is moved from SBUF, it comes from the receive buffer.
Timer/Counters:
There are two 16-bit timer/counters are available.
Register pairs (TH0, TL0), (TH1, TL1) are the 16-bit Counting registers for Timer/Counters 0
and 1 respectively.
Control Registers:
Special Function Registers IP, IE, TMOD, TCON, SCON and PCON contain control and status bits
for the interrupt system, the Timer/Count and the serial port. They are described in later
sections.
Memory Organization:
The 8051 devices have separate address space for Program and Data Memory, as shown in
Figure.
The logical separation of Program and Data Memory allows the Data Memory to be accessed
by 8-bit address, which can be more quickly stored and manipulated by an 8-bit CPU.
Nevertheless, 16-bit Data Memory addresses can also be generated through the DPTR register.
Program Memory can only be read, not written to.
There can be up to 64K bytes of Program Memory.
In the ROM of these devices the lowest 4K bytes of Program Memory are provided on-chip.

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 The read strobe for external Program Memory is the signal PSEN (Program Store Enable).
Data Memory occupies a separate address space from Program memory.
Up to 64K bytes of external RAM can be addressed in the external Data Memory.
The CPU generates a read and write signals and as needed during external Data
Memory accesses.

Figure 3(Logical Separation of Memory)

External Program Memory and external Data Memory combined if-desired by applying the
signals to the inputs of an AND gate and using the output of the gate as the read strobe
to the external Program/Data memory.
Program Memory:
The Figure shows a map of the
lower part of the Program Memory.
After reset, the CPU begins
execution from location 0000H.
As shown in Figure, each interrupt
is assigned a fixed location in
Program Memory.
The interrupt causes the CPU to
jump to that location, where it
commences execution of the service
routine. Figure 4(Structure of ROM)

External Interrupt 0, for example, is assigned to location 0003H.

If External Interrupt 0 is going to be used, its service routine must begin at location 0003H.
If the interrupt is not going to be used, its service location is available as general purpose
Program Memory.
The interrupt service locations are spaced at 8-byte internal 0003H for External Interrupt 0,
000BH for Timer 0, 0013H for External Interrupt 1, 001BH for Timer 1, etc.

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 If an interrupt service routine is short enough (as is often the case in control applications), it
can reside entirely within that 8-byte interval.
Longer service routines can use a jump instruction to skip over subsequent interrupt
locations, if other interrupts are in use.
The lowest 4K bytes of Program Memory can be either in the on-chip ROM or in an external
ROM.
This selection is made by strapping the (External Access) pin to either VCC or VSS.
In the 4K byte ROM devices, if the pin is strapped to VCC, then program fetches to addresses
0000H through 0FFFH are directed to the internal ROM and Program fetches to addresses
1000H through FFFFH are directed to external ROM.
If the pin is strapped to VSS, then all program fetches are directed to external ROM.
The read strobe to external ROM, is used for all external program fetches. is not
activated for internal program fetches.
Data Memory:

Figure 5 (Data Memory Organization)

Internal RAM Organization:
The 8051 has 128-byte internal RAM.
It is accessed using RAM address register.
The figure shows the internal RAM organized into three distinct areas as follows
1. Register Bank (00-1F)
2. Bit addressable(20-2F)
3. General purpose(30-7F)
1. Register Banks (Working Registers)
RS1 RSO Bank Selection
The first 32-bytes from address 00H to 1FH of internal
RAM constitute 32 working registers. 0 0 00H - 07H Bank 0
They are organized into four banks of eight registers 0 1 08H - 0FH Bank 1
each. 1 0 10H - 17H Bank 2
The four register banks are numbered 0 to 3 and are 1 1 18H - 1FH Bank 3
consists of eight registers named Ro to R7
Each register can be addressed by name or by its RAM address.
Only one register bank is in use at a time. Bits RSO and RS1 in the PSW determine which bank
of registers is currently in use.
On reset, the bank 0 is selected and hence it is a default register bank.
Register banks when not selected can be used as general purpose RAM.

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2. Bit / Byte Addressable RAM:
The 8051 provides 16 bytes of a bit-addressable area.
It occupies RAM byte addresses from 20H to 2FH, forming a total of 128 (16 x 8 addressable
bits.
An addressable bit may be specified by its bit address of 00H to 7FH, or 8 bits may form any
byte address from 20H to 2FH.
For example, bit address 4EH refers bit 6 of the byte address 29H.
3. General Purpose RAM
The RAM area above bit addressable area from 30H to 7FH is called general purpose RAM.
It is addressable as byte.
It is also known as scratch pad memory.

Figure 6(Internal RAM Organization)

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Power-ON Reset:
For HMOS devices when VCC is turned on an
automatic reset can be obtained by connecting the
RST pin to VCC through a 10pF capacitor and to VSS
through an 8.2 KΩ resistor.
The CHMOS device does not require this resistor
although its presence does no harm.
In fact, for CHMOS devices the external resistor can
be removed because they have an internal pull
down on the RST pin.
The capacitor value could then be reduced to 1 pF.
When power is turned on, the circuit holds the RST
pin high for an amount of time that depends on the
capacitor value and the rate at which it charges. Figure 7 (Power on Reset)
To ensure valid reset the RST pin must be held high long enough to allow the oscillator to start
up plus two machine cycles.
On power up, VCC should rise within approximately ten milli seconds.
The oscillator start-up time will depend on the oscillator frequency.
For a 10MHzcrystal, the start-up time is typically 1ms.
For a 1MHzcrystal, the start-up time is typically 10ms.
With the given circuit reducing VCC quickly to 0 causes the RST pin voltage to momentarily fall
below 0V.
However, this voltage is internally limited and will not harm the device.
Power saving modes of Operation:
For applications where power
consumption is critical the CHMOS
version provides a power reduced
modes of operation as a standard
feature.
There are two power-reducing
modes, Idle and Power Down.
The input through which backup
power is supplied during these
operations is VCC.
The figure shows the internal
circuitry which implements these
features. Figure 8(Logic for Power Saving Mode)
In the Idle mode (IDL = 1), the oscillator continue to run and the Interrupt, Serial Port, and
Timer blocks continue to be clocked, but the clock signal is gated off to the CPU.
In Power Down (PD = 1), the oscillator is frozen.
The Idle and Power Down modes are activated by setting bits in Special Function Register
PCON.
The address of this register is 87H.
User software should never write 1s to unimplemented bits, since they may be used in future
products.
Idle Mode:

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 An instruction that sets PCON.0 causes that to be the last instruction executed before going
into the idle mode.
In the idle mode, the internal clock signal is gated off to the CPU, but not to the Interrupt,
Timer, and Serial Port functions.
The CPU status is preserved in its entirety the Stack Pointer, Program Counter, Program Status
Word, Accumulator, and all other registers maintain their data during Idle.
The port pins hold the logical states they had at the time Idle was activated.
ALE and hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause
PCON.0 to be cleared by hardware.
Terminating the Idle mode The interrupt will be serviced and following RETI the next
instruction to be executed will be the one following the instruction that put the device into
Idle.
The flag bits GF0 and GFI can be used to give an indication of a n interrupt occurred during
normal operation or during an Idle.
For example, an instruction that activates Idle can also set one or both flag bits.
When Idle is terminated by an interrupt, the interrupt service routine can examine the flag
bits.
The other way of terminating the idle mode is with a hardware reset.
Since the clock oscillator is still running the hardware reset needs to be held active for only
two machine cycles (24 oscillator periods) to complete the reset.
The signal at the RST pin clears the IDL bit directly and asynchronously.
At this time the CPU resumes program execution from where it left off; that is, at the
instruction following the one that invoked the Idle Mode.
On-chip hardware inhibits access to the internal RAM during this time, but access to the port
pins is not inhibited.
To eliminate the possibility of unexpected outputs at the port pins, the instruction following
the one that invokes Idle should not be one that writes to a port pin or to external Data RAM.
Power down Mode:
An instruction that set PCON.1 causes that to be the last instruction executed before going
into the Power Down mode.
In the Power Down mode, the on-chip oscillator is stopped.
With the clock frozen, all functions are stopped, but the on-chip RAM and Special Function
Registers are held.
The port pins output the values held by their respective SFRs.
ALE and output lows.
The only exit from Power Down for the 8051 is a hardware reset.
Reset redefines all the SPRs, but does not change the on-chip RAM.
In the Power Down mode of operation, VCC can be reduced to as low as 2V.
Care must be taken, however, to ensure that VCC is not reduced before the Power Down mode
is invoked, and that VCC is restored to its normal operating level, before the Power Down mode
is terminated.
The reset that terminates Power Down also frees the oscillator.
The reset should not be activated before VCC is restored to its normal operating level, and must
be held active long enough to allow the oscillator to restart and stabilize (normally less than
10 ms).
Interrupt Logic:
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The 8051 core provides 5 interrupt sources 2 external interrupts, 2 timer interrupts, and the
serial pat interrupt as follows.
0 - External hardware Interrupt 0.
1 - External hardware Interrupt 1.
TF0 - Timer /Counter 0 interrupt.
TF1 - Timer/Counter 1 Interrupt.
TI (OR) RI - Serial Port Interrupt.

Figure 9( Interrupt Structure)

In operation, all the interrupt flags are latched into the interrupt control system during State 5
of every machine cycle.
The samples are polled during the following machine cycle-.
If the flag for an enabled interrupt is found to be set (l), the interrupt system generates an
LCALL to the appropriate location in Program Memory, unless some other condition blocks
the interrupt.
Several conditions can block an interrupt, among them that an interrupt of equal or higher
priority level is already in progress.
The hardware-generated LCALL causes the contents of the Program Counter to be pushed
onto the stack, and reloads the PC with the beginning address of the service routine.
The service routine for each interrupt begins at a fixed location called Vector location of the
respective interrupts.
Only the Program Counter is automatically pushed onto the stack, not the PSW or any other
register.
Having only the PC be automatically saved allows the programmer to decide how much time
to spend saving which other registers.
This enhances the interrupt response time, albeit at the expense of increasing the
programmer’s burden of responsibility.
As a result, many interrupt functions that are typical in control applications – toggling a port
pin for example, or reloading a timer, or unloading a serial buffer-can often be completed in
less time than it takes other architectures to commence them.
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Timer / Counter Logic:
The 8051 has two timers: Timer 0 and Timer 1.
They can be used either as timers or as event counters.
Both Timer 0 and Timer 1 are 16 bits wide.
Since the 8051 has an 8-bit architecture, each 16-bit timer is accessed as two separate registers
of low byte and high byte.
The “Timer or Counter” function is selected by control bits / in the Special Function
Register TMOD.
These two Timer/Counter have four operating modes which are selected by bit-pairs (M1.
M0) in TMOD.
Modes 0, 1, and 2 are the same for both Timer/Counters.
Mode3 is different. The four operating modes are described in the following text.
Clock source for timer:
As we know, every timer needs a clock pulse to tick.
If / = 0, the crystal frequency attached to the 8051 is the source of the clock for the timer.
This means that the size of the crystal frequency attached to the 8051 also decides the speed at
which the 8051 timer ticks.
The frequency for the timer is always 1/12th the frequency of the crystal attached to the 8051.
Although various 8051-based systems have an XTAL frequency of 10 MHz to 40 MHz, we will
concentrate on the XTAL frequency of 11.0592 MHz.
The reason behind such an odd number has to do with the baud rate for serial communication
of the 8051.
XTAL = 11.0592 MHz allows the 8051 system to communicate with the IBM PC with no errors,
as we will see in Chapter 10.
Mode 0:
The figure shows the Mode0 operation as it applies to Timer 1.
In this mode, the Timer register is configured as a 13-Bit register.
As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TF1.
The counted input is enabled to the Timer when TR1 = 1 and either GATE = O or 1= 1.
Setting GATE = 1 allows the Timer to be controlled by external input 1, to facilitate pulse
width measurements.
TR1 is a control bit in the Special Function Register TCON, GATE is in TMOD.
The 13-Bitregister consists of all 8 bits of TH1 and the lower 5 bits of TL1.
The upper 3 bits of T1l are indeterminate and should be ignored.
Setting the run flag (TR1)does not clear the registers.
Mode0 operation is the same for Timer 0 as for Timer 1, substituteTR0,TF0 and 0 for the
corresponding Timer 1signals in the figure.
There are two different GATE bits one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

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 Figure 10(Mode 0 of Operation)

Mode 1:
Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits.

Figure 11(Mode 1 of Operation)

Mode 2:

Figure 12(Mode2 0f Operation)

Mode2 configure the Timer register as an 8-bit Counter (TL1) with automatic reload, as
shown in the above figure.
Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is
preset by software.
The reload leaves TH1 unchanged
Mode2 operation is the same for Timer/Counter 0.
Mode 3:

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 Timer 1 in Mode3 simply holds its count.
The effect is the same as setting TRl = 0.
Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters.
The logic for Mode3 on Timer O is show in the above figure, TL0 & uses the Timer0 control
bits: / GATE, TR0, 0, and TF0.
TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1
and TF1 from Timer 1.

Figure 13(Mode 3 0f Operation)

Thus TH0 now controls the Timer 1 interrupt.
Mode 3 is provided for applications requiring an extra 8-bit timer or counter.
With Timer 0 in Mode 3, an 8051 can look like it has three Timer/Counter and an
When Timer 0 is in Mode 3. Timer 1 Can be turned on and off by switching it out of and into its
own Mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any
application not requiring interrupt.

Serial Logic:
The serial port is full duplex, meaning it can transmit and receive simultaneously.
It is also receive- buffered, meaning it can commence reception of a second byte before a
previously received byte has been read from the receive register. (However, if the first byte
still hasn’t been read by the time reception of the second byte is complete one of the bytes will
be lost).
The serial port receive and transmit registers are both accessed at Special Function Register
SBUF.
Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate
receive register.
Serial Port Modes of Operations:
M1 M0 Mode Operation
0 0 Mode 0 8 –Bit Shift register mode with fixed Baud rate
0 1 Mode 1 8-Bit UART mode with variable baud rate
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 1 0 Mode 2 9-Bit UART mode with fixed baud rate
1 1 Mode 3 9-Bit UART mode with Variable baud rate

The serial port can operate in 4 modes.

In all four modes, transmission is initiated by any instruction that uses SBUF as a destination
register.
Reception is initiated in Mode0 by the condition RI = 0 and REN = 1.
Reception is initiated in the other modes by the incoming start bit if REN = 1.
Mode 0:
Serial date enters and exits through RXD pin.
TXD outputs the shift clock.
8 bits are transmitted/received as LSB first.
The baud rate is fixed at 1/12 the oscillator frequency.
Mode 1:
10 bits are transmitted through TXD or received through RXD
A start bit (0), 8 data bits (LSB first), and a stop bit (l).
On receive the stop bit goes into RB8 in Special Function Register SCON.
The baud rate is variable.
Mode 2:
11bits are transmitted through TXD or received through RXD
A start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1).
On Transmit, the 9th data bit (TB8 in SCON) can be assigned the value of O or 1.
Or, for example, the parity bit (P, in the PSW) could be moved into TB8.
On receive; the 9th data bit goes into RB8 in Special Functon Register SCON, while the stop bit
is ignored.
The baud rate is programmable to either 1/32 or 1\64 the oscillator frequency.
Mode 3:
11bits are transmitted through TXD or received through RXD.
A start bit (0), 8 data bits (LSB first), a programmable 9th data bit and a stop bit (1).
In fact Mode 3 is same as the Mode 2 in all aspects except the baud rate.
The baud rate in Mode3 is variable.

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Special Function Register of 8051:
The group of registers, implemented to
perform special functions and are located
immediately above the 128 bytes of RAM are
called special function registers.
All access to the four I/O ports, the CPU
registers, interrupts control registers, the
timer/counter, UART and power control are
performed through registers between 80H and
FFH.
Special Function Registers (SFRs) are a sort of
control table used for running and monitoring
the operation of the microcontroller.
Even though there are 128 memory locations
intended to be occupied by them, the basic
core, shared by all types of 8051
microcontrollers, has only 21 such registers.
Rest of locations is intentionally left
unoccupied in order to enable the
manufacturers to further develop
microcontrollers keeping them compatible
with the previous versions.
Among the 21 SFRs 11 registers are bit addressable. Figure 14(Addressing of SFRs)

Timer /Counter Registers:

Timer/ Counter 0:
The 16-bit register of Timer 0 is accessed as 16 bit or as low byte and high byte.
The low byte register is called TL0 (Timer 0 low byte) and the high byte register is referred to
as TH0 (Timer 0 high byte).
These registers can be accessed like any other register in 8051.
It can be used as timer or as an event counter.
Timer/ Counter 1:
The 16-bit register of Timer 1 is accessed as16 bit or low byte and high byte.
The low byte register is called TL1 (Timer 1 low byte) and the high byte register is referred to
as TH1 (Timer 1 high byte).
These registers can be accessed like any other register in 8051.
It can be used as timer or as an event counter.
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TMOD Register:
Both timers 0 and 1 use the same register, called TMOD, to set the various timer operation
modes.
TMOD is an 8-bit register in which the lower 4 bits are set aside for Timer 0 and the upper 4
bits for Timer 1.
In each case, the lower 2 bits are used to set the timer mode and the upper 2 bits to specify the
operation.

GATE: Gating control when set. The timer/counter is enabled only while the 0 or 1 pin
is high and the TR0 or TR1 control pin is set.
When cleared, the timer is enabled whenever the TR1 or TR0 control bit is set.
/ : Timer or counter select bit.
Cleared for timer operation, the clock input is from internal system clock.
Set for counter operation, the clock input is from T0 or T1 input pin of the port 3.
M1, MO: M1 and M0 select the timer mode as shown in the table below.
M1 M0 Mode Operation
0 0 Mode 0 13 bit Timer / Counter
0 1 Mode 1 16 Bit Timer / Counter
1 0 Mode 2 8 Bit Auto Reload mode Timer/Counter
1 1 Mode 3 8-Bit Split timer.

PCON.7 PCON.6 PCON.5 PCON.4 PCON.3 PCON.2 PCON.1 PCON.0

SMOD - - - GF1 GF0 PD IDL

PCON.7: SMOD : Double baud rate bit for Serial Communication.

PCON.6
To - : Reserved for feature purpose
PCON.4
PCON.3 GF1 : General Purpose Flag 1

PCON.2 GF0 : General Purpose Flag 0

PCON.1 PD : Power Down mode select bit

PCON.0 IDL : Idle Mode Select bit

IE- Register (Interrupt Enable):

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Each of the interrupt sources can be individually enabled or disabled by setting or clearing a
bit in the SFR named IE (Interrupt Enable).
This register also contains a global disable bit, which can be cleared to disable all interrupts at
once.
The following figure shows the bit format of the IE register.

IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0

EA - - ES ET1 EX1 ET0 EX0

: Disables all interrupts.

IE.7 If EA = 0,no interrupt will be acknowledged.
EA
If EA = 1, each interrupt source is Individually enabled or
disabled by setting or clearing its enable bit.
IE.6 - : Reserved for future use.

IE.5 : Reserved for future use

IE.4 ES : Serial Interrupt enable bit

IE.3 ET1 : Timer / Counter 1 Interrupt enable bit

IE.2 EX1 : External hardware interrupt 1 enable bit

IE.1 ET0 : Timer / Counter 1 Interrupt enable bit

IE.0 ET0 : External hardware interrupt 0 Enable bit

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