IC Synthesis and Optimisation

Professor: Sci.D., Professor

Vazgen Melikyan

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Course Overview

 Logic Synthesis  CTS

 2 lectures  2 lectures
 Timing and Area Constraints  Placement
 2 lectures  2 lectures
 Design for Test  Routing
 5 lectures  2 lectures
 Attributes and Constraints  Power Optimization
 5 lectures  4 lectures
 Compile Strategies  OCV
 5 lectures  2 lectures
 Physical Design Data  Physical Verification
 2 lectures  1 lecture
 Design Planning  Power Estimation
 4 lectures  2 lectures

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Logic Synthesis

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Synthesis and Optimization

 Goal of this course:

 Learn ways of synthesizing digital ICs
 Explore optimization possibilities and issues
 Learn usage of Synopsys EDA tools for design
synthesis and optimization

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Design Levels
Hardware
Example of Modeling
Level Modeling Object Description
Object
Language Used
System C/C++
(Electronic System Structural Circuit RAM bus CPU System Verilog
Level – ESL) System C
Functional Circuits
Register-Transfer on the level of Add
Accumulator
Level multibit devices – Input
registers, and data Command Register
(RTL) transfer between +1
Verilog
Command Counter
them VHDL
Gate Level Circuit containing
logic gates (AND,
(Gate level netlist, OR, etc.) and flip- J

Logic circuit) flops K

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Design Levels (2)

Hardware
Level Modeling Object Example of Modeling Object Description
Language Used

Circuit Level
SPICE
(Transistor Level, Electrical Circuit
CDL
SPICE Netlist)

n+

p+
Device Level IC Components n -
n+
p

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Design Steps

 Digital IC Design  Custom Design (Digital, Analog,

Manual Specification Mixed-Signal)

Specification Manual
System Level Design

System Level Schematic Design

Auto

High-level synthesis Transistor Manual

(HLS)

RTL Layout Design

Auto
Logic Synthesis Physical

Gate
Auto
Physical Synthesis

Physical

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Main Concepts

 Synthesis
 The process which converts an abstract form of
desired circuit behavior into a design implementation
in terms of logic gates
 Optimization
 Changing design to achieve design goal (required by
specification)

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Basic Steps of Synthesis
RTL y=(a+b)&(c⊕d)&e

Logic Synthesis

Gate

Physical Synthesis

Physical

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Logic Synthesis

Specification Logic Synthesis Logic Circuit

Building Blocks
(Library)

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Specification

Specification
Design Description
Circuit must turn lights when a button is pressed, or ask for recharge
if battery charge is low
N0 Parameter description Min Typ Max Units Specification is the list of
1. Process 3.3V IO devices in TSMC 0.11 goals that should be
2. Voltage 1.08 1.2 1.32 V achieved in the given design.
3. Temperature -40 125 0C

4. Power Dissipation 100 mW

5. Die Area 2 um2

6. Clock frequency 1GHz

…. …. …. …. …. ….
…. …. …. …. …. ….
…. …. …. …. …. ….

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 Design Description

Design description (behavior)

Specification
must be translated to
Design Description
Hardware Description
Circuit must turn lights when a button is pressed, or ask for recharge
if battery charge is low Language (HDL)
N0 Parameter description Min Typ Max Units understandable by EDA tools.
1. Process 3.3V IO devices in TSMC 0.11
2. Voltage 1.08 1.2 1.32 V RTL level description is used
3. Temperature -40 125 0C as input for synthesis.
4. Power Dissipation 100 mW
RTL Example
5. Die Area 2 um2

6. Clock frequency 1GHz

if button1_pressed
if (battery_charge > 10)
…. …. …. …. …. ….
turn_on_light();
…. …. …. …. …. ….
else
…. …. …. …. …. …. prompt_for_recharge();

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 Operating Conditions
Specification Design depends on operating
Design Description conditions
Circuit must turn lights when a button is pressed, or ask for recharge
if battery charge is low Design parameters change if
designs operates at different
N0 Parameter description Min Typ Max Units
 Process variation
1. Process 3.3V IO devices in TSMC 0.11  Voltage change
2. Voltage 1.08 1.2 1.32 V  Temperature
3. Temperature -40 125 0C

Design is designed to work at

4. Power Dissipation 100 mW different combinations of P, V, T
5. Die Area 2 um2  Fast transistors, 1.08V, 1250C
 Slow transistors, 1.2V, 1250C
6. Clock frequency 1GHz
…. …. …. …. …. ….
This cases are called PVT corners
…. …. …. …. …. ….
…. …. …. …. …. ….
Process variations are usually generalized as: fast , slow, typical
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 Design Constraints

Specification Design goals are specified

Design Description as constraints .
Circuit must turn lights when a button is pressed, or ask for recharge
if battery charge is low Power ≤ 100 mW
N0 Parameter description Min Typ Max Units Area < 2 um2
1. Process 3.3V IO devices in TSMC 0.11 Frequency > 1 GHz
2. Voltage 1.08 1.2 1.32 V
3. Temperature -40 125 0C Design constraints are used
4. Power Dissipation 100 mW
as input for synthesis.
5. Die Area 2 um2
6. Clock frequency 1GHz
…. …. …. …. …. ….
…. …. …. …. …. ….
…. …. …. …. …. ….

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Logic Synthesis

Design RTL
description

Specification Logic Synthesis Logic Circuit

Design
Constraints

Building Blocks
(Library)

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Logic Circuit
Digital standard cells Final logic circuit consists
of digital standard cells
and Intellectual Property
(IP) blocks.

Digital Standard Cell

Library and IP cell library
should be given as input
to synthesis to be used as
building blocks.

RAM
Intellectual property (IP) block

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Logic Synthesis

Design RTL
description

Specification Logic Synthesis Logic Circuit

Design
Constraints

Digital Standard
IP cell library
Cell Library

Building Blocks (Library)

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 Logic Synthesis Steps
residue = 16’h0000;
Design RTL description if (high_bits == 2’b10)
residue = state_table[index];
Technology Specific else
Circuit is obtained state_table[index] = 16’h0000;
from independent one Translation
by replacing all
components by real
blocks (standard Technology Independent
cells). This
Circuit
replacement process
is also called
mapping. Technology
Compilation
Independent Circuit is
4x and Optimization
logic circuit which fully
3x
implements function
2x 8x described but is built
Technology Specific from Generic Boolean
1x 2x Circuit Gates.

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Constraint-Driven Synthesis
Design RTL description User can control synthesis process by
providing constraints. Constraints are taken
into account in the optimization step
Translation

Technology Independent
Circuit

Design
Compilation
Constraints
and Optimization

Technology Specific
Circuit
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Synthesis and Optimization

y=(a+b)&(c⊕d)&e
 Synthesis
 The process which converts
an abstract form of desired a
circuit behavior into a b y
design implementation in c
terms of logic gates d
e
 Optimization
 Changing design to achieve
design goal (required by a
2
specification) b 3 y
c
1
d
e
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Main Optimization Trade-Offs

Circuit design is a trade- Cell Power

off of timing, power and 2

area 2.5
 Timing optimization 3
 Goal: small delays
Same function: Y=a+b+c+d
 Power optimization
a a
 Goal: low power b b
c y c
consumption d d y
e e
 Area optimization
 Goal: small area Total power:~6 Total power:~5

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Design Constraints: Parameter
Trade-off
Frequency is usually
Power replaced by delay, as the
lower the delay the larger is
frequency
Large
Optimal point Power < 100 mW
•
Area < 2 um2
• Delay < 1ns
•
• • •
Small

Short Long Delay

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