UNIT – 1

Computer Organization and Architecture

Computer Organization and Architecture explores the internal structure and functionality of computer systems,
encompassing both hardware components and their interactions. It delves into how these components are designed,
connected, and controlled to perform operations, ultimately shaping the system's overall performance and capabilities.

 Computer Architecture:
The blueprint of a computer system, describing the structure and behavior of its functional modules, including
instruction sets, data representation, and I/O mechanisms. It focuses on the logical interface visible to programmers.

 Computer Organization:

The implementation of the architectural specifications, detailing how operational units are interconnected and how
hardware details are realized. It focuses on the physical implementation and how the architecture is realized in
hardware.

In essence, computer organization and architecture focuses on the following:

 How hardware components are designed and interconnected.

 How software interacts with the hardware.

 How different architectural choices impact performance, cost, and reliability.

 Understanding the inner workings of computers to design, develop, and implement better applications.

Difference between Computer Architecture and Computer Organization

Computer Architecture Computer Organization

Architecture describes what the computer does. The Organization describes how it does it.

Computer Architecture deals with the functional Computer Organization deals with a structural
behavior of computer systems. relationship.

In the above figure, it’s clear that it deals with In the above figure, it’s also clear that it deals with

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 Computer Architecture Computer Organization

high-level design issues. low-level design issues.

Architecture indicates its hardware. Whereas Organization indicates its performance.

As a programmer, you can view architecture as a

The implementation of the architecture is called
series of instructions, addressing modes, and
organization.
registers.

For designing a computer, its architecture is fixed For designing a computer, an organization is decided
first. after its architecture.

Computer Architecture is also called Instruction Computer Organization is frequently called

Set Architecture (ISA). microarchitecture.

Computer Architecture comprises logical

Computer Organization consists of physical units like
functions such as instruction sets, registers, data
circuit designs, peripherals, and adders.
types, and addressing modes.

The different architectural categories found in

our computer systems are as follows: CPU organization is classified into three categories
 Von-Neumann Architecture based on the number of address fields:
 Harvard Architecture  Organization of a single Accumulator.
 Instruction Set Architecture  Organization of general registers
 Micro-architecture  Stack organization
 System Design

It makes the computer’s hardware visible. It offers details on how well the computer performs.

Architecture coordinates the hardware and Computer Organization handles the segments of the
software of the system. network in a system.

The software developer is aware of it. It escapes the software programmer’s detection.

Examples- Intel and AMD created the x86 Organizational qualities include hardware elements
processor. Sun Microsystems and others created that are invisible to the programmer, such as
the SPARC processor. Apple, IBM, and interfacing of computer and peripherals, memory
Motorola created the PowerPC. technologies, and control signals.

Structure of Desktop Computers

The desktop computers are the computers which are usually found on a home or office desk. They consist of
processing unit, storage unit, visual display and audio as output units, and keyboard and mouse as input units. Figure
shows these five functional

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 Input Unit - The input unit accepts the digital information from user with the help of input devices such as
keyboard, mouse, microphone etc. The information received from the input unit is either stored in the memory for
later use or immediately used by the arithmetic and logic unit to perform the desired operations.

Memory Unit - The memory unit is used to store programs and data. Usually, two types of memory devices are used
to form a memory unit: primary storage memory device and secondary storage memory device. The primary
memory, commonly called main memory is a fast memory used for the storage of programs and active data. These
memories are fast but they are small in capacities and expensive. Therefore, the computer uses the secondary storage
memories such as magnetic tapes, magnetic disks for the storage of large amount of data.

Arithmetic and Logic Unit - The Arithmetic and Logic Unit (ALU) is responsible for performing arithmetic
operations such as add, subtract, division and multiplication and logical operations such as AND, OR, Inverting etc.

Output Unit - The output unit sends the processed results to the user using output devices such as video monitor,
printer, plotter, etc. The video monitors display the output on the CRT screen whereas printers and plotters give the
hard- copy output.

Control Unit - The control unit co—ordinates and controls the- activities amongst the functional. The basic
function, of control unit is to fetch the instructions stored in the main memory, identify the operations and the devices
involved in it and accordingly generate control signals to execute the desired operations.

CPU (Central Processing Unit)

The CPU is the brain of the Computer system. It works as an administrator of a system. All the operations within the
system are supervised and controlled by CPU. It interprets and co-ordinates the instructions. The data and
instructions are temporarily stored in its memory unit. After performing Operation, the result of operation can be
stored in this memory unit.

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 The results of operation are sent towards output unit for the user. Thus, CPU controls all internal and external devices,
performs arithmetic and logical operations, and controls the memory usage and control the sequence of operations.
For performing all these operations, the CPU has three subunits.

 Arithmetic and Logic Unit (ALU)

 Control Unit
 Memory (CPU registers)

Types of CPU Organization

There are three main types of CPU organization in computer architecture: Single Accumulator Organization, General
Register Organization, and Stack Organization. These organizations differ primarily in how they handle data storage and
access during instruction execution.

1. Single Accumulator Organization:

This is one of the simplest forms of CPU design. In this organization, there is only one accumulator register that holds
intermediate data for arithmetic or logical operations. The CPU fetches data from memory into the accumulator,
performs the operation, and stores the result back into the accumulator or memory.

2. General Register Organization:

CPU Registers - Register is a group of flip-flops which can be used to store a word. It is a high speed temporary
storage space for holding data, addresses and instructions during processing the instruction. Registers are not
referenced by their addresses; they are directly accessed. To perform execution of instruction, the processor contains
a number of registers used for temporary storage of data and some special function registers.
The special purpose registers include Program Counter (PC), Instruction Register (IR), Memory Address Register
(MAR) and Memory Data Register (MDR).
Program Counter (PC):- It is used to store the address of next instruction to be executed.
Instruction Register (IR):- It is used to hold the instruction that is currently being executed. The contents of IR are
available to the control unit, which generate the timing signals that control the various processing elements involved
in executing the instruction.
Memory Address Register [MAR] and Memory Data Register (MDR): - These registers are used to handle the
data transfer between the main memory and the processor.
Memory Address Register [MAR] :-The MAR holds the address of the main memory to or from which data is to
be transferred.
Memory Data Register [MDR] :-The MDR sometimes also called MBR (Memory Buffer Register) contains the
data to be written into or read from the addressed word of the main memory.
Accumulator (AC):- It holds the result generated by ALU.
General purpose registers - These are used to hold the operands for arithmetic and logic operations and/or used to
store the result of the operation. Since the access time of these registers is lowest, these are used to store frequently
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 used data.
Figure shows the general Register organization for seven CPU registers. It shows that how registers are selected and
how data flow between register and ALU take place. Decoder is used to select a particular register. The output
of each register is connected to two multiplexers (MUX) to form the two buses A and B. The selection lines in each
multiplexer select the input data for the particular bus. The A and B buses form the two inputs of an Arithmetic Logic
Unit (ALU). The operation select lines decide the micro operation to be performed by ALU. The result of the micro-
operation is available at the output bus. The output bus connected to the inputs of all registers, thus by selecting a
destination register it is possible to store the result in it.

Control Word
The combined value of a binary selection inputs specifies the control word. There are 14 binary selection inputs in
the unit and their combined value specifies a Control word. It consists of four fields SELA, SELB and SELREG
contain three bits each and SELOPR field contains four bits. Thus the total bits in the control word are 13-bits.

Format of control word

The three bits of SELA select a source registers of the A input of the ALU. The three bits of SELB select a source
registers of the B input of the ALU. The three bits of SELREG select a destination register using the decoder. The
four bits of SEL OPR select the operation to be performed by ALU.

Encoding of Register Selection Fields

Binary Code SEL A SEL B SEL D
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7

The encoding of the ALU operations for the CPU is specified in the table given below. The OPR field has five bits and
each operation is designated with a symbolic name.

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 Encoding of ALU Operation
OPR Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 Add A+B ADD
00101 Subtract A-B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift Right A SHRA
11000 Shift Left A SHLA

3. Stack Organization:

The stack in the digital computer is a part of register unit or memory unit with a register that holds the address for the
stack. The part of register array or memory used for stack is called stack area and the register used to hold the
address of stack is called stack pointer. The value in the stack pointer always points at the top data element in the
stack.

1. Register Stack

5 word register stack

A stack can be placed in a portion of a memory unit or it can be organized as a collection of a finite numbe r of
CPU registers. The Figure shows the organization of a 32-word register stack. The stack pointer holds the address
of the register that is currently the top of stack. As shown in the Figure four data elements 10, 20, 30 and 40 are
placed in the stack. The data element 40 is on the top of stack therefore, the content of SP is now 4.

2. Memory Stack
The operation of memory stack is exactly similar to the register stack. It is implemented using computer memory
instead of CPU register array. The number of registers in the CPU is limited and it restricts the size of stack in the
stack computer. But when stack is implemented using memory its size is extended upto the memory addressing
capacity of the CPU.

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 Memory Stack Organization

Instruction Format:

Computer has a variety of instruction code formats, it is the control unit within the CPU that interprets each
instruction code and provides the necessary control functions needed to process the instruction. The format of an
instruction is usually depicted in a rectangular box symbolizing the bits of the instruction as they appear in memory
words or in a control register given in figure. The bits of the instruction are divided into groups called fields. These
information fields of instructions are called elements of instruction & most common fields found in instruction
formats are:

16 bit
Instruction Format

Operation code: - The operation code field in the instruction specifies the operation to be performed. The operation is
specified by binary code hence the name operation code or simply opcode.
Source / Destination operand: - The source/destination operand field directly specifies the source/destination operand for
the instruction.
Source operand address: - The operation specified by the instruction may require one or more operands. The source
operand may be in the CPU register or in the memory.
Destination operand address: - The operation executed by the CPU may produce result. Most of the time the results are
stored in one of the operand. Such operand is known as destination operands.
Next instruction address: - The next instruction address tells the CPU from where to fetch the next instruction
after completion of execution of current instruction.
Address Instructions
In these instructions, the locations of all operands are defined implicitly. Such instructions are found in machines that
store operands in a structure called a pushdown stack. A stack-organized computer does not use an address field for
the instructions ADD and MUL. The PUSH and POP instructions, however, need an address field to specify the
operand that communicates with the stack.
The following program shows how X = (A + B) * (C + D) will be written for a stack organized computer. (TOS
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 stands for top of stack.)
Three-Address Instructions: Computers with three-address instruction formats can use each address field to
specify either a processor register or a memory operand. The program in assembly language that evaluates
X = (A + B) ∗ (C + D) is shown below,
ADD R1, A, B R1 C M [A] + M [B]
ADD R2, C, D R2 C M [C] + M [D]
MUL X, R1, R2 M [X] C R1 ∗ R2
Two-Address Instructions: Two address instructions are the most common in commercial computers. Here again
each address field can specify either a processor register or a memory word. The program to evaluate
X = (A + B) ∗ (C + D) is as follows:
MOV R1, A R1 C M [A]
ADD R1,B R1 C R1 + M [B]
MOV R2, C R2 C M [C]
ADD R2, D R2 C R2 + M [D]
MUL R1, R2 R1 C R1∗R2
MOV X, R1 M [X] C R1
One-Address Instructions: One-address instructions use an implied accumulator (AC) register for all data
manipulation. The program to evaluate
X = (A + B) ∗ (C + D) is as follows:
LOAD A AC C M [A]
ADD B AC C A [C] + M [B]
STORE T M [T] C AC
LOAD C AC C M [C]
ADD D AC C AC + M [D]
MUL T AC C AC ∗ M [T]
STORE X M [X] C AC
Zero-Address Instructions: A stack-organized computer does not use an address field for the instructions ADD
and MUL. The PUSH and POP instructions, however, need an address field to specify the operand that
communicates with the stack.
The following program shows how X = (A + B) ∗ (C + D) will be written for a stack organized computer. PUSH A
TOS C A
PUSH B TOS C B
ADD TOS C (A + B)
PUSH C TOS C C
PUSH D TOS C D
ADD TOS C (C + D)
MUL TOS C (C + D) ∗ (A + B)
POP X M [X] C TOS
The name “zero-address” is given to this type of computer because of the absence of an address field in the
computational instructions.

Difference between two address instructions and three address instructions

Feature Two-Address Instructions Three-Address Instructions

Operands Two Three

Source & Combined (destination is often Separate source and destination

Destination one source)

Code Shorter than one-address Potentially shorter than two-address

Length

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 Bits per Fewer bits needed More bits needed
Instruction

Complexity Simpler to decode More complex to decode

Difference between 2-Address Instruction and 1-Address Instruction

Parameter 2-Address Instruction 1-Address Instruction

The type of instruction in a

A type of instruction in computer
computer system that requires
system that takes only one
Basic minimum two operands to
operand to perform operations is
perform operations is known as a
called a 1-address instruction.
2-address instruction.

Number of 2-address instruction takes two 1-address instruction takes only

operands operands. one operand.

The following is the syntax of a 2- The following is the syntax of a

Syntax address instruction: 2-address instruction:
Opcode Source, Destination Opcode Operand

1-address instructions use only

Number of 2-address instructions use more
one register to store both operand
registers number of registers.
and the result.

Execution 2-address instructions require 1-address instructions require less

time more time to execute. time to execute.

The implementation of a 2-address The implementation of 1-address

Complexity
instruction may be more complex. instructions is less complex.

1-address instructions result in

2-address instructions require less
less compact code than 2-address
instructions to perform tasks,
Code density instructions as they require more
hence they are more compact in
instructions to perform the same
terms of code.
tasks.

1-address instructions require

Memory 2-address instructions require less
frequent memory access to load
access frequent address to memory.
operands and store results.

Computer programs that use 1-

Computer programs written using
adress instructions require less
Storage 2-address instructions require
memory space than 2-address
more storage space in memory.
instruction programs.

Instruction The delay of 2-address The delay of 1-address instruction

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 delay instructions can be longer as they is shorter than that of 2-address
require more cycles to execute. instructions.

Arithmetic and Logic Unit (ALU)

ALU conducts arithmetic and logic operations. It is a major component of the CPU in a computer system. An integer unit
(IU) is just an integrated circuit within a GPU or GPU that performs the last calculations in the processor.

It can execute all arithmetic and logic operations, including Boolean comparisons, such as subtraction, addition, and
shifting (XOR, OR, AND, and NOT operations). Binary numbers can also perform bitwise and mathematical operations.
AU (arithmetic unit) and LU (logic unit) are two types of arithmetic logic units. The ALU’s operands and code instruct it
on which operations to perform based on the incoming data. When the ALU has finished processing the data, it sends the
result to the computer memory.

Operations Performed by ALU

Although the ALU is a critical component of the CPU, the design and function of the ALU may vary amongst
processors. Some ALUs, for example, are designed solely to conduct integer calculations, whereas others are built to
perform floating-point computations. Some processors have a single arithmetic logic unit that performs operations,
whereas others have many ALUs that conduct calculations. ALU’s operations are as follows:

1. Arithmetic Operators: It refers to bit subtraction and addition, despite the fact that it does multiplication and
division. Multiplication and division processes, on the other hand, are more expensive to do. Addition can be used in
place of multiplication, while subtraction can be used in place of division.

2. Bit-Shifting Operators: It is responsible for a multiplication operation, which involves shifting the locations of a bit
to the right or left by a particular number of places.

3. Logical Operations: These consist of NOR, AND, NOT, NAND, XOR, OR, and more.

ALU Signals
The ALU contains a variety of electrical input and output connections, which result in the digital signals being cast
between the ALU and the external electronics. External circuits send signals to the ALU input, and the ALU sends
signals to the external electronics.

Opcode: The operation selection code specifies whether the ALU will conduct arithmetic or a logic operation when it
performs the operation.

Data: The ALU contains three parallel buses, each with two input and output operands. These three buses are in charge
of the same amount of signals.

Status
Input: Once ALU has completed the operation, then the status inputs allow the ALU to obtain more information needed
to complete the process successfully. A single “carry-in” is used, which is a stored carry-out from the prior ALU
operation.

Output: The status outputs, which are numerous signals, offer the results of an ALU operation in the form of extra data.
Overflow, carry out, zero, negative, and other status signals are usually handled by general ALUs. The status output
signals were stored in the external registers after the ALU completed each operation. These signals are saved in external
registers, which allows them to be used in future ALU operations.

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 I/O SYSTEM

The central processing unit, memory unit and I/O unit are the hardware components/modules of the computer. They
work together with communicating each other and have paths for connecting the modules together.
The terminal sends and receives serial information. Each quantity of information has eight bits of an alphanumeric
code. The serial information from the keyboard is shifted into the input register INPR. The serial information for the
printer is stored in the output register OUTR. These two register communicate with a communication interface
serially and with the AC in parallel. The flags are needed to synchronize the timing difference between I/O device
and the Computer.
The input-output configuration is shown in Figure.

Input-Output Configuration

Functions of Input-Output Interface:

1. It is used to synchronize the operating speed of CPU with respect to input-output devices.
2. It selects the input-output device which is appropriate for the interpretation of the input-output signal.
3. It is capable of providing signals like control and timing signals.
4. In this data buffering can be possible through data bus.
5. There are various error detectors.
6. It converts serial data into parallel data and vice-versa.
7. It also convert digital data into analog signal and vice-versa.

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 Bus:

The collection of paths connecting the various modules is called the interconnection structure or Bus. A group of
wires called bus is used to provide necessary signals for communication between modules. A bus is a shared
transmission medium, it must only be used by one device at a time and when used to connect major computer
components (CPU, memory, I/O) is ‘called a system bus.
The system bus is separated into three functional groups: data bus, address bus and control bus
Data lines (data bus) - Move data between system modules. The data bus lines are bidirectional. CPU can read data on
these lines from a port, as well as send data out on these lines to a memory location or to a port. Width is a key factor, It
determines number of bytes that can be transferred in one cycle and hence the overall system performance.
Address lines (address bus) - Designate source or destination of data on the data bus. It is a unidirectional bus.
Width determines the maximum possible memory capacity of the system. It also used to address I/O ports. Typically:
High -order bits select a particular module. Lower order bits select a memory location or I/0 ports within the module.
Control lines (Control bus) - Control access to use the data and address lines. Typical control lines include:
1. Memory Read and Memory write
2. I/O Read and [/0 Write
3. Transfer ACK
4. Bus Request and Bus Grant
5. Interrupt Request and Interrupt ACK
6. Clock & Reset
If one module wishes to send data to another, it must:
1. Obtain use of the bus
2. Transfer data via the bus
If one module wishes to request data from another, it must :
1. Obtain use of the bus
2. Transfer a request to the other module over control and address lines
3. Wait for second module to send data

Connecting I/O Devices to CPU and Memory

It shows that how I/0 devices are connected to CPU and memory. I/0 devices are interfaced to CPU through I/O
interface or I/O module. The I/O interface consists of circuit, which connect an I/O device to a CPU bus. On one side
of the interface we have the bus signals for address, data and control. On the other side we have a data path with its
associated controls to transfer data between the interface and the I/O device. Usually I/O interface or I/O module is
capable of interfacing more than one external device.
Since data, address and control buses are connected in parallel to CPU, memory and I/O the I/O module is allowed to
exchange data directly with memory without going through the processor, using Direct Memory- Access (DMA).
The bus interconnection scheme shown in Figure supports following types of data transfers:
1. Memory to processor - Memory read operation
2. Process to memory – Memory write operation
3. Processor to I/O – I/O write operation
4. I/O to processor - I/O read operation
5. I/O to or from memory- DMA operation

Architecture of System Bus

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 Bus Structure

 A more efficient scheme for transferring information between registers in a multiple- register configuration is a
common bus system.
 A bus structure consists of a set of common lines, one for each bit of a register, through which binary
information is transferred one at a time.
 Control signals determine which register is selected by the bus during each particular register transfer. A
common bus system can be constructed using multiplexers.
 These multiplexers select the source register whose binary information is then placed on the bus.
 The system bus is a cable which carries data communication between the major components of the
computer, including the microprocessor.
 The system bus consists of three different groups of wiring, called the data bus, control bus and address bus.

Register Transfer Language

The symbolic notation used to describe the micro operation transfer among registers is called a register transfer
language. The term “register transfer” implies the availability of hardware logic circuits that can perform stated
micro operation and transfer the results to the operation to the same or another register.
Example:
MOV R1, R2
Here MOV is an Opcode, R1 is destination Register and R2 is source Register. In this Instruction Content of R2 is
being transferred into Register R1.
The features of register transfer logic are:
1. Uses registers as a primitive component in the digital system instead of flip-flops and gates.
2. The information flow and processing tasks among the data stored in the registers is described in a
concise and precise manner.
3. Uses a set of expressions and statements which resemble the statements used in programming
languages.
4. The presentation of digital functions in register transfer logic is very user friendly.
Micro-operations
The operation executed on the data store in registers is called micro-operations. They are detailed low-level
instructions used in some designs to implement complex machine instructions.
Register Transfer
The information transformed from one register to another register is represented in symbolic form by replacement
operator is called Register Transfer.
Replacement Operator
In the statement, R2 <- R1, <- acts as a replacement operator. This statement defines the transfer of content of register
R1 into register R2.

The micro-operations used in the digital system can be classified as:

1. Register transfer micro-operations: The micro-operations that transfer information from one register to
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 another.
2. Arithmetic micro-operations: The micro-operations that perform arithmetic operations on numeric data stored
in registers.
3. Logic micro-operation: The micro-operations that perform bit manipulation operations on non-numeric data
stored in registers.
4. Shift micro-operations: The micro-operations that perform shift operations on data stored in registers.
5.
Examples of Micro operations for the CPU
Micro operations Symbolic Designation Control Word
SEL SEL SEL OPR
A B D
R1<-R2 - R3 R2 R3 R1 SUB 010 011 001 00101
R4<-R4 V R5 R4 R5 R4 OR 100 101 100 01010
R6<-R6+1 R6 - R6 INCA 110 000 110 00001
R7<-R1 R1 - R7 TSFA 001 000 111 00000
Output<-R2 R2 - None TSFA 010 000 000 00000
Output<-Input Input - None TSFA 000 000 000 00000
R4<-sh1 R4 R4 - R4 SHLA 100 000 100 11000
R5<-0 R5 R5 R5 XOR 101 101 101 01100

Bus and Memory Transfer

Bus Transfer
A digital computer has many registers and it is necessary to provide data path between them to transfer information
from one register to another. If separate lines are used between each register there will be excess number of wires
and controlling of those wires make circuit complex. Therefore, in multiple-register configuration a common bus
system is used to transfer information between two registers.

Bus Transfer using multiplexers

The concept of working a common bus system using a multiplexer in 4 bits, 8 bits, or 16 bits is almost the same. This
article will teach us about 4-bit and 8-bit register architecture, but most registers are 16-bit in computer architecture.

Generally, computers use many registers for different purposes. We need to transfer the data and instructions between
these registers. So, To transfer the data between the registers, the common bus system is used. For this purpose, we
connect all registers with a common BUS through Multiplexer.

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 4-bit register in the Common Bus System

The 4-bit register means that the size of the register is 4-bit. These 4-bit registers use four multiplexers because the
number of bits in the register always equals the number of multiplexers. This mechanism is also known as a “4×1”
multiplexer. The 4×1 Multiplexer means four inputs to each Multiplexer from four registers and one output to the
common bus.

As in the above diagram, four registers and four multiplexers, each register of 4 bits, numbering from 0 to 3. There are
two select lines, S0 and S1.

How Registers and multiplexers are connected?

The bits of Register A are (A3, A2, A1, A0). Register B is (B3, B2, B1, and B0). Register C is (C3, C2, C1, and C0).
And Register D is (D3, D2, D1, and D0).

And the first Multiplexer is (D0, C0, B0, and A0). The second Multiplexer is (D1, C1, B1, and A1). The third
Multiplexer is (D3, C3, B3, and A3). The fourth Multiplexer is (D4, C4, B4, and A4).

If we connect the first Multiplexer with registers, then fetch all zero bits from all registers and connect them to the first
Multiplexer. In some way, if we want to connect the second Multiplexer with registers, then fetch all bits from position 1
of all registers, connect them to the 2nd Multiplexer, and so on for other registers and multiplexer connections.

How are the bits transferred from the Multiplexer to the common bus?

We assign values to the select lines connected to each Multiplexer. So, the value of the select line activates the relevant
bit of each Multiplexer and transfers it to the common bus. Here’s a table that shows all combinations of select lines
(S1S0).

SELECT LINES COMBINATION SELECTED REGISTER TO TRANSFER

S1S0 DATA

00 Register A

01 Register B

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 SELECT LINES COMBINATION SELECTED REGISTER TO TRANSFER
S1S0 DATA

10 Register C

11 Register D

When S1S0=00, then Register “A” is activated. The select lines are linked to each Multiplexer, activating the zero (0) bit
in every Multiplexer, as each zero bit is connected to register A. So, one output from each Multiplexer will be sent to the
common bus

Bus Transfer using Three State Buffer

A three-state bus buffer is an integrated circuit that connects multiple data sources to a single bus. The open drivers
can be selected to be either a logical high, a logical low, or high impedance which allows other buffers to drive the
bus. Now, let’s see the more detailed analysis of a 3-state bus buffer in points:

1. As in a conventional gate, 1 and 0 are two states.

2. The third state is a high impedance state.
3. The third state behaves like an open circuit.
4. If the output is not connected, then there is no logical significance.
5. It may perform any type of conventional logic operations such as AND, OR, NAND, etc.
6. To form a single bus line, all the outputs of the 4 buffers are connected together.
7. The control input will now decide which of the 4 normal inputs will communicate with the bus line.
8. The decoder is used to ensure that only one control input is active at a time.
9. The diagram of a 3-state buffer can be seen below.

BASIC CONCEPT OF INSTRUCTIONS

Computer organization refers to the way in which the components of a computer system are organized and
interconnected to perform specific tasks. One of the most fundamental aspects of computer organization is the set of
basic computer instructions that the system can execute.
Basic Computer Instructions
Basic computer instructions are commands given to a computer to perform specific tasks. These instructions are
typically divided into three categories:
1. Data Transfer Instructions: Move data between memory and registers (e.g., Load, Store).
1. Arithmetic and Logic Instructions: Perform math or logic operations (e.g., Add, Subtract, AND, OR).
1. Control Instructions: Guide the flow of the program (e.g., Jump, Branch, Call).
Data Transfer Instructions

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 These instructions deal with moving data from one location to another within the computer. Think of it as copying or
transferring information between various components like memory, registers, or storage.
Common Data Transfer Instructions:
 Load: Copies data from memory to a register (temporary storage inside the CPU).
 Store: Transfers data from a register to memory.
 Move: Transfers data from one register to another.
Arithmetic and Logic Instructions
These instructions are used to perform mathematical and logical operations. They enable computers to handle
calculations and make decisions based on certain conditions.
Arithmetic Instructions:
 Add: Adds two numbers.
 Subtract: Subtracts one number from another.
 Multiply: Multiplies two numbers.
 Divide: Divides one number by another.
Logic Instructions:
 AND: Compares two bits and returns 1 if both are 1; otherwise, returns 0.
 OR: Compares two bits and returns 1 if at least one is 1.
 NOT: Inverts a bit (1 becomes 0, and 0 becomes 1).
 XOR (Exclusive OR): Returns 1 if the bits are different, 0 if they are the same.
Control Instructions
Control instructions determine the flow of execution in a program. They guide the computer on which instruction to
execute next, allowing flexibility in decision-making and repeated actions.
Common Control Instructions:
 Jump (JMP): Directs the program to execute a specific instruction elsewhere in the code.
 Conditional Branch: Jumps to another instruction only if a specific condition is true. Example: Branch if zero
(BZ) or branch if not zero (BNZ).
 Call: Transfers control to a subroutine (a set of instructions performing a specific task) and returns afterward.
 Return: Brings back control to the main program after a subroutine is executed.
Instruction Set of a Basic Computer
The basic computer has 16-bit instruction register (IR) which can denote either memory reference or register reference
or input-output instruction.
Memory Reference Instructions
These instructions refer to memory address as an operand. The other operand is always accumulator. Specifies 12-bit
address, 3-bit opcode (other than 111) and 1-bit addressing mode for direct and indirect addressing.

Register Reference Instructions

These instructions perform operations on registers rather than memory addresses. The IR(14 – 12) is 111
(differentiates it from memory reference) and IR(15) is 0 (differentiates it from input/output instructions). The rest 12
bits specify register operation.

Input/Output Instructions
These instructions are for communication between computer and outside environment. The IR(14 – 12) is 111
(differentiates it from memory reference) and IR(15) is 1 (differentiates it from register reference instructions).
The rest 12 bits specify I/O operation.

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 Addressing Modes

Every instruction of a program has to operate on some data. An addressing mode is a way in which an operand is
specified in an instruction.
There are different ways in which an operand may be specified in an instruction.
1. Implied Mode: In implied addressing mode, the instruction itself specifies the data to be operated. the
implied addressing mode is also called implicit addressing mode, because there is no need to explicitly specify an
effective address for either the source or the destination.
For example -‘‘complement accumulator’’
2. Immediate Mode: In this mode the operand is specified in the instruction itself. The actual operand to be used in
conjunction with the operation specified in the instruction is contained in the operand field. Example: MOVE A, #20
3. Register Mode: In this mode the operands are in registers that reside within the CPU. The register required is
chosen from a register field in the instruction.
Example: MOV R1, R2
4. Register Indirect Mode: In this mode the instruction specifies a register that contains the address of the
operand and not the operand itself.
Effective Address=R
Example: MOVE A, (R0)
5. Auto increment or Auto decrement Mode: After execution of every instruction from the data in memory it is
necessary to increment or decrement the register. This is done by using the increment or decrement instruction.
Example: MOVE R2), + R0
MOVE (R2), - R0

6. Direct Address Mode: In this mode the operand resides in memory and its address is given directly by the
address field of the instruction such that the effective address is equal to the address part of the instruction. Example:
MOVE A, 2000

7. Indirect Address Mode: The effective address of the operand is the contents of a register or main memory
location, location whose address appears in the instruction. Indirection is noted by placing the name of the register or
the memory address given in the instruction in parentheses.
Effective address = address part of instruction + context of CPU register
8. Relative Address Mode: In this mode the content of the program counter is added to the address part of the
instruction in order to obtain the effective address.
EA = PC + Address part of instruction

9. Indexed Addressing Mode: In this mode the effective address is obtained by adding the content of an index
register to the address part of the instruction.
EA= offset + R
Example: MOVE 20 [R1], R2

10. Base Register Addressing Mode: In this mode the effective address is obtained by adding the content of a base
register to the part of the instruction. A base register is assumed to hold a base address and the address field of the
instruction, and gives a displacement relative to this base address. The base register addressing mode is handy for
relocation of programs in memory to another as required in multi programming systems
Example: ADD AX, [BX+SI]
Eight Addressing Modes for load Instruction
Mode Assembly Convention Register Transfer
Direct Address LD ADR AC<-M[ADR]
Indirect Address LD @ADR AC<-M[M[ADR]]
Relative Address LD $ADR AC<-M[PC+ADR]
Immediate Operand LD #NBR AC<-NBR
Index Addressing LD ADR(X) AC<-M[ADR+XR]
Register LD R1 AC<-R1
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 Register Indirect LD(R1) AC<-M[R1]
Auto increment LD (R1) AC<-M[R1],R1<-R1+1

Microinstruction Format
A microinstruction format includes 20 bits in total. They are divided into four elements as displayed in the figure.

F1, F2, F3 are the micro-operation fields. They determine micro-operations for the computer.
CD is the condition for branching. They choose the status bit conditions.
BR is the branch field. It determines the type of branch.
AD is the address field. It includes the address field whose length is 7 bits.
The micro-operations are divided into three fields of three bits each. These three bits can define seven different micro-
operations. In total there are 21 operations as displayed in the table.

Symbols with their Binary Code for Microinstruction Fields

Name: Code Symbol

000 None NOP

001 AC ← AC + DR ADD

010 AC ← 0 CLRAC

011 AC ← AC + 1 INCAC
F1
100 AC ← DR DRTAC

101 AR ← DR(0 − 10) DRTAR

110 AR ← PC PCTAR

111 AC ← AC + DR WRITE

000 None NOP

001 AC ← AC + DR SUB

010 AC ← AC ∨ DR OR

011 AC ← AC ∧ DR AND
F2
100 DR ← M[AR] READ

101 DR ← AC ACTDR

110 DR ← DR + 1 INCDR

111 DR(0 − 10) ← PC PCTDR

000 None NOP

F3 001 AC ← AC ⊕ DR XOR

010 AC ← AC′ COM

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 Name: Code Symbol

011 AC ← shl AC SHL

100 AC ← shr AC SHR

101 PC ← PC + 1 INCPC

110 PC ← AR ARTPC

111 DR(0 − 10) ← PC Reserved

As shown in the table, each microinstruction can have only three micro-operations, one from each field. If it uses less
than three, it will result in more than one operation using the no operation binary code.
Condition Field
A condition field includes 2 bits. They are encoded to define four status bit conditions. As stated in the table, the first
condition is always a 1, with CD = 0. The symbol that can indicate this condition is ‘U’. The table displays the multiple
condition fields and their summary in an easy manner.

Condition Field Symbols and Descriptions

Condition Symbol Comments

00 Always = 1 U Unconditional Branch

01 DR (15) I Indirect address bit

10 AC (15) S Sign bit of AC

11 AC = 0 Z Zero value in AC
As shown in the table, when condition 00 is connected with BR (branch) field, it results in an unconditional branch
operation. Then the execution is read from memory the indirect bit I is accessible from bit 15 of DR. The status of the
next bit is supported by the AC sign bit. If all the bits in AC are 1, then it is indicated as Z (its binary variable whose
value is 1). The symbols U, I, S, and Z can indicate status bits while writing microprograms.
Branch Field
The BR (branch) field includes 2 bits. It can be used by connecting with the AD (address) field. The reason for
connecting with the AD field is to select the address for the next microinstruction. The table illustrates the various branch
fields and their functions.

Branch Field Symbols and Descriptions

BR Symbol Comments

JMP CAR ←AD if condition = 1

00
CAR←CAR + 1 if condition = 0

CALL CAR ←AD , SBR ← CAR +1, if condition = 1

01
CAR←CAR + 1 if condition = 0

10 RET CAR ←SBR (Return from subroutine)

11 MAP CAR(2-5) ←DR(11-14), CAR(0,1,6) ←0

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 As shown in the table, when BR = 00, a JMP operation is implemented and when BR = 01, a subroutine is called. The
only difference between the two instructions is that when the microinstruction is saved, the return address is saved in
the Subroutine Register (SBR).
These two operations are dependent on the CD field values. When the status bit condition of the CD field is defined as 1,
the address that is next in order is transferred to CAR. Else, it gets incremented. If the instruction needs to return from
the subroutine, its BR field is determined as 10.
This results in the transfer of the return address from SBR to CAR. The opcode bits of instruction can be mapped with
an address for CAR if the BR field is 11. They are present in DR (11 - 14) after instruction is read from memory. The
last two conditions in the BR fields are not dependent on the CD and AD field values.
Types of microinstruction
In computer architecture, microinstructions are divided into two main types: horizontal and vertical. Horizontal
microinstructions use a large number of control signals to control multiple operations concurrently, while vertical
microinstructions encode control signals to represent specific operations, making them more compact.
Elaboration:
Horizontal Microinstructions:
 Employ a large number of control signals to control multiple operations simultaneously.
 Each control signal can directly control a specific hardware component or operation.
 This approach allows for greater flexibility and parallelism, as multiple operations can be performed
concurrently.
 However, horizontal microinstructions can be less efficient in terms of memory usage, as they require a
larger number of control bits.
Vertical Microinstructions:
 Encode control signals to represent specific operations, using a smaller number of control bits.
 Each control signal represents a group of operations or a higher-level function.
 This approach results in more compact microprograms, as the control signals are compressed.
 However, vertical microinstructions may be less flexible and less parallel than horizontal
microinstructions.
Other Related Concepts:
 Symbolic Microinstructions: These are used to represent low-level operations performed by a
microprocessor in a more human-readable way.
 Microprogrammed Control Unit: This type of control unit uses a sequence of microinstructions to
execute instructions.
 Hardwired Control Unit: This type of control unit uses a fixed set of logic gates and circuits to execute
instructions, without relying on microprograms.

Instruction cycle

A program residing in the memory unit of a computer consists of a sequence of instructions. These instructions are
executed by the processor by going through a cycle for each instruction.

In a basic computer, each instruction cycle consists of the following phases:

1. Fetch instruction from memory.

2. Decode the instruction.
3. Read the effective address from memory.
4. Execute the instruction.

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 The instruction cycle, also known as the fetch
fetch-decode-execute cycle, is the fundamental process by which a computer's
CPU executes instructions. It involves fetching an instruction from memory, decoding it to determine the operation, and
then executing that operation. This cycle is repeated continuously until the computer is shut down.
Here's a more detailed breakdown:
1. Fetch:
 The CPU retrieves the instruction from memory, typically using the address stored in the Program Counter (PC).
 The instruction is loaded into the Instruction Register (IR).
2. Decode:
 The CPU's control unit interprets the instruction, identifying the opcode and any operands.
 This determines the type of operation to be performed.
3. Execute:
 The CPU performs the operation specified by the instruction.
 This might involve reading or writing data, performing arithmetic/logic operations, or changing the program flow.
4. Additional Considerations:
 Fetch Operands:
Some instructions require fetching operands from memory before execution, which can be done during a separate
cycle.
 Store Results:
After execution, the results might be stored back to memory in a separate cycle.
 Interrupts:
The CPU may check for interrupts after the current instruction is executed. If an interrupt is pending, the CPU will
handle it, possibly interrupting the current instruction. Registers Involved In Each Instruction Instr Cycle:

 Memory address registers(MAR) : It is connected to the address lines of the system bus. It specifies the address
in memory for a read or write operation.
 Memory Buffer Register(MBR) : It is connected to the data lines of the system bus. It contains the value to be
stored in memory or the last value read from the memory.
 Program Counter(PC) : Holds the address of the next instruction to be fetched.
 Instruction Register(IR) : Holds the last instruction fetched.

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 Hardwired Control Unit
A hardwired control is a mechanism of producing control signals using Finite State Machines (FSM) appropriately. It is
designed as a sequential logic circuit. The final circuit is constructed by physically connecting the components such
as gates, flip flops, and drums. Hence, it is named a hardwired controller.
The figure shows a 2-bit sequence counter, which is used to develop control signals. The output obtained from these
signals is decoded to generate the required signals in sequential order.

The hardwired control consists of a combinational circuit that outputs desired controls for decoding and encoding
functions. The instruction that is loaded in the IR is decoded by the instruction decoder. If the IR is an 8-bit register, then
the instruction decoder generates 28 (256) lines.
Inputs to the encoder are given from the instruction step decoder, external inputs, and condition codes. All these inputs
are used and individual control signals are generated. The end signal is generated after all the instructions get executed.
Furthermore, it results in the resetting of the control step counter, making it ready to generate the control step for the next
instruction.
The major goal of implementing the hardwired control is to minimize the cost of the circuit and to achieve greater
efficiency in the operation speed. Some of the methods that have come up for designing the hardwired control logic are
as follows −
 Sequence Counter Method − This is the most convenient method employed to design the controller of moderate
complexity.
 Delay Element Method − This method is dependent on the use of clocked delay elements for generating the
sequence of control signals.
 State Table Method − This method involves the traditional algorithmic approach to design the Notes controller
using the classical state table method.

Microprogrammed Control Unit

A control unit whose binary control values are saved as words in memory is called a microprogrammed control unit.
A controller results in the instructions to be implemented by constructing a definite collection of signals at each system
clock beat. Each of these output signals generates one micro-operation including register transfer. Thus, the sets of
control signals are generated definite micro-operations that can be saved in the memory.
Each bit that forms the microinstruction is linked to one control signal. When the bit is set, the control signal is active.
When it is cleared the control signal turns inactive. These microinstructions in a sequence can be saved in the internal
’control’ memory. The control unit of a microprogram-controlled computer is a computer inside a computer.
The following image shows the block diagram of a Microprogrammed Control organization.
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 There are the following steps followed by the microprogrammed control are −
 It can execute any instruction. The CPU should divide it down into a set of sequential operations. This set of
operations are called microinstruction. The sequential micro-operations need the control signals to execute.
 Control signals saved in the ROM are created to execute the instructions on the data direction. These control signals
can control the micro-operations concerned with a microinstruction that is to be performed at any time step.
 The address of the microinstruction is executed next is generated.
 The previous 2 steps are copied until all the microinstructions associated with the instruction in the set are executed.
The address that is supported to the control ROM originates from the micro counter register. The micro counter received
its inputs from a multiplexer that chooses the output of an address ROM, a current address incrementer, and an address
that is saved in the next address field of the current microinstruction.
Advantages of Microprogrammed Control Unit
There are the following advantages of microprogrammed control are as follows −
 It can more systematic design of the control unit.
 It is simpler to debug and change.
 It can retain the underlying structure of the control function.
 It can make the design of the control unit much simpler. Hence, it is inexpensive and less error-prone.
 It can orderly and systematic design process.
 It is used to control functions implemented in software and not hardware.
 It is more flexible.
 It is used to complex function is carried out easily.

Hardwired Control Unit vs Microprogrammed Control

Hardwired Control Unit Microprogrammed Control Unit

Microprogrammed control unit generates the

Hardwired control unit generates the control signals needed
control signals with the help of micro instructions
for the processor using logic circuits
stored in control memory

Hardwired control unit is faster when compared to

This is slower than the other as micro instructions
microprogrammed control unit as the required control
are used for generating signals here
signals are generated with the help of hardwares

Difficult to modify as the control signals that need to be Easy to modify as the modification need to be done
generated are hard wired only at the instruction level

More costlier as everything has to be realized in terms of Less costlier than hardwired control as only micro
logic gates instructions are used for generating control signals

It cannot handle complex instructions as the circuit design It can handle complex instructions

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 Hardwired Control Unit Microprogrammed Control Unit

for it becomes complex

Only limited number of instructions are used due to the Control signals for many instructions can be
hardware implementation generated

Used in computer that makes use of Reduced Instruction Set Used in computer that makes use of Complex
Computers(RISC) Instruction Set Computers(CISC)

Microprogram Sequencing

The microcode for the control memory should be generated by the inventor once the configuration of the computer is
settled. The generation of code is known as microprogramming.
There are various points to be treated while designing the microprogram sequencer are −
 Size of the microinstruction
 Time of address generation
The microinstruction’s size should be in the least, therefore that the co
control
ntrol memory necessary is less and the cost is
decreased. Microinstructions can be implemented at a quicker rate if the time to create an address is less. This results in
raised throughput.
Disadvantage of Micro-program Sequencing
The disadvantage of microprogram
program sequencing is as follows −
 If each device instruction has an independent micro routine, therefore it results in the help of huger areas for
storage.
 The branching needed more time for implementation.
Micro Instructions Sequencer is a combination of all hardware for selecting the next micro-instruction
instruction address. The
micro-instruction in control memory contains a set of bits to initiate micro-operations in computer registers and other
bits to specify the method by which the address is obtained.

Implementation of Micro Instructions Sequencer

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  Control Address Register(CAR) : Control address register receives the address from four different paths. For
receiving the addresses from four different paths, Multiplexer is used.
 Multiplexer : Multiplexer is a combinational circuit which contains many data inputs and single data output
depending on control or select inputs.
 Branching : Branching is achieved by specifying the branch address in one of the fields of the micro instruction.
Conditional branching is obtained by using part of the micro-instruction to select a specific status bit in order to
determine its condition.
 Mapping Logic : An external address is transferred into control memory via a mapping logic circuit.
 Incrementer : Incrementer increments the content of the control address register by one, to select the next micro-
instruction in sequence.
 Subroutine Register (SBR) : The return address for a subroutine is stored in a special register called Subroutine
Register whose value is then used when the micro-program wishes to return from the subroutine.
 Control Memory : Control memory is a type of memory which contains addressable storage registers. Data is
temporarily stored in control memory. Control memory can be accessed quicker than main memory.
Micro-programmed Controller Unit
A set of micro-instructions make up microprogramming. Three micro-operation phases are primarily present in each
micro-instruction. F1, F2, F3, respectively. We also have the condition, branch, and address fields in addition to these
three.
A 3X8 decoder decodes the F1, F2, and F3 fields because they are all 3 bits in size. We receive 8 outputs from the F1
micro-operation phase. One of these eight outputs is still unutilized.
Like the F1 procedure, the F2 operation produces a total of 7 outputs.
Only six operations can be carried out in the F3 micro-operation phase (one is left unfinished, and the other is saved
for later use).
Therefore, we can complete 20 micro-operations in total (7+7+6).
Out of 20 operations, the diagram above shows 5 micro-operations.
The ALU is attached to F2 output number 3. It applies the AND operation to the contents of the data register and
accumulator, then transfers the outcome to the accumulator. This is how it is written: ACAC AND DR
And we give the matching accumulator a clock pulse. The ability to load it onto the accumulator is enabled.
Output 1 of F1 adds data register and accumulator using an ALU, then sends the outcome to the accumulator.
The DRTAR operation, or transfer of the contents of the data register to the address register, is carried out by output 5
of F1. However, the data register’s size is 16 bits, while the the rightmost significant 12 bits of the data register are
moved to the address register since the address register only has a capacity of 12 bits.
Transferring the contents of the programme counter to the address register is what output 6 of F1 does.

MICROINSTRUCTION SEQUENCING
The first concern which is applicable in general is "to minimize the sue of control memory". The second concern is "to
execute a microinstruction as fast as possible". This implies that the address of next microinstruction should be calculated
at a fast rate. Now, let us find out how these two concerns can be achieved. The factors responsible for reducing the sue
of control memory depend on the length of a microinstruction. The length of microinstruction is greatly influenced by the
following three major factors:
 Degree of parallelism which is needed at the microoperation level or in other words "the number of microoperations
which can be executed simultaneously".
 Representation of encoding of control information.
 The means of specifying the address of next microinstruction.
The number of microoperations which can be executed simultaneously in a processor may vary from one to hundred.
This degree of parallelism is frequently used for characterising the microprogrammable processors. A highly encoded
instruction also tends to be short. We will discuss more about these while we discuss about microinstruction execution.
Let us focus in this section about calculation of the address of next microinstruction. In general, the address of next
microinstruction is:
 The address of next microinstruction in sequence :
 Calculated on the basis of op-code
 Branch address (conditional or unconditional)
Address is calculated only once from the opcode in one instruction cycle. The machine sequences are not long and
branches are common after three or four sequences. Thus, by making branching algorithm better we can make a
microinstruction addressing more time efficient. In general. three techniques based on number of addresses have been
utilized for sequencing. These are:
 Two address fields in each microinstruction
 Single address field and
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  Variable format microinstructions
In the two address fields microinstructions, either of the two addresses or the address generated with the help of op-code
is selected using a branch logic which is based on the flags and control signal. In such a case, branching to a desired
address can be made very easily. However, in this approach a lot of control memory is wasted as at least one of the
addresses may not be needed in several microinstructions.

Microinstruction Execution

The microinstruction cycle can consist of two basic cycles: the fetch and the execute. Here, in the fetch cycle the address
of the microinstruction is generated and this microinsauction is put in a microinstruction register for execution. We have
already dealt with this part in the previous sections. The execution of microinstruction simply means generation of
control signals. These control signals may drive the CPU (internal control signals) or the system bus. The format of
microinstruction and its contents determine the complexity of a logic module which executes a microinstruction.
One of the key features which is incorporated in microinstruction is the encoding of microinstructions. What is encoding
of microinstruction? For answering it, let us recall the Wilkes control unit. In W&es control unit, each bit of information
either generates a control signal or form a bit of next instruction address. Now, let us assume that a machine needs N
total number of control signals. If we follow the Wilkw scheme we require N bits, one for each control signal in the
control unit. Since we are dealing with binary control signals, therefote, a N bit microinstruction can represent 2N
combinations of control signals.
Do we need all these 2N combinations? No, some of these 2* combinations are not used because:
(a) Two sources may be connected by respective control signals to a single destination, however, only one of these
swrces can be used at a time. Thus, the combinations where both these control signals are active for same destination are
redundant.
(b) A register cannot act as source and destitution at the same time. Thus, such a combination of control signals is
redundant
(c) We can provide only one pattern of control signals at a time to ALU, making some of the combinations redundant.
(d) We can provide only one pattern of conml signals at a time to the external control bus also.
Therefore, we do not need all these 2N combinations. Suppose, we only need 2K (which is less than 2N) combinations
then we need only K encoded bits instead of N control signals. The K bit microinstruction is an extreme encoded
microinstruction. Let us touch upon the characteristics of the extreme encoded and unencoded microinstructions:

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