Fundamentals of Low-Power

Neuromorphic Circuit Design with Spiking

Neural Networks (SNNs)

Brain-inspired computing is revolutionizing the way we approach artificial intelligence,

allowing us to tackle complex problems with efficiency and creativity.
(Jeff Hawkins)

1 Background

Spiking neural networks (SNNs) represent a pivotal convergence of neuroscience

and machine learning, offering a biologically plausible framework. In contrast to
earlier iterations of artificial neural networks (ANNs), SNNs operate on discrete
firing events triggered by the attainment of specific postsynaptic potentials,
departing from continuous value firing patterns. Earlier models, such as the integrate
and fire (I&F) model and the Hodgkin-Huxley (HH) model, portrayed neurons as
point entities lacking spatial extent, overlooking the complex dendritic structure
characteristic of biological neurons. Additionally, while simulated currents are
typically injected as input stimuli in SNNs, biological neurons receive inputs within
a network context, wherein inputs manifest as synaptic spikes, eliciting postsynaptic
responses.
As illustrated in Fig. 1, upon the occurrence of an input spike, neurotransmitters
are released via the synaptic cleft, where they are subsequently received by the
postsynaptic receptor. Within the presynaptic terminal, neurotransmitter-loaded
vesicles are situated, with some residing internally while others are positioned on
the surface. Upon the propagation of an action potential along the axon and its
eventual arrival as a spike at the presynaptic neuron, a subset of these vesicles
undergoes fusion with the membrane, thereby expelling neurotransmitters into the
synaptic cleft, which constitutes the interstitial space between the presynaptic and
postsynaptic neurons.

© European Alliance for Innovation 2024 79

A. Ghani, Innovations in Computer Vision and Data Classification,
EAI/Springer Innovations in Communication and Computing,
https://doi.org/10.1007/978-3-031-60140-8_5
80 Fundamentals of Low-Power Neuromorphic Circuit Design with Spiking. . .

400
Pre-synaptic 300 AMPA

Synaptic Current (pA)

200
100 NMDA

0
–100 GABAB
–200 GABAA
Post-synaptic –300
0 100 200 300 400 500
Time (ms)
a b
Fig. 1 (a) The dynamics of neurotransmitters. (b) Multiple synaptic currents

Analogue very-large-scale integration (VLSI) has been widely applied in the

creation of artificial neural networks owing to the resemblance of its transistor
behaviour to that of nerve membrane channels. The imperative of minimal power
consumption in design is underscored by the rapid escalation in power demand
inherent in the deployment of extensive networks comprising thousands of neurons.
A prevalent strategy to address this excellence involves operating transistors within
the weak inversion region, also known as the subthreshold region, where transistor
leakage manifests as minute currents on the order of picoamps to femtoamps.
Among the available transistor options, complementary metal-oxide-semiconductor
(CMOS) transistors have emerged as particularly favourable for VLSI designs.
CMOS transistors exhibit low power consumption during idle periods, draw only
nominal leakage currents, and consume power solely during state transitions, in stark
contrast to bipolar junction transistors (BJTs), which draw continuous currents.
While BJTs boast faster operation speeds, the preference for low power consumption
remains paramount. Furthermore, CMOS fabrication techniques afford the flexibility
to alter channel dimensions, enabling the reduction of transistor lengths to accom-
modate more transistors per unit area. However, this reduction in length is accom-
panied by a concomitant increase in static power consumption, presenting a
noteworthy drawback. This book chapter will particularly help readers understand
the low-level dynamics of a neuronal synapse, its modelling with an analogue circuit
design, the controllable time constant for the decaying and rising phases of synapses,
the linear summation of spikes, a first-order system that experiences minimum delay
and parasitic effects and the control of the quiescent current. Finally, various circuit
simulations are demonstrated for deeper insight.
2 Fundamentals of SNN Circuits and Mathematical Models 81

2 Fundamentals of SNN Circuits and Mathematical Models

2.1 Leaky Integrate and Fire Neuron Model

Figure 2 depicts a fundamental neuron circuit that integrates, fires and resets once the
output reaches the voltage potential ϴ. Despite its straightforward nature, this model
serves as the keystone for various neuron circuits, playing an essential role in
understanding the circuits of spiking neural networks (SNNs) and their operational
attributes.
The equivalent circuit behaviour can be described as:

d
τ u = -ðu - urest Þ þ RI ðt Þ ð1Þ
dt

In Fig. 3, the output fire and reset mechanisms are depicted for both the linear
region, where the potential has not yet reached the threshold value ϴ, and the point at
which the potential reaches ϴ.

Fig. 2 The basic circuit of

an LIF neuron
Output spikes

Input spikes

Fig. 3 Input spikes, output response and reset mechanism

82 Fundamentals of Low-Power Neuromorphic Circuit Design with Spiking. . .

2.2 Mathematical Models of Synapses

Mathematical models of synapses play a crucial role in understanding the complex

dynamics of synaptic transmission and plasticity. These models aim to capture the
intricate interplay of biochemical, electrical and biophysical processes that govern
synaptic function. Various mathematical approaches have been employed to
describe synaptic behaviour, ranging from simple phenomenological models to
detailed biophysical models that incorporate the underlying physiological mecha-
nisms. Phenomenological models, such as the alpha function and the exponential
decay model, offer simplicity and computational efficiency, making them suitable
for large-scale neural network simulations. These models typically describe the time
course of synaptic currents or conductances based on empirical observations of
synaptic responses. On the other hand, biophysically based models seek to elucidate
the underlying physiological mechanisms of synaptic transmission, including neu-
rotransmitter release, receptor dynamics, and postsynaptic receptor kinetics. These
models often involve systems of ordinary differential equations that capture the
dynamics of ion channels, neurotransmitter diffusion and receptor activation. Exam-
ples of biophysical synaptic models include the Tsodyks-Markram model for short-
term synaptic plasticity and the Morris-Lecar model for synaptic integration in
neurons. Overall, mathematical models of synapses provide valuable tools for
investigating synaptic function, plasticity and information processing in neural
circuits and continue to advance our understanding of brain function.
Mathematical models for synaptic conductance are under development to gener-
ate synaptic currents, as illustrated in Figs. 1 and 2:

- I syn ðt Þ = -gsyn ðt Þ u - Esyn ð2Þ

The overall synaptic current is determined by the disparity between the instanta-
neous voltage u and the synaptic reversal potential Esyn. The conductance gsyn(t)
varies over time and can be conceptualized as an exponential pulse for ease of
interpretation, aligning with the synaptic current output AMPA (Fig. 1):
t -t k
gsyn ðt Þ = gsyn e τ Θðt - t k Þ ð3Þ

For t > tk, where the spike initiates at tk, the exponential curve described by Eq. 3
commences at time tk and exponentially decays with a time constant τ. When a
sequence of spikes is received, their outputs exhibit additive behaviour. Conse-
quently, the overall synaptic conductance is obtained by summing these individual
contributions:
t -t k
gsyn ðt Þ = gsyn e τ Θðt - t k Þ ð4Þ
k
2 Fundamentals of SNN Circuits and Mathematical Models 83

The synaptic conductance, shown in Eq. 1 and multiplied by the drive, yields
the synaptic output. To enhance the model’s realism, it is beneficial to incorporate
the rise time, as biological neurons typically exhibit two distinct time constants, with
the rising phase typically faster than the decaying phase. A slight adjustment to Eq. 4
could accommodate the inclusion of the rise time, as depicted below:

t -t k t -t k
-τ
gsyn ðt Þ = gsyn e τ 1-e rise Θðt - t k Þ ð5Þ
k

The total synaptic conductance can be multiplied by the driving potential to

obtain the synaptic current. Subsequently, this synaptic current could be incorpo-
rated into models such as the Hodgkin-Huxley model:

du
C = -gNa m3 hðuENa Þ - gK n4 ðu - EK Þ - gl ðu - E l Þ þ I stim ðt Þ ð6Þ
dt

The total stimulating current, denoted as Istim(t), is delineated by Eq. 2, indicating

that the output derived from synaptic currents such as AMPA or NMDA manifests as
a positive stimulating current. However, within actual neuronal systems, stimulating
currents per se are absent; rather, they are represented by channels. Specifically, gNa,
gk and gl correspond to sodium, potassium and leak channels, respectively, while
Istim (t) represents an additional channel characterized by a negative sign (Eq. 2).
Glutamate mediates excitatory synapses, whereas GABA governs inhibitory synap-
ses. Both synaptic types adhere to the same equation outlined in Eq. 2. Nevertheless,
disparity arises from the reversal potential; excitatory synapses exhibit a high Esyn
(approximately 0 mV), whereas inhibitory synapses feature a low Esyn (approxi-
mately -75 mV).

2.3 Fundamental Synapse Circuit Design

Figure 4 depicts a straightforward synapse circuit, initially conceived by Carver

Mead at Caltech [1], designed to convert a voltage pulse into a current. The
magnitude of this current is governed by the weighted voltage Vw. Notably, the
pulse width of the resulting current mirrors that of the input voltage. However, in
scenarios where input voltages exhibit minimal width and lack control, the parameter
Vτ assumes significance, setting the time constant or pulse width of the current I0, as
exemplified in Fig. 5, as per the original design described in [2].
Synaptic circuits typically exhibit scaling, which can be achieved through either
voltage control or current control. In Fig. 6, this scaling mechanism utilizes two
voltages, V1 and V2, to adjust the current.
The transistors operate within the subthreshold region to leverage their exponen-
tial characteristics and achieve very low power consumption. Eq. 7 elucidates the
84 Fundamentals of Low-Power Neuromorphic Circuit Design with Spiking. . .

Fig. 4 A simple electronic

synapse circuit

Fig. 5 A basic synapse

circuit featuring both
magnitude and width control

functioning of the synapse circuit within this subthreshold region, as shown in Eq. 7,
where VT is the thermal voltage.
.

kðV 1 -V 2 Þ
I0 = Iie 2V T
ð7Þ

The scaling of current through current controls is facilitated by the circuit

depicted in Fig. 6b, as documented by [2].
In this instance, the scaling is delineated by Eq. 8.

I1
I0 = Ii ð8Þ
I2

The scaling property observed in the circuits depicted in Fig. 6a, b can be applied
to synapse circuits requiring adaptation. An adaptive circuit utilizing the scaling
circuit is exemplified in Fig. 7, as documented by [3]. In this circuit, the input Ii
yields an output I0, which represents a scaled version of Ii. A supplementary input to
3 Methodology for Neuromorphic Circuit Simulation 85

Fig. 6 (a) Adjusting the current output by utilizing the two voltage controls, V1 and V2
(b) Adjustment of current output through the utilization of I1 and I2

Fig. 7 Synaptic circuit with

adaptation

the circuit, denoted by a pulse input to the transistor gate, regulates the scaling of the
output current to exceed that of the input current. When the supplementary input is
inactive, no scaling occurs. Additionally, the voltage Vl establishes an upper limit for
the current scaling. The supplementary input serves to facilitate the implementation
of learning algorithms, wherein it can be replaced with a logical combination of
various inputs.

3 Methodology for Neuromorphic Circuit Simulation

In this chapter, a synapse circuit was devised and executed for software simulation
employing LTspice electronic simulator software. LTspice is freely available for
download and used by students and researchers, offering a range of analysis options,
86 Fundamentals of Low-Power Neuromorphic Circuit Design with Spiking. . .

including DC and transient circuit analysis, which were utilized in crafting the circuit
discussed herein. The LTspice library encompasses numerous transistor options,
permitting the adjustment of parameters to suit specific needs. The parameters of the
transistors employed in this study are detailed in Tables 1, 2 and 3. Notably, a pulse-
type input voltage source serves as the input to the circuit, with the LTspice
facilitating the customization of various parameters such as the period, duty cycle,
rise time, fall time, delay and number of cycles in alignment with the circuit’s
requirements. Tables 1 and 2 delineate the parameter values for both the NMOS
and PMOS transistors, while Table 3 provides insight into the dimensions of the
transistors utilized.

3.1 Circuit Analysis and Testing

Numerous synapse circuits have been documented in the literature, with many
relying on the current mirror synapse due to its simplicity, albeit plagued by
concerns about gain, tau and other parameters. An alternative model introduced by
[4] employs exponential decay via log domain filtering [5], endowing the circuit
with characteristics akin to an LTI (linear time invariant) system. Additionally, the
CMOS synapse proposed by [4] shows independent controllability over the leakage
current, synaptic gain and decay time constant. This chapter aims to provide a
comprehensive exposition of the operation of the circuit, complemented by detailed
analysis and simulation outcomes.

3.2 Circuit Description

In this chapter, the synaptic circuit employed offers distinct control over the leakage
current, synaptic weight and decay time constant, thereby enabling precise manip-
ulation of synaptic behaviour. Utilizing current feedback, the circuit achieves a first-
order response characteristic. The architecture of five PMOS transistors, three
NMOS transistors, and a capacitor is delineated, as depicted in Fig. 8. The arrival
of an action potential is simulated by applying an inverted logic pulse with a narrow
width to the gate of transistor M1. Concurrently, the voltage Vτ governs the magni-
tude of current passing through transistor M7, denoted as Iτ, thereby dictating the
decay time constant of the output. The voltage Vw, on the other hand, regulates
synaptic strength. Transistor M6 serves to convert the voltage across the capacitor
into a corresponding current. The resulting current is channelled through a current
mirror formed by transistors M4 and M5, subsequently passing through a source
follower composed of transistors M3 and M4. The inhibitory synaptic current output
is derived from the drain current of transistor M8. Notably, all NMOS transistor bulk
terminals are grounded, while the bulk terminals of the PMOS transistors are
connected to Vdd, except for M3.
 3

Table 1 NMOS parameters

Cgd Cgd
Parameter Rg Rd Rs Vto Kp (max) (min) Cgs Cjo Is Rb Vds Ron Qg
Methodology for Neuromorphic Circuit Simulation

Value 3 4.8 m 3.6 m 0.8 0.7 0.7n 0.25n 1n 0.36n 0.1u 6m 20 12 m 18n
87
 88

Table 2 PMOS parameters

Cgd Cgd
Parameter Rg Rd Rs Vto Kp (max) (min) Cgs Cjo Is Rb Vds Ron Qg
Value 3 14 m 10 m -0.8 32 .5n 0.07n 0.9n 0.26n 26p 17 m -20 34 m 13n
Fundamentals of Low-Power Neuromorphic Circuit Design with Spiking. . .
4 Circuit Simulations 89

Table 3 Dimension require- PMOS NMOS

ments for the transistors
Part No. M1 M2 M3 M4 M5 M6 M7
L 1.6u 4u 4u 4u 4u 4u 4u
W 2.4u 8u 10u 4u 4u 4u 4u

Fig. 8 CMOS synapse

circuit model

4 Circuit Simulations

4.1 Subthreshold Characteristics

The transistors within the simulated circuit function within the subthreshold regime,
also known as the weak inversion region. In this operational mode, the relationship
between the current and voltage exhibits an exponential characteristic, succinctly
encapsulated by the drain current equation depicted in Eq. 9. This mode of operation
is pivotal in achieving the desired synaptic behaviour, facilitating nuanced control
over synaptic currents and ensuring efficient utilization of power resources:

k n vgs ð1 -k n Þvbs -vds

ids = Sn I 0n e vT
e vT
1 - e vT ð9Þ

where V T = kTq is the thermal voltage and S = WLnn . To determine the technology
current Ion, the gate and source terminals are connected to the ground, with the bulk
terminal being shorted to the source terminal. This configuration ensures a specific
operating condition where the transistor’s behaviour can be accurately characterized,
and its technology current can be reliably estimated. This step is fundamental in the
comprehensive analysis of transistor performance within the circuit context, provid-
ing essential insights into its operational dynamics and facilitating informed design
decisions where vbs = vgs = 0, and the dimensions are set to W = L = 10μ so that
S = 1. This results in the drain current equation being simplified to Eq. 10:
90 Fundamentals of Low-Power Neuromorphic Circuit Design with Spiking. . .

Fig. 9 Technology current for the NMOS. Approximately 1 nA when the threshold voltage VT
exceeds 0.1 V

V ds
ids = I 0n 1 - e - V T ð10Þ

The temperature was meticulously maintained at 300 K, a standard value in

electronic simulations, resulting in an approximate threshold voltage VT of approx-
imately 26 mV, where k represents Boltzmann’s constant and q denotes the elemen-
tary charge. Notably, when the drain-to-source voltage Vds exceeds approximately
4VT, or approximately 0.103 V, the exponential curve tends toward zero. This critical
threshold marks a significant transition point in the behaviour of the circuit,
highlighting the importance of meticulous voltage management in ensuring optimal
performance:

ids ≈ I 0n when V ds > 0:103V at 300 K ð11Þ

Based on the previously discussed equations and parameters, circuit simulations

were meticulously conducted to ascertain the technology current of both the PMOS
and NMOS transistors. The results, depicted in Figs. 9 and 10, indicate that Ion
approximately equals 1 nA for the NMOS transistor, while Iop approximately equals
18 nA for the PMOS transistor.

4.2 Synapses Strength and Time Constant

The decay time constant of the synaptic output is governed by the leakage current
passing through M7. The LTspice simulation of the circuit is depicted in Fig. 11,
which provides a visual representation of its functionality and characteristics. Fig-
ure 12 illustrates the synaptic output obtained from the drain of M6 in conjunction
with the input potential.
4 Circuit Simulations 91

Fig. 10 Technology current for the PMOS at Vds = 1 V. Ion≈18 nA when VT > 0.1 V

Fig. 11 LTspice-based circuit simulation

92 Fundamentals of Low-Power Neuromorphic Circuit Design with Spiking. . .

Fig. 12 The simulation results depicting the synapse current output alongside the pulse input for
Vτ = 0.2 and a pulse width of 10 ms

To validate the aforementioned results, a mathematical calculation is conducted

using Eq. 12 to determine the value of the current output, denoted as isyn (t):

k n v c ðt Þ
isyn ðt Þ = S8 I on e VT
ð12Þ

where S8 = 1 and kn = 0.7 (Table 3), Ion = 1 nA (Fig. 9) and

vc(t)jt = 3.117s = 635.559 mV (Fig. 13). Substituting these values gives:

0:7ð0:63555862Þ
isyn ðt Þ = 10 -9 e 0:02586492 ffi 0:295μA

This result closely matches the value of 0.299 μA observed in Fig. 12.
Figures 13 and 14 illustrate how the decay time constant changes proportionally
with Vτ while maintaining a constant VW at 3.75 V, with the pulse width set at 10 ms.
Figures 12, 13 and 14 illustrate the direct impact of Vτ on the time constant, with a
slight increase in magnitude observed concurrently. Meanwhile, the voltage VW
governs the synapse gain. As depicted in Fig. 15 below, with Vτ held constant at
0.25 V, the VW is varied. Notably, while the magnitude (gain) decreases with
increasing weight, the time constant remains consistent throughout.

4.3 Spike Train Response

Figure 16 depicts the summation behaviour and saturation phenomenon observed in

the incoming spike signals. The pulse widths of the spikes are uniformly set at 2 ms.
4 Circuit Simulations 93

Fig. 13 The synaptic current output for Vτ = 0.23

Fig. 14 The synaptic current output for Vτ = 0.25

This visual representation offers insight into how the synapse circuit handles the
accumulation of multiple spike inputs over time, highlighting any limitations or
saturation effects that may arise under specific conditions.
94 Fundamentals of Low-Power Neuromorphic Circuit Design with Spiking. . .

Fig. 15 Vw = 3.6 V

Fig. 16 This figure shows the input (blue) spikes and corresponding synaptic outputs (green)

5 Addressing Nonidealities and Optimizing Design

5.1 First-Order System

The analysis of the proposed design was simplified under two key assumptions.
First, it was assumed that all transistors operated solely in the subthreshold region.
However, this assumption does not hold for transistor M7 (as depicted in Fig. 11),
which occasionally operates in the triode region when Vc(t) < 4VT, which is
equivalent to 0.103 V. Consequently, the synapse current response may be faster
than initially anticipated. Second, the analysis disregarded all parasitic capacitances,
whose impact on the circuit’s output at low currents can be significant due to a
sluggish feedback response. Specifically, when Vc(t) is equivalent to 0 and an input
potential is introduced, the transconductances of the feedback loop transistors
typically range from 10-12 to 10-15, causing a delayed response from the loop.
Consequently, the voltage across the capacitor and hence the synaptic output
deviates from the behaviour of a true first-order system. To address this issue, a
small bias voltage was introduced at the source of M7, ensuring that the minimum
5 Addressing Nonidealities and Optimizing Design 95

Fig. 17 Inclusion of bias voltage in the modified circuit

value of Vc(t) corresponds to the bias voltage. This approach results in a small
leakage current for the synaptic output when no input potential is present. Alterna-
tively, this characteristic can be rectified by directly connecting the source of M6 to
the bias voltage. The modified circuit design is illustrated in the schematic provided
in Fig. 17.
The schematic in Fig. 17 illustrates the modified circuit design after the incorpo-
ration of a small bias voltage. This adjustment addresses the deviation from the ideal
behaviour observed in the original circuit. By introducing a bias voltage at the source
of transistor M7, the minimum value of Vc(t) is now fixed to the bias voltage,
ensuring consistent behaviour even in the absence of an input potential. Conse-
quently, the synaptic output current exhibits a small leakage current when no input
potential is applied, thus rectifying the previously observed nonideal characteristics.
This modification enhances the circuit’s performance, aligning it more closely with
the desired behaviour of a true first-order system.
96 Fundamentals of Low-Power Neuromorphic Circuit Design with Spiking. . .

Fig. 18 The integration of the bias current. Upon complete discharge of the capacitor, it diminishes
to 100 mV, aligning with the bias voltage value. The depicted period represents the entire discharge
cycle

Fig. 19 Synaptic exponential rise and decay

In the preceding design iteration, grounding the source of transistor M7 resulted in

a rapid increase in voltage across the capacitor, followed by exponential decay.
However, this behaviour deviates from the expected exponential rise outlined in
Eq. 13:

k n v c ð 0Þ S2 S3 S5 S8 I 2op kp ðvdd -vw Þ t -t j

isyn ðt Þ = S8 I 0n e VT
þ e VT 1 - e- τ ð13Þ
S4 S6 I τ

However, integrating the bias voltage effectively regulated the quiescent current,
as shown in Fig. 18.
As depicted in Fig. 19, setting the bias voltage Vs to 100 mV results in the
synaptic current exhibiting both an exponential increase and a decay. This config-
uration ensures minimal delay in the feedback loop, thereby providing a more
precise representation of the desired first-order dynamic characteristic.
5 Addressing Nonidealities and Optimizing Design 97

Fig. 20 Schematic view of circuit modifications for independent control over rising and falling
time constants

5.2 Biologically Plausible Circuit Model

As depicted in Fig. 20, the time constant for the synapse output is solely determined
by the current passing through M7. Nonetheless, biological synapses exhibit dual
time constants, with the rising phase typically considerably swifter than its decaying
counterpart. This poses a significant challenge in SNNs, particularly given the
narrow pulse width of the spike concerning the spike period. The subsequent circuit
design overcomes this obstacle by enabling independent regulation of both the rising
and falling time constants, thus enhancing the model’s fidelity to biological systems.
A supplementary current branch composed of transistors M8 and M9 runs parallel
to M7, providing a combined current of ITr + Iτ. In the absence of any input signal,
M8 and M9 act as open circuits, operating similarly to the configuration depicted in
Fig. 17. When the current passing through M7 increases, the steady-state value isyn
(1) diminishes because the additional current branch reduces the flow of current
responsible for charging the capacitor. Figure 21 shows the autonomous regulation
of both the rising and falling time constants. Moreover, the expression for the decay
time constant is derived from Eqs. 14 and 15:
98 Fundamentals of Low-Power Neuromorphic Circuit Design with Spiking. . .

Fig. 21 The impact of altering Vt2 on the decay time constant, with varying values for Vt2: 0.1, 0.25
and 0.4, arranged from top to bottom. The blue trace represents the input to M1, while the red trace
represents the input to M9

CV T
τd = ð14Þ
kn I τ

The rising time constant is given by:

CV T
τr = ð15Þ
kn ðI τr þ I τ Þ

6 Discussion

This book chapter presents an insightful exploration into the realm of energy-
efficient circuit design tailored for spiking neural networks (SNNs). While this
book chapter highlights several promising aspects of the proposed circuit design,
critical discussion is warranted to assess its strengths, limitations and potential
implications. One notable strength of the chapter lies in its emphasis on leveraging
analogue complementary metal-oxide-semiconductor (CMOS) technology for VLSI
implementation, aligning with the growing demand for low-power, high-perfor-
mance neuromorphic computing solutions. By capitalizing on the nonidealities of
real transistors, particularly their minimal leakage currents at subthreshold voltages,
the circuit demonstrates commendable power efficiency, a crucial attribute for
7 Future Tasks for Students/Researchers 99

practical deployment in resource-constrained environments. Moreover, the incorpo-

ration of user-adjustable time constants in synapse circuit design represents a
significant advancement, offering flexibility in modelling synaptic behaviour and
enhancing the adaptability of the system to diverse computational requirements. This
adaptability is further augmented by the introduction of an enhanced circuit design
featuring separate time constants for the rise and fall of synaptic potentials, mirroring
the distinct time constants observed in biological synapses. Such advancements
contribute to the biological plausibility of the circuit, a critical consideration in the
development of neuromorphic systems aimed at emulating the complexity of bio-
logical nervous systems. However, despite these advancements, several limitations
and challenges merit attention. One such limitation is the reliance on simulation-
based validation, which may not fully capture the complexities and nuances of real-
world implementation. While LTspice simulations provide valuable insights into
circuit performance, empirical validation through hardware prototyping and testing
is essential for assessing its practical feasibility and reliability. Furthermore, the
scalability of the proposed circuit design to large-scale neuromorphic systems
remains a pertinent concern, particularly regarding the integration of multiple syn-
apses and neurons within a cohesive network architecture. Additionally, the chapter
alludes to the potential power consumption of networks comprising multiple neurons
and synapses, hinting at the scalability challenges inherent in energy-efficient
neuromorphic circuit design. Addressing these challenges requires innovative
approaches to optimize circuit architectures, minimize power dissipation and ensure
robustness and scalability across varying computational loads. In conclusion, while
the chapter presents a compelling exploration of low-power neuromorphic SNN
circuit design, critical evaluation reveals both the strengths and limitations inherent
in the proposed approach. By addressing these challenges and refining circuit design
methodologies, researchers can pave the way for the development of more efficient,
scalable and biologically plausible neuromorphic computing systems, thereby
unlocking new frontiers in artificial intelligence and cognitive computing.

7 Future Tasks for Students/Researchers

The following activities are highly recommended and provide a comprehensive hands-on
experience for students to explore and experiment with circuit modelling of
neuromorphic circuits as low-power building blocks. It is highly recommended to
implement and simulate the following circuit for further extension. Some of the work
presented in [6–10] is highly recommended, and readers interested in accessing the
software code or seeking hands-on implementation are encouraged to contact the author.

Task: The following circuit can be implemented as an STDP (spike timing-

dependent plasticity) circuit as an extension to the circuits presented in this
book chapter. A possible design is presented below. It uses the circuits
presented earlier and could be used to feed the STDP circuit.

(continued)
100 Fundamentals of Low-Power Neuromorphic Circuit Design with Spiking. . .

V2
V11 V5

4.4
4.4 4.4
PULSE(0 4.7 0.001 1p 1p 0.9 1)
PULSE(0 4.7 0.001 1p 1p 0.99 1)

PULSE(0 4.7 0.001 1p 1p 0.99 1)

SpkIn3
AO6407 AO6407
AO6407 AO6407 AO6407 AO6407 AO6407
AO6407 M3 M4 AO6407
M26 M27 M1 M10 M11
V10

V4
M24 M8

AO6407
AO6407 AO6407
M7
M30 M14
V1
V9 V3
AO6407
AO6407 AO6407
M2 3.7
M25 3.75 M9 3.75

M5
M28 M12
AO6408
AO6408 AO6408

.tran 3
.tran 5 C1 .tran 5
C4 M6 C2
M29 M13
Vt6 M31 AO6408 0.1µ
AO6408 0.35µ AO6408 0.35µ
AO6408
0.25

Vt5

0.25

Vt2
0.3

PULSE(0 4.7 0.001 1p 1p 0.1 1)

spkIN4 M32
AO6408

Vs2

0.05

Acknowledgements The authors would like to thank M.Sc. thesis student(s) for contributing to
the experimental work conducted in the IoT laboratory within the School of Computing, Electronics
and Maths, Coventry University, UK. The work reported in this chapter was solely supervised by
Dr. Arfan Ghani at Coventry University, UK.

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