Sector: ECE STUDENT PROJECT SCHEME 2025-2026 Project Proposal On “FPGA Implementation of TFT Controller for Images" Submitted to ascst TAMIL NADU STATE COUNCIL FOR SCIENCE AND TECHNOLOGY (Department of Higher Education, Government of Tamil Nadu) Submitted by Anusree K Ijean SN Kamala Kannan S Kayalvizhi K Under the Supervision of Mrs. 8. Sasikala Dhanalakshmi Srinivasan Engineering CollegeTAMIL NADU STATE COUNCIL FOR SCIENCE AND V4 . TECHNOLOGY ( }) (Department of Higher Education, Government of Tamil Nadu) S Webs tn.gov.in APPLICATION FORMAT FOR STUDENT PROJECT PROPOSAL Please fill all the details in this MS word file. Convert to pdf file, get it approved from the project guide / head of the department and head of your institution. Keep ready the scanned pdf file of 1) Signed Application form 2) Declaration and Endorsement and fill-up the Google Form. Note: Handwritten proposals & multiple entries in Google form will not be accepted. 2025 Project Title: "FPGA Implementation of TFT Controller for Images" Sector: ECE & EEE Name of project guide: IName: Mrs. S. SASIKALA Department: Electronics and Communication Engineering |Email id: sasikala.s@dsengg.ac.in |Contact No.: 90039 77143 Name of Team Members: Ivear of Studying/Department: IV/ Electronics and Communication Engineering Email id: anusreekarunagaran4@gmail.com Mobile No:63802 03120 tame: IJEAN SN Wear of Studying/Department: IV/ Electronics and Communication Engineering [Email id: snijean41@gmail.com IMobile No.: 78260 14873 tame: KAMALA KANNAN S rear of Studying/Department: IV/ Electronics and Communication Engineering lemail id: subbukamal2004@gmail.com Mobile No.: 87780 51008 lwame: KAYALVIZHI K lvear of Studying/Department: IV/ Electronics and Communication Engineering |email id:-kayalkayalvizhi740@gmail.com Mobile No.: 74187 53246 Institution Details: Name of the Institution: Dhanalukshmi Srinivasan Engineering College Institution category: Self Finance Address: Thuraiyur Road,Perambalur-621212 ‘TNSCST-SPS 2025 Page?District: Perambalur : Pincode: 621 212 Introduction: The increasing use of Thin Film Transistor (TFT) displays in embedded systems and multimedia applications demands efficient controllers capable of| handling high-speed image data and strict timing requirements. Conventional microcontrolicr-based solutions often face limitations in mecting these demands, especially at higher resolutions. Field Programmable Gate Arrays (FPGAs), with their inherent parallelism and flexibility, provide an effective platform for implementing TFT controllers by enabling precise synchronization, real-time pixel data management, and customizable display features. This work presents the FPGA-based implementation of a TFT controller for image display, focusing on the, generation of synchronization signals, image buffering, and pixel mapping to achieve reliable and high-performance display control. Objectives of the project: * To design and implement a TFT display controller on an FPGA platform for real-time image display. = To generate the necessary timing signals such as horizontal sync, vertical syne, and pixel clock for proper TFT operation. * To develop an image buffering mechanism for efficient storage and transfer of pixel data. + To achieve accurate pixel mapping and color display on the TFT screen. + To demonstrate the advantages of FPGA-bascd implementation in terms of speed, parallelism, and flexibility compared to microcontroller-based| solutions. late the design by displaying static and/or dynamic images on the TFT display. Methodology: ‘The project methodology involves a structured approach to designing and implementing the TFT controller on an FPGA platform. First, the functional requirements of the TFT display, including resolution, color depth, and timing| specifications, are studied from the display datasheet. Based on these parameters, the synchronization signals such as horizontal syne, vertical sync, and pixel clock are generated using FPGA logic design. Next, an image buffering mechanism is| developed to store pixel data and supply it to the display in real-time. The controller! architecture is then designed in a Hardware Description Language (HDL) such as: Verilog or VHDL, and simulated using FPGA design tools to verify timing and functionality. After successful simulation, the design is synthesized, implemented, and programmed onto the FPGA hardware. Finally, testing and validation are carried out by displaying images on the TFT screen, analyzing performance in terms of synchronization accuracy, image clarity, and system reliability. Workplan: The project work plan begins with a literature review and requirement analysis to understand TFT display specifications and FPGA capabilities. This is followed by system design, where the controller architecture is defined, and HDL| ‘TNscst-ss 2025 Pagescoding is carried out for synchronization, buffering, and pixel mapping. The design is then simulated and verified before being synthesized and implemented on the FPGA board. Finally, the system is tested with the TFT display, analyzed for performance and optimized if necessary. 10. |” Expected Outcome of the project: ‘The expected outcome of this project is a fully functional FPGA-based TFT |controller capable of gencrating the required synchronization signals, managing image buffering, and displaying images accurately on a TFT screen. The system is janticipated to demonstrate real-time performance, stable image clarity, and lefficient resource utilization of the FPGA. Additionally, the project will highlight the \dvantages of FPGA-based implementation aver microcontroller-based solutions in terms of speed, flexibility, and reliability for display control applications. 22. Is the project proposed relevant to the Industry / Society? ‘Yes / No: Yes Details: ‘The project is highly relevant to both industry and society, as TFT displays are widely used in consumer clectronics, automotive dashboards, medical devices, industrial control panels, and portable embedded systems. The ability to implement a TFT controller on FPGA provides flexibility, real-time performance, and scalability, which are essential for industries requiring customizable and high-speed display| solutions. In society, such technology enables better human-machine interfaces, improved visualization in healthcare and education tools, and efficient multimedia| devices. 112. | Can the product or process developed in the project be taken up for filing @ Patent? Yes / No: No Prior Art search done? ‘Yes/No: No 13. | Budget details (The following is a tentative budget with break-up details; it is subject to change depending on the specific project requirements): Category Details Amount (INR) Materials FPGA Development Board, TFT Display 20,000 Module, Image Storage Device, Programming Cable Consumables | Interfacing connectors, jumper wires, cables Miscellaneous | Report pri utilities 1g, documentation, testing Total 24,552 TNSCST-SPS 2025 Pagesa4. Has a similar project been carried out in your college / elsewhere? If so furnish details of the previous project and highlight —_the novelty & improvements suggested in the present one: No 15. | Components: + FPGA Development Board — for implementing the TFT controller. * TFT Display Module — the target display for image output. + Image Storage Device (c.g., onboard flash memory / SD card module) — for| storing image data. Interfacing Connectors & Cables - for FPGA-TFT communication. PC / Laptop with FPGA Toolchain — for coding, simulation, synthesis, and| FPGA programming. * Programming Cable (JTAG/USB Blaster) - to load the HDL design into the FPGA. 16. | SPs Coordinator (Identified by the college Note: To be identified by the Head of the Institution. The project proposals must be submitted to TNSCST through SPS coordinator designated, Name: Dr. Chandran Masi Department: Food Technology Email id: foodtechhod@dsengg.ac.in Contact No.: 98940 93495 Note: Any mismatch between the scanned PDF, the details filled in the Google Form, and the hard copy as well as multiple submissions via the Godgle Form will lead to disqualification of the proposal. S Roe le qe Name & Signature of the the HOD \ Name & Signature of the Project Guide Spa JEGWARI WE.PRD, wISTE, Pitctpal / Head of the E HEAR eae natitatin with eal) Bis. J a7 alii or ctrcrronics AND PRINCIPAL, : ; canoe Pplecey cae eine NPR SEB ADIR ENCREERNG COUETE, ST inom orb ota eer oe 21212 ‘TNSCST-SFS 2025 PaarDECLARATION (From Project Students) We, the project team hereby declare that the information provided in the enclosed project proposal (Title of the Project: FPGA Implementation of TPT Controller forlmages, Branch: Electronies and Communication Engineering, College: Dhanalakshmt Srinivasan Engineering College are true and correct to the best of our knowledge and belief. We understand that the Tamil Nadu State Council for Science and Technology (TNSCST) will not entertain any changes to the project title or the names of the team members under any cireumstances, We further declare that the proposed project work is original, not copied or purchased from any source. We are committed to carrying out the project independently, with appropriate guidance from our faculty and Project guide, and by utilizing the facilities provided by our institution. We pledge to maintain academic integrity, avoid plagiarism, and work sincerely and diligently to execute and complete the project as proposed. We understand that any false, incorrect, or misleading information provided in this proposal may lead to disqualification or other consequences as deemed appropriate. We also authorize the sharing of the project details contained in this proposal with TNSCST, Chennai. We acknowledge that, if selected, our team is required to exhibit and present the project at the Annual ‘State-Level Seminar-cum-Exhibition organized by TNSCST. ‘The endorsement form for TNSCST, Chennai is enclosed herewith. Name of the students with Register Ne Signature with date Anusree K: 810422106011 ean 8: 1810422106041 KamalaKannanS: 810422106045 Hayalvizhi Ke 810422106050 bs ‘ature\ef HUD (with Seal) CrceaAs AL. Ze aA Mame & Signature of project Guide Name & 61 Dc. P. RAJESWAR), we PRD. wisTs,, ASSOCIATE PROFESSOR 8 HEAD DEPARTMENT OF ELECTRONW'S AN COMMUNICATION ENQINEEKING.. -OMAMALAKSHM SRINIVASAN BACN* tinct COLLEGE (AUTOMOMC#'s). —PERAMBALUR~e<~7+ ‘Twscar-srs 2025 PageENDORSEMENT (From College, cndorsement to bo taken in the Institution / Department Letter head) ‘This is to certify that the following students: 1. Ms. Anusree k, 2. Mr. tiean $ N, 3. Mr. 4 ‘amala Kannan S, |. Ms. Kayalvizhi k, fare bonafide final year students of the Department of Electronic and Communication Engineering, snrolicd in the B. E. degree program at our inctitution and it is certified that 2 copies of Utilization Certificate (UC) and final report along with seminar paper will be sent to the Council after completion of the project within specified timeline. We hereby confirm that, if the project proposal submitted by the above-mentioned students under the Student Project Scheme is selected by TNSCST, our institution will extend full support by providing the necessary laboratory, computer, and infrastructure facilities required for the successful execution of the project Furthermore, we assure that appropriate measures will be taken to ensure the project team participates in the Annual State-Level Seminer-cum-Exhibition (if eelected) and exhihits/demonstrates their penjeet Ifthe student team or project guide fails to submit the completed project report and the Utilisation Certificate within the timeline specified by TNSCST (if selected), our institution will ensure that the sanctioned project, amount is retuned to TNSCST. nature of Rimela signature of the Project Guide OD (with Wess) Principal / Tead of the (spsitcnd Dr. P_RAJESWARI. we pro. wisrermttstion (uth Seal pplece ASSOCIATE PPPESSOR & HEAD, PRINCIPAL ey cust, OREN fe CoeRTSRS pune : DDHANALAKSI ts CRINTVASAN ENGINEERING ‘ RETA COLLEGE. «1° 1NOMOUS), Y PERAMBr—un 621.212, TNscsT-sPs 2025, Page