Dr.

Kananbala Ray
KIIT, Deemed to be University

COMBINATIONAL LOGIC CIRCUIT

Combinational logic circuit is a circuit in which we combine the

different gates in the circuit, for example encoder, decoder,
multiplexer and de-multiplexer. Some of the characteristics of
combinational circuits are following −

 The output of combinational circuit at any instant of time,

depends only on the levels present at input terminals.
 The combinational circuit do not use any memory. The previous
state of input does not have any effect on the present state of the
circuit.
 A combinational circuit can have an n number of inputs and m
number of outputs.

Block diagram

Half Adder and Full Adder Circuit

An Adder is a device that can add binary bits. Half adder is a type of
digital circuit that performs the operation of additions of two number.
It is mainly designed for the addition of binary number, but they can
be used in various other applications like binary code
decimal, address decoding, table index calculation, etc. There are two
types of Adder, One is Half Adder, and another one is known as
Full Adder. The detail explanation of the two types of the adder is
given below.

Half Adder

There are two inputs and two outputs in a Half Adder. Inputs are
named as A and B, and the outputs are named as Sum (S) and Carry
(C). The Sum is X-OR of the input A and B. Carry is AND of the
input A and B. With the help of half adder, one can design a circuit
that is capable of performing simple addition with the help of logic
gates.

Block diagram
Let us first take a look at the addition of single bits.

0+0=0

0+1=1

1+0=1

1 + 1 = 10

These are the least possible single bit combinations. But the result for
1 + 1 =10. This problem can be solved with the help of an EX – OR
gate. The sum results can be re-written as a 2-bit output. Thus the
above combination can be written as

0 + 0 = 00

0 + 1 = 01

1 + 0 = 01

1 + 1 = 10

Here the output “1” of “10” becomes the carry-out. SUM is the
normal output and the CARRY is the carry-out.

The truth table of the half adder is shown below.

Inputs Outputs
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
HDL implementation: Verilog code of half adder in data flow
level
Application of Half Adder

Half Adder is used in the arithmetic logic unit of the processor of the
computer system for performing arithmetic operations of input.
Besides, it is also used in calculators for the addition of number, in
address decoding in processors, calculation of table indices etc.

The reason these simple binary adders are called Half Adders is that
there is no scope for them to add the carry bit from previous bit. This
is a major limitation of half adders when used as binary adders
especially in real time scenarios which involves addition of multiple
bits. To overcome this limitation, full adders are developed.
 Full Adder
The full adder is a little more difficult to implement than a half adder.
The main difference between a half adder and a full adder is that the
full adder has three inputs and two outputs. The two inputs are A and
B, and the third input is a carry input CIN. The output carry is
designated as COUT, and the normal output is designated as S(SUM).

Block diagram

The truth table of the Full Adder Circuit is shown below.

Inputs Outputs

A B CIN COUT S(SUM)

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1
 Inputs Outputs

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

The S(SUM) output is equal to 1 when only one input is equal to 1 or

when all three inputs are equal to 1.
S(SUM) =��(1,2,4,7)
The COUT output has a carry 1 if two or three inputs are equal to 1.
COUT= ��(3,5,6,7)

Thus, a full adder circuit can be implemented with the help of two
half adder circuits. The first half adder circuit will be used to add A
and B to produce a partial sum. The second half adder logic can be
used to add CIN to the sum produced by the first half adder circuit.
Finally, the output S is obtained.
If any of the half adder logic produces a carry, there will be an output
carry. Thus, COUT will be an OR function of the half adder CARRY
outputs.

SUM(S) =A̅B̅CIN+A̅BC̅IN+AB̅C̅IN+ABCIN
= A̅(B̅CIN+ BC̅IN)+A(B̅C̅IN+BCIN)
= A̅(B̅CIN+ BC̅IN)+A(B̅CIN+ BC̅IN)'
= A ⊕ B ⊕ CIN
Carry(COUT) = A̅BCIN+AB̅CIN+ABC̅IN+ABCIN
=AB(C̅IN+CIN)+ CIN (A̅B+AB̅)
=AB + (A ⊕ B). CIN
= AB + ( A̅. B + A. B̅). CIN
= AB + A̅. BCIN + A. B̅. CIN
= B (A + A̅. CIN) + A. B̅. CIN
= B [(A+ A̅) (A + CIN)] + A. B̅. CIN
= AB + BCIN + A. B̅. CIN
= AB + CIN (B + A. B̅)
= AB + CIN [(B + A) (B + B̅)]
= AB + BCIN + ACIN
Full adder using logic gates
 Full Adder using two half adders

Block diagram

Circuit diagram
HDL implementation: Verilog code for full adder in data flow level
module full_adder( input a,b,c, output sum,cout );

assign sum = (a ^ b ^ c );

assign cout = (a & b ) | (b & c) | (a & c); //cout=a & b | (a^b) & c;

endmodule

// Testbench for Full adder

module testbench_fulladder;
reg a,b,c;
wire sum,cout;
full_adder f1(a,b,c,sum,cout);
initial begin
a = 1'b0;
b = 1'b0;
c = 1'b0;
#20;
a = 1'b0;
b = 1'b0;
c = 1'b1;
#20;
a = 1'b0;
b = 1'b1;
c = 1'b0;
#20;
a = 1'b0;
b = 1'b1;
c = 1'b1;
#20;
a = 1'b1;
b = 1'b0;
c = 1'b0;
#20;
a = 1'b1;
b = 1'b0;
c = 1'b1;
#20;
a = 1'b1;
b = 1'b1;
c = 1'b0;
#20;
a = 1'b1;
b = 1'b1;
c = 1'b1;
#20;
$finish;
end endmodule
 Full adder using NAND gates

Full adder using NOR gates

Comparison Chart

Parameters Half Adder Full Adder

Half Adder is combinational logic Full Adder is a combinational circuit

Definition
circuit which adds two 1-bit digits. which adds three 1-bit digits.

Carry generated from previous Carry generated from previous

Carry Addition
addition is not added in next step. addition is added in the next step.

Hardware It consists of one EX-OR gate and It consists of two EX-OR, two AND
components one AND gate. gate and one OR gate.

Calculators, computers, digital Multiple bit addition, digital

Applications
measuring devices etc. processors etc.

N-Bit Parallel Adder

The Full Adder is capable of adding only two single digit binary
number along with a carry input. But in practical we need to add
binary numbers which are much longer than just one bit. To add two
n-bit binary numbers we need to use the n-bit parallel adder. It uses a
number of full adders in cascade. The carry output of the previous full
adder is connected to carry input of the next full adder.

4 Bit Parallel binary Adder(Asynchronous Ripple-Carry Adder)

A binary adder is a digital circuit that produces the arithmetic sum of
two binary numbers.
A binary adder can be constructed with full adders connected in
cascade with the output carry form each full adder connected to the
input carry of the next full adder in the chain.
The four-bit adder is a typical example of a standard component .It
can be used in many application involving arithmetic operations.
The input carry to the adder is C0 and it ripples through the full adders
to the output carry C4 .
n- bit binary adder requires n full adders.

In the block diagram shown below, A1 and B1 represent the LSB of

the four bit words A and B. Hence Full Adder-1 is the lowest stage.
Hence its Cin(C0) has been permanently made 0. The rest of the
connections are exactly same as those of n-bit parallel adder is shown
in fig. The four bit parallel adder is a very common logic circuit.

The inter connection of 4 full adder in 4bit parallel adder is shown

below,
Let us examine the justification of the above circuit by taking an
example of addition of two 4 bit binary numbers.
Example: Add 1011 with 1101.

As there is no previous carry C0 = 0.

Therefore, final result of the addition would be

HDL implementation: Verilog code for parallel binary adder in
data flow level
module four_bit_adder (a,b,sum);

input [3:0]a;
input [3:0]b;
output [4:0]sum;

wire cout0,cout1,cout2;

full_adder full_adder_0(a[0],b[0],0,sum[0],cout0);
full_adder full_adder_1(a[1],b[1],cout0,sum[1],cout1);
full_adder full_adder_2(a[2],b[2],cout1,sum[2],cout2);
full_adder full_adder_3(a[3],b[3],cout2,sum[3],sum[4]);

endmodule

module full_adder (a,b,cin,sum,cout);

input a;
input b;
input cin;
output sum;
output cout;
assign sum = (a ^ b ^ cin );
assign cout = (a & b ) | (b & cin) | (a & cin); //cout=a & b | (a^b) & cin;
endmodule

Half Subtractor

Half subtractor is a combinational circuit with two inputs and two

outputs (difference and borrow). It produces the difference between
the two binary bits at the input and also produces an output (Borrow)
to indicate if a 1 has been borrowed. In the subtraction (A-B), A is
called as Minuend bit and B is called as Subtrahend bit.
 Truth Table
Inputs Outputs

A B D (Difference) b(Borrow)

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

Circuit Diagram
HDL implementation: Verilog code for half subtractor in data
flow level
module half_sub(d, bout, a, b);
input a,b;
output d,bout; // difference and borrow
assign d = a^b;
assign bout = (~a & b) ;
endmodule
Implementation of Half Subtractor using NAND gates :
 Implementation of Half Subtractor using NOR gates :

Full Subtractor
The disadvantage of a half subtractor is overcome by full subtractor.
The full subtractor is a combinational circuit with three inputs A,B,C
and two output D and C'. A is the 'minuend', B is 'subtrahend', C is the
'borrow' produced by the previous stage, D is the difference output
and C' is the borrow output.

A full subtractor is a combinational circuit that performs subtraction

of two bits, one is minuend and other is subtrahend, taking into
account borrow of the previous adjacent lower minuend bit. This
circuit has three inputs and two outputs. The three inputs A, B and
Bin, denote the minuend, subtrahend, and previous borrow,
respectively. The two outputs, D and Bout represent the difference
and output borrow, respectively.
From above table we can draw the K-Map as shown for “difference”
and “borrow”.
HDL implementation: Verilog code for full subtractor in data
flow level
module full_adder( input a,b,c, output d,bout );

assign d = (a ^ b ^ bin );

assign bout = (~a & b ) | (~a & bin) | (b & bin); //bout=~a & b |
~(a^b) & bin;

endmodule

Implementation of Full Subtractor using Half Subtractors –

2 Half Subtractors and an OR gate is required to implement a Full
Subtractor.
Full Subtractor using NAND gates and NOR gates.
 BINARY ADDER/SUBTRACTOR

HW: Implement combined adder-subtractor block using XNOR gates

only(minimum)?
 Decoder
A decoder is a combinational logic circuit. It has n input and to a
maximum m = 2n outputs. Only one output line is activated for each
one of the possible combinations of inputs. In other words, we can say
that a decoder identifies or recognizes or detects a particular code. For
each of these input combinations ,only one of the m outputs will be
active (HIGH), all other outputs will remain inactive(LOW). Some
decoders are designed to produce active low output, while all the
other outputs remain High. Decoder is identical to a de-multiplexer
without any data input. It performs operations which are exactly
opposite to those of an encoder.

Block diagram

Examples of Decoders are following.

 Code converters
 BCD to seven segment decoders
 Nixie tube decoders
 Relay actuator
2 to 4 Line Decoder

The block diagram of 2 to 4 line decoder is shown in the fig. A and B

are the two inputs where Q0 through Q3 are the four outputs. Truth
table explains the operations of a decoder. It shows that each output is
1 for only a specific combination of inputs.

Block diagram
HDL implementation: Verilog code for 2 to 4 line active high
decoder using data flow modeling
module decoder_2_4(a,b,w,x,y,z);

output w,x,y,z;
input a,b;
assign w = (~a) & (~b);
assign x = (~a) & b;
assign y = a & (~b);
assign z = a & b;
endmodule

Test Bench
module decoder_2_4_test;
reg a,b;
wire w,x,y,z;
decoder_2_4 decoder_2_4_test(a,b,w,x,y,z);
initial
begin
a=0; b=0;
#20 a=0; b=1;
#20 a=1; b=0;
#20 a=1; b=1;
end
endmodule
Active LOW decoder
In many applications, decoders are designed with active low output.
In such a case AND gates are replaced by NAND gates. Fig. shows
the active LOW 2 to 4 line decoder.

2 to 4 line Decoder using enable i/p

Let 2 to 4 line Decoder has two inputs A1 & A0 and four outputs Y3,
Y2, Y1 & Y0. The block diagram of 2 to 4 line decoder is shown in
the following figure.

One of these four outputs will be ‘1’ for each combination of inputs
when enable, E is ‘1’. The Truth table of 2 to 4 decoder is shown
below
 Enable Inputs Outputs
E A1 A 0 Y 3 Y 2 Y 1 Y 0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

From Truth table, we can write the Boolean functions for each output
as Y3=E.A1.A0

Y2=E.A1.A0′
Y1=E.A1′.A0
Y0=E.A1′.A0′

Each output is having one product term. So, there are four product
terms in total. We can implement these four product terms by using
four AND gates having three inputs each & two inverters. The circuit
diagram of 2 to 4 decoder is shown in the following figure.
2 to 4 line Active-low Decoder using enable i/p
Truth Table:

HDL implementation: Verilog code for 2 to 4 line active low

decoder using data flow modeling
module decoder24_assign(en,a,b,y);
// declare input and output ports
input en,a,b;
output [3:0]y;

// supportive connection required

wire enb,na,nb;
assign enb = ~en;
assign na = ~a;
 assign nb = ~b;

// assign output value by referring to logic diagram

assign y[0] = ~(enb&na&nb);
assign y[1] = ~(enb&na&b);
assign y[2] = ~(enb&a&nb);
assign y[3] = ~(enb&a&b);

endmodule

3 to 8 line Decoder
 A 3 to 8 decoder has three inputs (A,B,C) and eight outputs (DO
to D7).
 Based on the 3 inputs one of the eight outputs is selected.
 The truth table for 3 to 8 decoder is shown in table
 From the truth table, it is seen that only one of eight outputs
(DO to D7) is selected based on three select inputs.
 From the truth table, the logic expressions for outputs can be
written as follows:
Truth table of 3 to 8 decoder.

| Inputs | Outputs

A B C D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

 Using the above expressions, the circuit of a 3 to 8 decoder can

be implemented using three NOT gates and eight 3-input AND
gates as shown in fig .
 The three inputs A, B and C are decoded into eight outputs, each
output representing one of the midterms of the 3-input variables.
 The three inverters provide the complement of the inputs and
each one of the weight AND gates generates one of the
minterms.
 This decoder can be used for decoding any 3-bit code to provide
eight outputs, corresponding to eight different combinations of
the input code.
 This is also called a 1 of 8 decoder, since only one of eight
output lines is HIGH for a particular input combination.
Function Implementation Using Decoder
Home work: Implement full subtractor using decoder
NB: Connect the output line 6 of the decoder to OR gate of the function f2

The decoder NAND B will yield the function F(A,B,C) = A+B’+C.

Encoders
An encoder is a combinational circuit that converts binary information
in the form of a 2N input lines into N output lines, which represent N
bit code for the input. For simple encoders, it is assumed that only one
input line is active at a time. It is a combinational logic circuit that
performs the reverse operation of the decoder.

Examples of Encoders are following.

 Priority encoders
 Decimal to BCD encoder
 Octal to binary encoder
 Hexadecimal to binary encoder

4 : 2 Encoder –

The 4 to 2 Encoder consists of four inputs Y3, Y2, Y1 & Y0 and

two outputs A1 & A0. At any time, only one of these 4 inputs can be
‘1’ in order to get the respective binary code at the output. The figure
below shows the logic symbol of 4 to 2 encoder :
The Truth table of 4 to 2 encoder is as follows :

Logical expression for A1 and A0 :

A1 = Y3 + Y2

A0 = Y3 + Y1

The above two Boolean functions A1 and A0 can be implemented

using two input OR gates :
As an example, let’s consider Octal to Binary encoder. As shown in
the following figure, an octal-to-binary encoder takes 8 input lines
and generates 3 output lines.

Truth Table –

D7 D6 D5 D4 D3 D2 D1 D0 X Y Z
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

As seen from the truth table, the output is 000 when D0 is active; 001
when D1 is active; 010 when D2 is active and so on.
Implementation –
From the truth table, the output line Z is active when the input octal
digit is 1, 3, 5 or 7. Similarly, Y is 1 when input octal digit is 2, 3, 6 or
7 and X is 1 for input octal digits 4, 5, 6 or 7. Hence, the Boolean
functions would be:

X = D4 + D5 + D6 + D7
Y = D2 +D3 + D6 + D7
Z = D1 + D3 + D5 + D7
Hence, the encoder can be realised with OR gates as follows:

Priority Encoder–

A priority encoder is an encoder circuit in which inputs are given

priorities. When more than one inputs are active at the same time, the
input with higher priority takes precedence and the output
corresponding to that is generated.
Let us consider the 4 to 2 priority encoder as an example.

From the truth table, we see that when all inputs are 0, our V bit or the
valid bit is zero and outputs are not used. The x’s in the table show
the don’t care condition, i.e, it may either be 0 or 1. Here, D3 has
highest priority, therefore, whatever be the other inputs, when D3 is
high, output has to be 11. And D0 has the lowest priority, therefore
the output would be 00 only when D0 is high and the other input lines
are low. Similarly, D2 has higher priority over D1 and D0 but lower
than D3 therefore the output would be 10 only when D2 is high and
D3 are low (D0 & D1 are don’t care).

Priority order D3>D2>D1>D0

Truth Table –

D3 D2 D1 D0 X Y V
0 0 0 0 x x 0
0 0 0 1 0 0 1
0 0 1 x 0 1 1
0 1 x x 1 0 1
1 x x x 1 1 1

From the above truth table we can write

X=D3+D̅3D2=D3+D2
Y=D3+D̅3D̅2D1=D3+D̅2D1
V = D0 + D1 + D2 + D3
Implementation –

It can clearly be seen that the condition for valid bit to be 1 is that at
least any one of the inputs should be high. Hence,

K.map for X K.map for Y

X= D3+ D2
Y = D3+ D̅2 D1
Hence, the priority 4-to-2 encoder can be realized as follows:

Uses of Encoders –

1. Encoders are very common electronic circuits used in all digital

systems.
2. Encoders are used to translate the decimal values to the binary
in order to perform the binary functions such as addition,
subtraction, multiplication, etc.
 3. Other applications especially for Priority Encoders may include
detecting interrupts in microprocessor applications.

Multiplexers

Multiplexer is a combinational circuit that has maximum of 2n data

inputs, ‘n’ selection lines and single output line. The multiplexer or
MUX is a digital switch, also called as data selector. A digital
multiplexer or data selector Multiplexer is a logic circuit that accepts
several digital data inputs and selects one of them at a time to pass on
to the output. Thus multiplexer transmits several signals on the same
line. The purpose of the multiplexer is to save on the number of
wires/lines needed to transmit data from multiple sources. In the block
diagram E is called the strobe or enable input which is useful for the
cascading.

Since there are ‘n’ selection lines, there will be 2n possible

combinations of zeros and ones. So, each combination will select only
one data input. Multiplexer is also called as MUX.

Block diagram

Multiplexers come in multiple variations

  2 : 1 multiplexer
 4 : 1 multiplexer
 16 : 1 multiplexer
 32 : 1 multiplexer

Truth table for 2×1 mux is given below:

Input Output

I0 I1 S Out

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 1
HDL implementation: Verilog code for 2:1 MUX using gate-level
modeling
module mux2x1(out,I0,I1,s);

input I0,I1,s;

wire and_1,and_2,s_c;

output out;

not (s_c,s);

and (and_1,I0,s_c);

and (and_2,I1,s);

or (out,and_1,and_2);

endmodule

4x1 Multiplexer

4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines
s1 & s0 and one output Y. The block diagram of 4X1 MUX is shown
below.

The block diagram of 4x1 Multiplexer

One of these 4 inputs will be connected to the output based on the

combination of inputs present at these two selection lines.
Truth table of 4x1 Multiplexer is shown below.

Selection Lines Output

S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

From Truth table, we can directly write the Boolean function for
output, Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3

We can implement this Boolean function using Inverters, AND gates

& OR gate. The circuit diagram of 4x1 multiplexer is shown in the
following figure.

Implementation of Higher-order Multiplexers.

4x1 Multiplexer using 2x1 Multiplexer

HDL implementation: Verilog code for 4:1 MUX using 2:1 MUX
using gate-level modeling
module mux4x2(out,i0,i1,i2,i3,s1,s0);

input i0,i1,i2,i3,s1,s0;

output out;

wire mux1,mux2;

mux2x1 mux_1(mux1,i0,i1,s0);

mux2x1 mux_2(mux2,i2,i3,s0);

mux2x1 mux_3(out,mux1,mux2,s1);

endmodule
Test Bench code for 4×1 Mux

This 4×1 mux is tested for selective inputs given below:

i0 i1 i2 i3 S1 S0 out

1 0 1 1 0 1 0

0 1 0 0 0 1 1

0 0 1 0 1 0 1

0 0 0 1 1 1 1

1 0 0 0 0 0 1

timescale 1ns/1ns
module mux4x1_tb;
wire t_out;
reg t_a, t_b, t_c, t_d, t_s1, t_s0;
mux4x1 my_4x1_mux( t_a, t_b, t_c, t_d, t_s1, t_s0, t_out );
initial
begin
// 1
t_a = 1'b1;
t_b = 1'b0;
t_c = 1'b1;
t_d = 1'b1;
t_s1 = 1'b0;
t_s0 = 1'b1;

#5 //2
t_a = 1'b0;
t_b = 1'b1;
t_c = 1'b0;
t_d = 1'b0;
t_s1 = 1'b0;
t_s0 = 1'b1;

#5 //3
t_a = 1'b0;
t_b = 1'b0;
t_c = 1'b1;
t_d = 1'b0;
t_s1 = 1'b1;
t_s0 = 1'b0;

#5 //4
t_a = 1'b0;
t_b = 1'b0;
t_c = 1'b0;
t_d = 1'b1;
t_s1 = 1'b1;
t_s0 = 1'b1;

#5 //5
t_a = 1'b1;
t_b = 1'b0;
t_c = 1'b0;
t_d = 1'b0;
t_s1 = 1'b0;
t_s0 = 1'b0;

end
endmodule

Example-
The output logic equation Y of the 4×1 multiplexer shown in figure is:

Solution:

Y = A’B’C + A’BC +AB’C’ + ABC’

= A’C(B’+B) + AC’(B’+B)

= A’C + AC’

= A ⊕ C
Function implementation using multiplexers:

Q1) Implement the function F=ABC using multiplexer.

Demultiplexers

A demultiplexer performs the reverse operation of a multiplexer i.e. it

receives one input and distributes it over several outputs. It has only
one input, n outputs, m select input. At a time only one output line is
selected by the select lines and the input is transmitted to the selected
output line. A demultiplexer is equivalent to a single pole multiple
way switch as shown in fig.

Demultiplexers comes in multiple variations.

 1 : 2 demultiplexer
 1 : 4 demultiplexer
 1 : 8 demultiplexer
 1 : 16 demultiplexer
1-to-2 Demultiplexer

A 1-to-2 demultiplexer consists of one input line, two output lines and
one select line. The signal on the select line helps to switch the input
to one of the two outputs. The figure below shows the block diagram
of a 1-to-2 demultiplexer with additional enable input.

In the figure, there are only two possible ways to connect the input to
output lines, thus only one select signal is enough to do the
demultiplexing operation. When the select input is low, then the input
will be passed to Y0 and if the select input is high then the input will
be passed to Y1.

The truth table of a 1-to-2 demultiplexer is shown below in which the

input is routed to Y0 and Y1 depends on the value of select input S. In
the table output Y1 is active when the combination of select line and
enable input line are active high, i.e., S,E = 1,1.

Therefore, the output Y1 = S,E and similarly the output Y0 is equal to

S̅,E=0,1.
 Truth Table

From the above truth table, the logic diagram of this demultiplexer
can be designed by using two AND gates and one NOT gate as shown
in below figure. When the select lines S=0, 1st AND gate is enabled
while 2nd AND gate is disabled.

Then, the data from the input flows to the output line Y0. Similarly,
when S=1, 2nd AND gate is enabled and 1st AND gate is disabled,
thus data is passed to the Y1 output.
1-to-4 Demultiplexer

The 1 to 4 demultiplexer consists of one input, four outputs, and two

control lines to make selections. The below diagram shows the
circuit of 1 to 4 demultiplexer.

A 1-to-4 demultiplexer has a single input (D), two selection lines (S1
and S0) and four outputs (Y0 to Y3). The input data goes to any one
of the four outputs at a given time for a particular combination of
select lines.

This demultiplexer is also called as a 2-to-4 demultiplexer which

means that two select lines and 4 output lines. The block diagram of
1:4 DEMUX is shown below.

The truth table of this type of demultiplexer is given below. From the
truth table it is clear that, when S1=0 and S0= 0, the data input is
connected to output Y0 and when S1= 0 and s0=1, then the data input
is connected to output Y1.

Similarly, other outputs are connected to the input for other two
combinations of select lines.
Truth Table

From the table, the output logic can be expressed as min terms and are
given below.

Where D is the input data, Y0 to Y3 are output lines and S0 & S1 are
select lines.

From the above Boolean expressions, a 1-to-4 demultiplexer can be

implemented by using four 3-input AND gates and two NOT gates as
shown in figure below. The two selection lines enable the particular
gate at a time.

So depends on the combination of select inputs, input data is passed

through the selected gate to the associated output.
1 to 8 Demultiplexer

A 1 to 8 demultiplexer consists of one input line, 8 output lines and 3

select lines. Let the input be D, S1 and S2 are two select lines and
eight outputs from Y0 to Y7. It is also called as 3 to 8 demux because
of the 3 selection lines. Below is the block diagram of 1 to 8 demux.
Truth Table

The below is the truth table for 1 to 8 demultiplexer. It tells the

functionality of the demux, like, if S1S2S0=000, then the output is seen
at Y0 and so on.

Using the above truth table the logic diagram of the demultiplexer is
implemented using eight AND and three NOT gates. The different
combinations of the select lines select one AND gate at given time,
such that data input will be seen at a particular output.
Applications of Demultiplexer
Since the demultiplexers are used to select or enable the one signal
out of many, these are extensively used in microprocessor or
computer control systems such as

 Selecting different IO devices for data transfer

 Choosing different banks of memory
 Depends on the address, enabling different rows of memory
chips
 Enabling different functional units.

Other than these, demultiplexers can be found in a wide variety of

application such as

 Synchronous data transmission systems

 Boolean function implementation (as we discussed full
subtractor function above)
 Data acquisition systems
 Combinational circuit design
 Automatic test equipment systems
 Security monitoring systems (for selecting a particular
surveillance camera at a time), etc.

Difference between Multiplexer and Demultiplexer:

Multiplexer Demultiplexer
Multiplexer processes the Demultiplexer receives digital
digital information from information from a single source
various sources into a single and converts it into several
source. sources
It is known as Data Selector It is known as Data Distributor
Multiplexer is a digital
Demultiplexer is a digital circuit
switch
It follows combinational It also follows combinational
logic type logic type
It has n data input It has single data input
It has a single data output It has n data outputs
 Multiplexer Demultiplexer
It works on many to one It works on one to many
operational principle operational principle
In time division In time division Multiplexing,
Multiplexing, multiplexer is demultiplexer is used at the
used at the transmitter end receiver end
Difference between Decoder and Demultiplexer:

S.No. Comparison Decoder Demultiplexer

These are Logic
It is a Combination
circuit which
circuit which routes a
decodes an
1. Basic single input signal to
encrypted input
one of several output
stream from one to
signals.
another format.
n number of input
n number of select
lines and 2n
2. Input/Output lines and 2n number of
number of output
output lines.
lines.
3. Inverse of Encoder. Multiplexer.
In Detection of In Distribution of the
4. Application
bits, data encoding. data, switching.
It is used for
It is used as a routing
changing the
device to route the
format of the
5. Use data coming from one
instruction in the
signal into multiple
machine specific
signals.
language.
6. Select Lines Not contains. Contains.
Employed in data-
Majorly
intensive applications
implemented in the
7. Implementation where data need to be
networking
changed into another
application.
form.
Difference between of Multiplexer and Decoder :

S.NO. Multiplexer Decoder

MUX accepts several It takes n input binary code
1. inputs and allow only one and convert it into a
data output. corresponding outputs.
Select line are used to Enable inputs are used to
2. select data inputs and control the operation of the
allow only one of them. decoder.
It can be used in data
Application of decoder is in
3. routing and waveform
Decimal to BCD encoder.
generation.
Multiplexer converts the
Decoder converts binary
4. unary code into binary
code into unary..
code