MICROPROCESSORS

AND
MICROCONTROLLERS

Text Book
Advanced Microprocessors and Peripherals
A K RAY and K M Bhurchandi
Tata McGraw-Hill Publications, 2000
 8086 Microprocessor
• 8086 Microprocessor is an enhanced version of
8085Microprocessor that was designed by Intel in 1976.
• It is a 16-bit Microprocessor having 20 address lines and16
data lines that provides up to 1MB storage.
• It consists of powerful instruction set, which provides
operations like multiplication and division easily.
• It supports two modes of operation, i.e. Maximum mode
and Minimum mode. Maximum mode is suitable for system
having multiple processors and Minimum mode is suitable
for system having a single processor.
• It was the first 16-bit processor having 16-bit ALU, 16-bit
registers, internal data bus, and 16-bit external data bus
resulting in faster processing.
 Internal Architecture 8086

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
3
8086 Microprocessor
Bus Interface Unit (BIU)

Dedicated Adder to generate

20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Segment Registers >> 4

 8086 Microprocessor
Execution Unit (EU)

EU decodes and
executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 5
DX can be used as DH and DL
Internal Architecture of 8086
• 8086 has two blocks BIU and EU.
• The BIU performs all bus operations such as instruction
fetching, reading and writing operands for memory and
calculating the addresses of the memory operands. The
instruction bytes are transferred to the instruction queue.
• EU executes instructions from the instruction system byte
queue.
• Both units operate asynchronously to give the 8086 an
overlapping instruction fetch and execution mechanism
which is called as Pipelining. This results in efficient use of
the system bus and system performance.
• BIU contains Instruction queue, Segment registers,
Instruction pointer, Address adder.
• EU contains Control circuitry, Instruction decoder, ALU,
Pointer and Index register, Flag register.
Register organization of 8086
General Purpose Index
AH AL
BP
AX

SP
BH BL
BX
SI

CH CL
DI
CX

DH DL
DX Segment

CS

Status and Control SS

Flags DS

IP ES
 1.General Purpose Registers

AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register

• Normally used for storing temporary results

• Each of the registers is 16 bits wide (AX, BX, CX, DX)
• Can be accessed as either 16 or 8 bits AX, AH, AL
• AX
• Accumulator Register
• Preferred register to use in arithmetic, logic and data transfer instructions because
it generates the shortest Machine Language Code
• Must be used in multiplication and division operations
• Must also be used in I/O operations

• BX
– Base Register
– Also serves as an address register
• CX
 Count register
 Used as a loop counter
 Used in shift and rotate operations

• DX
• Data register
• Used in multiplication and division
• Also used in I/O operations
 2. Pointer and Index Registers

Stack Pointer (SP) is a 16-bit register pointing to program stack

.
Base Pointer (BP) is a 16-bit register pointing to data in stack
segment. BP register is usually used for based, based indexed or
register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based
indexed and register indirect addressing, as well as a source data
address in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed,
based indexed and register indirect addressing, as well as a
destination data address in string manipulation instructions.
Instruction Pointer (IP) is a 16-bit register.
 3. Flag Registers

Flags Register is a 16-bit register containing 9 one bit flags.

Overflow Flag (OF) - set if the result is too large positive number, or is too small
negative number to fit into destination operand.
Direction Flag (DF) - if set then string manipulation instructions will auto-
decrement index registers. If cleared then the index registers will be auto-
incremented.
Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
Single-step Flag (TF) - if set then single-step interrupt will occur after the next
instruction

Sign Flag (SF) - set if the most significant bit of the result to Zero.
Zero Flag (ZF) - set if the result is zero.
Auxiliary carry Flag (AF) - set if there was a carry to or borrow from bits 3-4 in the
AL register.
Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the
result is even.
Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit
during last result calculation.
 4. Segment Registers

• Code segment (CS) is a 16-bit register containing address of 64

KB segment with processor instructions. The processor uses CS
segment for all accesses to instructions referenced by instruction
pointer (IP) register. CS register cannot be changed directly. The
CS register is automatically updated during far jump, far call and
far return instructions.

• Stack segment (SS) is a 16-bit register containing address of

64KB segment with program stack. By default, the processor
assumes that all data referenced by the stack pointer (SP) and
base pointer (BP) registers is located in the stack segment. SS
register can be changed directly using POP instruction.

• Data segment (DS) is a 16-bit register containing address of

64KB segment with program data. By default, the processor
assumes that all data referenced by general registers (AX, BX,
CX, DX) and index register (SI, DI) is located in the data
segment. DS register can be changed directly using POP and
LDS instructions.
 Memory Organization

• The available memory of 8086 is divided into number of

logical segments.
• The complete 1 MB memory of 8086 is divided into 16
logical segments. Each segment thus contains 64KB of
memory.
• There are 4 segment registers, Code segment (CS), Data
segment (DS), Stack segment (SS) and Extra segment
(ES). Each segment is 64 KB in size and addressed by
one of the segment registers.
• The 16 bit contents of the segment register points to the
starting location of segment register. (Segment address/
base address)
• To address the specific memory location, it needs a
offset address (displacement) which is 16 bit long.
• The address of segment address (base address) may
assigned as 0000H to F000H respectively.
• The offset address values from 0000H to FFFFH so that
the physical address (20 bit long) of 8086 ranges from
00000H to FFFFFH
• The advantage of segmented memory is that the memory
capacity of 8086 is 1 MB with physical address of 20
bit long but the actual address handled are of 16 bit.
• It allows the placing of code, data and stack portions of
same program in different parts ( Segments) of memory.
• It permits a provision for relocation of program is done.
 Addressing modes of 8086
Addressing modes indicates a way of locating data or operands.
This modes describe the types of operands and the way they
accessed for executing instruction.
1. Immediate addressing mode
2. Direct addressing mode
3. Register addressing mode
4. Register Indirect addressing mode
5. Indexed addressing mode
6. Register relative addressing mode
7. Based indexed addressing mode
8. Relative Based indexed addressing mode
1: Immediate addressing mode

 In this type of mode, immediate data is part of

instruction and appears in the form of
successive byte or bytes

10 14H
MOV AX,1014H
AX
 2: Direct addressing mode

 In this type of addressing mode a 16-bit memory

address is directly specified in the instruction as a
part of it.

Memory
22 5000
33 5001
MOV AX, [5000H]
5002

AX
3: Register addressing mode

 In this type of addressing mode, the data is stored in the

register and it can be a 8-bit or 16-bit register. All the registers,
except IP, may be used in this mode.

10 14 BX
MOV AL, BL BH BL
MOV AX, BX
FF 33 AX
AH AL
4: Register Indirect addressing mode

 The address of the memory location which

contains data or operand is determined in a
indirect way, using the offset register.

Memory
22 5000
AX
33 5001
MOV AX, [BX] 5002

BX
50 00
5: Indexed addressing mode

 In this addressing mode, offset of the operand

is stored in one of the index registers. DS is the
default segment for index register SI and DI.

Memory
22 5000
AX
33 5001
MOV AX,[SI] 5002

50 00 SI
6: Register relative addressing mode

 In this mode, the data is available at an effective

address formed by adding an 8-bit or 16-bit
displacement with the content of any one of the
registers BX, BP, SI and DI in the default (either DS or
ES) segment.
Memory
44 5050
AX 33 5051
MOV AX, 50H[BX] 5052

50 00 + 50H = 5050H
Final
Index
BX Offset Address
7: Based indexed addressing mode

 In this mode the effective address is formed by

adding content of a base register (any one of BX or
BP) to the content of an index register (SI or DI).
Default segment register DS.
12 3000
MOV AX, [BX] [SI] AX
34 3001
3002

10 00 + 20 00 = 3000H
Final
BX SI Index
Address
8: Relatively based indexed addressing
mode

 In the effective address is formed by adding an 8 or

16-bit displacement with sum of contents of any
one of the base registers (BX or BP) and any one of
the index registers, in a default segment.
12 3050
MOV AX,50H[BX][SI] AX
34 3051
3052

50H + 10 00 20 00 = 3050H
Final
BX SI Index
Address
 Interrupts in 8086
• Interrupt is the method of creating a temporary halt during
program execution and allows peripheral devices to access the
microprocessor.
• The microprocessor responds to that interrupt with an ISR
(Interrupt Service Routine), which is a short program to instruct
the microprocessor on how to handle the interrupt.
• The following image shows the types of interrupts in a 8086
microprocessor
Hardware Interrupts:
• Hardware interrupt is caused by any peripheral device by
sending a signal through a specified pin to the microprocessor.
• The 8086 has two hardware interrupt pins, i.e. NMI and INTR.
NMI is a non-maskable interrupt and INTR is a maskable
interrupt having lower priority. One more interrupt pin associated
is INTA called interrupt acknowledge.

 NMI
• It is a single non-maskable interrupt pin (NMI) having higher
priority than the maskable interrupt request pin (INTR)and it is
of type 2 interrupt.
• When this interrupt is activated, these actions take place −
 Completes the current instruction that is in progress.
 Pushes the Flag register values on to the stack.
 Pushes the CS (code segment) value and IP (instruction pointer)
value of the return address on to the stack.
 Interrupt flag and trap flag are reset to 0.
 INTR
• The INTR is a maskable interrupt because the microprocessor
will be interrupted only if interrupts are enabled using set
interrupt flag instruction. It should not be enabled using clear
interrupt Flag instruction.
• The INTR interrupt is activated by an I/O port. If the interrupt is
enabled and NMI is disabled, then the microprocessor first
completes the current execution and sends ‘0’ on INTA pin
twice. The first ‘0’ means INTA informs the external device to
get ready and during the second ‘0’ the microprocessor receives
the 8 bit, say X, from the programmable interrupt controller.

• These actions are taken by the microprocessor

 First completes the current instruction.
 Activates INTA output and receives the interrupt type, say X.
 Interrupt flag and trap flag is reset to 0
Software Interrupts:
• Some instructions are inserted at the desired position into the
program to create interrupts. These interrupt instructions can be
used to test the working of various interrupt handlers. It includes

 INT- Interrupt instruction with type number

• It is 2-byte instruction. First byte provides the op-code and the
second byte provides the interrupt type number. There are 256
interrupt types under this group.

• The starting address for type0 interrupt is 000000H, for type1

interrupt is 00004H similarly for type2 is 00008H and ……so
on.

• The first five pointers are dedicated interrupt pointers. The

interrupts from Type 5 to Type 31 are reserved for other
advanced microprocessors, and interrupts from 32 to Type 255
are available for hardware and software interrupts.
 The first five pointers are dedicated interrupt pointers.
i.e. −
TYPE 0 interrupt represents division by zero situation.
TYPE 1 interrupt represents single-step execution
during the debugging of a program.
TYPE 2 interrupt represents non-maskable NMI
interrupt.
TYPE 3 interrupt represents break-point interrupt.
TYPE 4 interrupt represents overflow interrupt.
 Interrupt Service Routine
• For every interrupt, there must be an interrupt service
routine (ISR), or interrupt handler. When an interrupt is
invoked, the microprocessor runs the interrupt service
routine.
• For every interrupt, there is a fixed location in memory that
holds the address of its ISR.
• The group of memory locations set aside to hold the
addresses of ISRs is called the interrupt vector table.
• When an interrupt is occurred, the microprocessor stops
execution of current instruction.
• It transfers the content of program counter into stack.
• It also stores the current status of the interrupts internally
but not on stack.
• After this, it jumps to the memory location specified by
Interrupt Vector Table (IVT). After that the code written on
that memory area will execute.
 Interrupt vector table
• The first 1Kbyte of memory of 8086 (00000 to 003FF) is set aside
as a table for storing the starting addresses of Interrupt Service
Procedures (ISP). Since 4-bytes are required for storing starting
addresses of ISPs, the table can hold 256 Interrupt procedures.

• The starting address of an ISP is often called the Interrupt Vector

or Interrupt Pointer. Therefore the table is referred as Interrupt
Vector Table. In this table, IP value is put in as low word of the
vector & CS is put in high vector.

• The total interrupt vector table is divided into three groups namely,
A. Dedicated interrupts (INT 0…..INT 4)
B. Reserved interrupts (INT 5…..INT 31)
C. Available interrupts (INT 32…..INT 225 )
 The interrupt vector (or interrupt pointer) table is the link between an
interrupt type code and the procedure that has been designated to
service interrupts associated with that code. 8086 supports total 256
types i.e. 00H to FFH.

 For each type it has to reserve four bytes i.e. double word. This double
word pointer contains the address of the procedure that is to service
interrupts of that type.
Instruction set 8086
 Instruction set 8086
• An instruction is a binary pattern designed inside a
microprocessor to perform a specific function.
• Instruction set defines the basic operation that a
programmer can specify to the device to perform.
• The entire group of instructions that a microprocessor
supports is called instruction set.
• The 8086 microprocessor supports 7 types of instructions −
1. Data copy/Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. Branch Instructions
5. Flag Manipulation Instructions
6. String Instructions
7. Machine control instructions
1.Data Transfer Instructions
• These instructions are used to transfer the data from
the source operand to the destination operand.
Following are the list of instructions under this group
 Instruction to transfer a word
 MOV − Used to copy the byte or word from the provided
source to the provided destination.
 PUSH − Used to put a word at the top of the stack.
 POP − Used to get a word from the top of the stack to the
provided location.
 LEA- Used to get effective address of register.
 XCHG − Used to exchange the data from two locations.
 XLAT − Used to translate a byte in AL using a table in the
memory.
 MOV Des, Src
 It is used to copy the content of Src (Source) to Des (Destination)
 Src operand can be register, memory location or immediate
operand.
 Des can be register or memory operand.
 Both Src and Des cannot be memory location at the same time.
 E.g.:
 MOV CX, 037A H
 MOV AL, BL
 MOV BX, [0301 H]

 PUSH Operand
 It pushes the operand into top of stack.
 E.g.: PUSH BX
 POP Des:
 It pops the operand from top of stack to Des.
 Des can be a general purpose register, segment register
(except CS) or memory location.
 E.g.: POP AX
 XCHG Des, Src:
 This instruction exchanges Src with Des.
 It cannot exchange two memory locations directly.
 E.g.: XCHG DX, AX
 IN Accumulator, Port Address:
 It transfers the operand from specified port to accumulator register.
 E.g.: IN AX, 0028 H
 OUT Port Address, Accumulator:
 It transfers the operand from accumulator to specified port.
 E.g.: OUT 0028 H, AX
 LEA Register, Src:
 It loads a 16-bit register with the offset address of the data
specified by the Src.
 E.g.: LEA BX, [DI]
 This instruction loads the contents of DI (offset) into the
BX register.
 LAHF: It copies the lower byte of flag register to AH.
 SAHF: It copies the contents of AH to lower byte of flag
register.
 PUSHF: Pushes flag register to top of stack.
 POPF: Pops the stack top to flag register.
2. Arithmetic Instructions
These instructions are used to perform arithmetic operations
like addition, subtraction, multiplication, division, etc
 Instructions to perform addition
 ADD − Used to add the provided byte to byte/word to word.
 ADC − Used to add with carry.
 INC − Used to increment the provided byte/word by 1.
 AAA − Used to adjust ASCII after addition.
 DAA − Used to adjust the decimal after the
addition/subtraction operation.
 Instructions to perform subtraction
 SUB − Used to subtract the byte from byte/word from word.
 SBB − Used to perform subtraction with borrow.
 DEC − Used to decrement the provided byte/word by 1.
 CMP − Used to compare 2 provided byte/word.
 AAS − Used to adjust ASCII codes after subtraction.
 DAS − Used to adjust decimal after subtraction.
 Instruction to perform multiplication
 MUL − Used to multiply unsigned byte by byte/word by
word.
 IMUL − Used to multiply signed byte by byte/word by
word.
 AAM − Used to adjust ASCII codes after multiplication.

 Instructions to perform division

 DIV − Used to divide the unsigned word by byte or
unsigned double word by word.
 IDIV − Used to divide the signed word by byte or signed
double word by word.
 AAD − Used to adjust ASCII codes after division
 ADD Des, Src
 It adds a byte to byte or a word to word.
 It effects AF, CF, OF, PF, SF, ZF flags.
 E.g.:
 ADD AL, 74H
 ADD DX, AX
 ADD AX, [BX]
 ADC Des, Src
 It adds the two operands with CF.
 It effects AF, CF, OF, PF, SF, ZF flags.
 E.g.:
 ADC AL, 74H
 ADC DX, AX
 ADC AX, [BX]
 SUB Des, Src
 It subtracts a byte from byte or a word from word.
 It effects AF, CF, OF, PF, SF, ZF flags.
 For subtraction, CF acts as borrow flag.
 E.g.:
 SUB AL, 74H
 SUB DX, AX
 SUB AX, [BX]

 SBB Des, Src

 It subtracts the two operands and also the borrow from the result.
 It effects AF, CF, OF, PF, SF, ZF flags.
 E.g.:
 SBB AL, 74H
 SBB DX, AX
 SBB AX, [BX]
 INC Src:
 It increments the byte or word by one.
 The operand can be a register or memory location.
 E.g.: INC AX
 INC [SI]
 DEC Src:
 It decrements the byte or word by one.
 The operand can be a register or memory location.
 E.g.: DEC AX
DEC [SI]
 NEG Src:
 It creates 2’s complement of a given number.
 That means, it changes the sign of a number.
 CMP Des, Src:
 It compares two specified bytes or words.
 The Src and Des can be a constant, register or memory
location.
 Both operands cannot be a memory location at the same time.
 The comparison is done simply by internally subtracting the
source from destination.
 The value of source and destination does not change, but the
flags CF, ZF, SF are modified to indicate the result.
 DAA (Decimal Adjust after Addition)

 It is used to make sure that the result of adding two BCD

numbers is adjusted to be a correct BCD number.
 It only works on AL register.
3. Logical Instructions
These instructions provide logical operations between operands.

 NOT Src:
 It complements each bit of Src to produce 1’s complement of the specified
operand.
 The operand can be a register or memory location.
 E.g NOT AX
 AND Des, Src:
 It performs AND operation of Des and Src.
 Src can be immediate number, register or memory location.
 Des can be register or memory location.
 OR Des, Src:
 It performs OR operation of Des and Src.
 Src can be immediate number, register or memory location.
 Des can be register or memory location.
 XOR Des, Src:
 It performs XOR operation of Des and Src.
 Src can be immediate number, register or memory location.
 Des can be register or memory location.
 SHL/SAL Des, Count:
 It shift bits of byte or word left, by count.
 It puts zero(s) in LSBs.
 MSB is shifted into carry flag.

 SHR/SAR Des, Count:

 It shift bits of byte or word right, by count.
 It puts zero(s)(for SHL) and Sign bit (for SAL) in MSBs.
 LSB is shifted into carry flag
 ROL Des, Count:
 It rotates bits of byte or word left, by count.
 LSB is transferred to MSB and also to CF.
 ROR Des, Count:
 It rotates bits of byte or word right, by count.
 MSB is transferred to LSB and also to CF.
 RCL Des, Count:
 It rotates bits of byte or word left, by count.
 LSB to MSB then MSB is transferred to CF and CF to LSB
 RCR Des, Count:
 It rotates bits of byte or word right, by count.
 MSB to LSB then LSB is transferred to CF and CF to MSB.
4. Branch Instructions
These instructions are used to transfer the control during
an execution. It includes the following instructions −
 Instructions to transfer the control during an execution
without any condition −
 CALL − Used to call a subroutine and save their return
address to the stack.

 RET − Used to return from the subroutine to the main

program. Every CALL instruction should have a RET.

 JMP − Used to jump to the provided address to proceed

to the next instruction.
 Instructions to transfer the control during an execution with
some conditions −
5. Flag Manipulation Instructions
The flag manipulation instructions directly modify some
of the flags of 8086.
 CLC− Clear carry flag. (It clears carry flag to 0)
 CMC- Complementary carry flag (It inverts the content of
Carry flag)
 STC- Set carry flag (It sets carry flag to 1)
 CLD- Clear direction flag (It clears direction flag to 0)
 STD- Set direction flag (It sets direction flag to 1)
 CLI- Clear interrupt flag (It clears interrupt flag to 0)
 STI- Set interrupt flag (It sets interrupt flag to 1)
6. String Instructions
String is a group of bytes/words and their memory is always allocated in a
sequential order.
 REP − Used to repeat the given instruction till CX ≠ 0.
 REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero
flag ZF = 1.
 REPNE/REPNZ − Used to repeat the given instruction until zero flag
ZF = 0.
 MOVS/MOVSB/MOVSW − Used to move the byte/word from one
string to another.
 COMS/COMPSB/COMPSW − Used to compare two string bytes/words.

 INS/INSB/INSW − Used as an input string/byte/word from the I/O port to

the provided memory location.
 OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the
provided memory location to the I/O port.
 SCAS/SCASB/SCASW − Used to scan a string and compare its byte with
a byte in AL or string word with a word in AX.
 LODS/LODSB/LODSW − Used to store the string byte into AL or string
word into AX.
7. Machine control Instructions
These type of instructions control machine functions
such as Halt, Interrupt, or do nothing. This type of
instructions alters the different type of operations
executed in the processor.
HLT (Halt) :- It causes the processor to enter in to the halt state.
It can be stop by INTR,NMI or RESET pin
NOP (No Operation) :- It causes the processor to enter in to the
wait state for 3 Clock cycles.
WAIT :- It causes the processor to enter in to the ideal state. Can
be stop by TEST, INTR or NMI pin.
LOCK :- This instruction prevents other processors to take
the control of shared resources. For e.g LOCK IN AL,80H
 DI- Disable Interrupt
Disable interrupt is used when the execution of a code
sequence cannot be interrupted. For example, in critical
time delays, this instruction is used at the beginning of the
code and the interrupts are enabled at the end of the code.
 EI- Enable Interrupt
After a system reset or the acknowledgement of an
interrupt, the Interrupt Enable the flip-flop is reset, thus
disabling the interrupts
 SIM- Set Interrupt Mask
This SIM instruction is used to implementation of different
interrupts of 8086 microprocessor.
 RIM- Reset Interrupt Mask
This is a multipurpose instruction used to read the status of
8086 interrupts.
 ASSEMBLER DIRECTIVES
• Assembly languages are low-level languages for programming
computers, microprocessors, microcontrollers, and other IC.

• An assembler directive is a statement to give direction to the

assembler to perform task of the assembly process.

• An assembler supports directives to define data, to organize

segments to control procedure, to define macros.

• It consists of two types of statements: instructions and

directives. The instructions are translated to the machine code
by the assembler whereas directives are not translated to the
machine codes.
DB – Defined Byte
• Used to declare a byte type variable or to set aside one or more
locations of type byte in memory.
• Example, PRICES DB 49H, 98H, 29H: Declare array of 3 bytes
named PRICES and initialize 3 bytes as shown.
DW – Define Word
• Used to tell the assembler to define a variable type as word or reserve
word in memory
DD – Define Double Word
• Used to declare a variable of type double word or to reserve a
memory location which can be accessed as double word.
DQ – Define Quad word
• Used to tell the assembler to declare the variable as 4 words of
storage in memory.
DT – Define Ten bytes
• Used to tell the assembler to declare the variable which is 10 bytes in
length or reserve 10 bytes of storage in memory.
.
END – End the program
• To tell the assembler to stop fetching the instruction and end the
program execution.
ENDP – it is used to end the procedure.
ENDS – it is used to end the segment.

EQU – Equate
• Used to give name to some value or symbol.
EVEN – Align on Even memory address
• Tells the assembler to increment the location counter to the next
even address if it is not already at an even address.
EXTRN
• Used to tell the assembler that the name or labels following the
directive are in some other assembly module.
GLOBAL – Declares symbols as PUBLIC or EXTRN
• Used to make the symbol available to other modules.
• It can be used in place of EXTRN or PUBLIC keyword.
GROUP – Group related segment
• Used to tell the assembler to group the logical segments
named after the directive into one logical segment.
• This allows the content of all the segments to be accessed
from the same group.
INCLUDE – include source code from file
• Used to tell the assembler to insert a block of source code
from the named file into the current source module. This
shortens the source code.
LABEL
• Used to give the name to the current value in the location
counter.
• The LABEL directive must be followed by a term which
specifies the type you want associated with that name.
PROC – Procedure
• Used to identify the start of the procedure.
PTR – Pointer
• Used to assign a specific type to a variable or a label.
• It is necessary to do this in any instruction where the type of the
operand is not clear.
PUBLIC
• It is used to tell the assembler that the specified label or variable
is accessible by other modules.
• This is useful in large programs which are generally written in
modules.
SEGMENT
• Used to indicate that the start of a logical segment.
• Preceding the segment directive is the name you want to give to
the segment.
Assume
• Used to tell the assembler the name of the logical segment it
should use for a specified segment.
• You must tell the assembler that what to assume for any
segment you use in the program.
• Example, ASSUME: CODE tells the assembler that the
instructions for the program are in segment named CODE.
 PROCEDURES
• In a program, very frequently face situations where there is
a need to perform the same set of task again and again.

• So, for that instead of writing the same sequence of

instructions, again and again, they are written separately in
a subprogram. This subprogram is called a procedure.

• With the help of procedures, we can very well implement

the concept of modular programming in our code.

• Also, whenever we need to execute the instructions

mentioned in the procedure, we can simply make a CALL
to it. Therefore, with the help of procedures, the duplicity
in the instructions can be avoided.
Syntax of Procedure:

Here, the PROC is a keyword to define that the set of instructions

enclosed by the given name is a procedure. It is used in the starting
instruction whenever we define a procedure. The ENDP keyword
defines that the body of the procedure has been ended.
• All the instructions lying between these two keywords are the
instructions that belong to the procedure and will be executed
whenever a CALL to the procedure is made.

• The keyword near or far defines the range of code within which
the procedure is defined. If it is defined in the same segment as
the rest code, then near is used. If it is defined in some other
segment, then the keyword far is used for it.

• The CALL to a procedure can be made in the following way,

CALL procedure_ name

• At the end of the procedure, the RET instruction is used. This

instruction will cause the execution to be transferred to the
program from which the call to the procedure was made.
 MACROS
• A Macro is a set of instructions grouped under a single
unit. It is another method for implementing modular
programming in the 8086 microprocessors
• The Macro is different from the Procedure in a way
that unlike calling and returning the control as in
procedures, the processor generates the code in the
program every time whenever and wherever a call to
the Macro is made.
• A Macro can be defined in a program using the
following assembler directives: MACRO (used after
the name of Macro before starting the body of the
Macro) and ENDM (at the end of the Macro).
• The following is the syntax for defining a Macro in the
8086 Microprocessor:

• The advantage of using Macro is that it avoids the

overhead time involved in calling and returning (as in
the procedures). Therefore, the execution of Macros is
faster as compared to procedures.
INTERFACE WITH I/O
AND
ADVANCED DEVICES
 Interfacing
• Any application of Microprocessor based system
requires transfer of data between external circuitry to
the microprocessor and Microprocessor to the external
circuitry.
• User can give information (input) to the microprocessor
using keyboard and user can see the result or output
from the display.
• Interfacing is used to exchange information between
two different applications or devices.
• Programmable peripheral interface (PPI-8255) is a
general purpose programmable I/O device designed to
interface the CPU with its outside world such as ADC,
DAC, keyboard, display etc.
• We can program it according to the given condition. It
can be used with almost any microprocessor.
8255 Working
 Program Peripheral Interface (PPI-8255)
• The Intel 8255 PPI is a 40 pin IC having total 24 I/o pins.

• The 24 I/O pins represented with 3 number of 8 bit I/O

ports. That are Port A, Port B and Port C.

• The ports can be programmed to function either input port

or output port.

• It main functions are to interface peripheral devices to

microprocessor.

• 8255 basically used for parallel data transfer from ports.

• It mainly operates in two modes

1. BSR Mode (Bit Set Reset mode)
2. I/O Mode
Block Diagram of 8255 PPI
Pin Diagram of 8255
 PPI-8255
• The Data Bus buffer is used to interface the internal data
bus of 8255 to the system data bus by reading and writing
operations.

• Read/Write control logic accepts the input from the

address bus and issues commands to the individual group
blocks. It also gives appropriate enabling signals to access
the required data/control words/status words.

• Port A can be programmed in three modes Mode0, Mode1

and Mode2.

• Port B can be programmed in two modes i.e Mode0 and

Mode1.

• Port C can be programmed for Bit set/ Reset operation.

 OPERATING MODES OF 8255

• There are mainly two operational modes of 8255

1. Input / output mode (I/O Mode)

2. Bit Set/Reset Mode (BSR Mode)

• Input / Output mode further classified into three modes

1. Mode 0
2. Mode 1
3. Mode 2
 Mode 0 (I/O Mode)
• In this mode, the ports can be used for simple input/output
operations.

• If both port A and port B are initialized in mode 0, the two

halves of port C can be either used together as an
additional 8-bit port, or it can be used as individual 4 bit
ports.

• Since the two halves of port C are independent, they may

be used such that one half is initialized as input port while
the other half is initialized as output port.

• In mode 0, the output are latched and input are buffered

not latched.
 Mode 1(I/O Mode)

• When we wish to use port A or port B for handshake

(strobed) input or output operation, we initialize that port
in mode 1.

• For port B in this mode (irrespective of weather is acting

as input port or output port) PC0, PC1 and PC2 pins
functions as handshake signals.

• In mode 1, two ports i.e port A and port B can be uses as 8

bit I/O port.

• In mode 1, Interrupt logic is supported.

• Input and output data are latched in mode 1.

 Mode 2 (I/O Mode)

• Only group A can be initialized in this mode.

• Port A can be used for bidirectional handshake data

transfer. This means that data can be input or output on the
same eight lines (PA0 to PA7).

• Pins PC3-PC7 are used as handshake lines for port A.

• The remaining pins of port C (PC0-PC2) can be used as

input/output lines if group B is initialized in mode 0.

• In this mode, the 8255 may be used to extend the system

bus to a slave microprocessor.
 BSR Mode
• BSR mode stands for “ Bit Set or Reset mode.

• The first bit of the Most Significant Bit (MSB) of the

control word decides the mode of operation of 8255 PPI.

• For BSR mode, the MSB must be Reset that is “0”.

• The BSR mode is works for only port C. In this mode, we

can select any bit of the port C and assign it any value
either 0 or 1.
 BSR Mode

• Here D7 bit is reset, which indicates BSR mode.

• The next three bits D6, D5 and D4 are don’t cares which
means there is no matter what value they contain, either 0
or 1, the processor does not consider them for any kind of
operations.

• The last bit of the control word D0 is responsible for the

selected bit to be set or reset.

• The processor sets the selected bit of the port C either 0 or

1 according to the value of D0.
 BSR Mode

• The bits D3, D2, and D1 decide which bit of the port C
must be selected. This is done in following way
Interfacing of ADC with 8086 through
8255
 Programmable Interrupt Controller (8259)

• The Programmable Interrupt Controller is a special

purpose integrated circuit that function as overall manager
in an interrupt driven system.

• It accepts interrupt request (IRQ) from the peripheral

equipment and determines priority, checks weather
incoming priority greater than current level being serviced

• Programmable Interrupt Controllers (PIC) are typically

have eight interrupt lines, and two PICs are often cascaded
to provide 15 available interrupt lines.

• Individually maskable interrupts and no clock is required

for operation.
Functional Block diagram of 8259
 PIC-8259
 Data Bus buffer
• It is a 3-state bidirectional 8-bit buffer is used to
interface the 8259 to the system data bus.

• Control words and status information are transferred

through the data bus buffer.

 Read/Write control logic

• The function of this block is to accept OUTPUT
commands from CPU.

• It contains the initialization command word (ICW)

register and operation command word (OCW) register
which store the various control formats for device
operation.
 PIC-8259
 Interrupt Request Register (IRR)
• IRR stores all the interrupt inputs that are requesting
service.
• Basically, it keeps track of which interrupt inputs are
asking for service.
• If an interrupt input is unmasked, and has an interrupt
signal on it, then the corresponding bit in the IRR will
be set.

 Interrupt Mask Register (IMR)

• The IMR is used to disable (mask) or enable (unmask)
individual interrupt inputs.
• Each bit in this register corresponds to the interrupt
input with the same number.
• Masking of the higher priority input will not affect the
interrupt request lines of lower priority. To unmask any
interrupt the corresponding bit is set ‘0’.
 PIC-8259
 In Service Register (ISR)
• The ISR keeps tracks of which interrupt inputs are
currently being serviced.

• For each input that is currently being serviced the

corresponding bit will be set in the in service register.

• Each of these 3- register can be read as status register.

 Priority Resolver
• This logic block determines the priorities of the set in
the IRR.

• The highest priority is selected and strobed into the

corresponding bit of the ISR during pulse.
 PIC-8259
 Cascade buffer/ Comparator
• This functional block stores and compare the IDs of all
8259’s in the registers. The associated 3-I/O pins
(CAS0, CAS1, CAS2) are outputs when 8259 is used a
master.

• Master and slave relation is performed by 8259 with

input devices. As a master, the 8259 sends the ID of the
interrupting slave device onto the CAS2-CAS0.

• The slave thus selected will send its pre-programmed

subroutine address on to the data bus during the next
one or two successive pulses.
Connection of 8259A with 8086
microprocessor
 USART(8251)

• The 8251 chip is Universal Synchronous Asynchronous

Receiver Transmitter (USART).
• It acts as a mediator between the microprocessor and
peripheral devices.
• USART is a 28 pin DIP and converts serial data to parallel
and parallel data to serial vice versa.
• Synchronous and Asynchronous communication shown below
 USART-8251
 Pin Diagram and Functional diagram of 8251
 USART-8251
• The USART takes data serially from peripheral (outside
devices) and converts into parallel data.

• After converting the data into parallel form, it transmits

it to the CPU.

• Similarly, it receives parallel data from microprocessor

and converts it into serial form.

• After converting data into serial form, it transmits it to

outside device (peripheral).
 Data Bus buffer
• This block helps in interfacing the internal data bus of
8251 to the system data bus. The data transmission is
possible between 8251 and CPU by the data bus buffer
block.
 USART-8251
 Read/Write Control logic
• It is a control block for overall device. It controls the
overall working by selecting the operation to be done.
The operation selection depends upon input signals as:

• In this way this unit selects one of the three registers-

data buffer register, status register and control register.
 USART-8251
 Modem control (modulator/ demodulator)
• A device converts analog signals to digital signals
and vice-versa and helps the computers to
communicate over telephone lines or cable wires.
The following are active-low pins of Modem.

• DSR: Data Set Ready signal is an input signal.

• DTR: Data Terminal Ready is an output signal.
• CTS: It is an input signal which controls the data
transmit circuit.
• RTS: It is an output signal which is used to set the
status RTS.
 USART-8251
 Transmit Buffer
• This block is used for parallel to serial converter that
receives a parallel byte for conversion into serial signal and
further transmission onto the common channel.
• TXD: It is an output signal, if its value is one, means
transmitter will transmit the data.
 Transmit Control
• This block is used to control the data transmission with the
help of following pins:
• TXRDY: It means transmitter is ready to transmit data
character.
• TXEMPTY: An output signal which indicates that
TXEMPTY pin has transmitted all the data characters and
transmitter is empty now.
• TXC: An active-low input pin which controls the data
transmission rate of transmitted data.
 USART-8251
 Receive Buffer
• This block acts as a buffer for the received data. It converts
serial data to parallel data.
• RXD: An input signal which receives the data.

 Receive Control
• This block controls the receiving data.
• RXRDY: An input signal indicates that it is ready to receive
the data.
• RXC: An active-low input signal which controls the data
rate of received data.
• SYNDET/BD: An input or output terminal. External
synchronous mode-input terminal and asynchronous mode-
output terminal.
8251A USART Interfacing with 8086
 Microprocessor - 8257 DMA
Controller
• DMA stands for Direct Memory Access. It is
designed by Intel to transfer data at the fastest
rate. It allows the device to transfer the data
directly to/from memory without any
interference of the CPU.
• Using a DMA controller, the device requests the
CPU to hold its data, address and control bus, so
the device is free to transfer data directly to/from
the memory. The DMA data transfer is initiated
only after receiving HLDA signal from the CPU.
How DMA Operations are Performed?
• Following is the sequence of operations performed by
a DMA −
• Initially, when any device has to send data between the
device and the memory, the device has to send DMA
request (DRQ) to DMA controller.
• The DMA controller sends Hold request (HRQ) to the
CPU and waits for the CPU to assert the HLDA.
• Then the microprocessor tri-states all the data bus,
address bus, and control bus. The CPU leaves the
control over bus and acknowledges the HOLD request
through HLDA signal.
• Now the CPU is in HOLD state and the DMA controller
has to manage the operations over buses between the
CPU, memory, and I/O devices.
 Features of 8257
• Here is a list of some of the prominent features of 8257
• It has four channels which can be used over four I/O
devices.
• Each channel has 16-bit address and 14-bit counter.
• Each channel can transfer data up to 64kb.
• Each channel can be programmed independently.
• Each channel can perform read transfer, write transfer
and verify transfer operations.
• It generates MARK signal to the peripheral device that
128 bytes have been transferred.
• It requires a single phase clock.
• Its frequency ranges from 250Hz to 3MHz.
• It operates in 2 modes, i.e., Master mode and Slave
mode.
8257 Architecture
8257 Pin Description
DRQ0−DRQ3
• These are the four individual channel DMA request inputs, which are
used by the peripheral devices for using DMA services. When the
fixed priority mode is selected, then DRQ0 has the highest priority and
DRQ3 has the lowest priority among them.
DACKo − DACK3
• These are the active-low DMA acknowledge lines, which updates the
requesting peripheral about the status of their request by the CPU.
These lines can also act as strobe lines for the requesting devices.
Do − D7
• These are bidirectional, data lines which are used to interface the
system bus with the internal data bus of DMA controller. In the Slave
mode, it carries command words to 8257 and status word from 8257.
In the master mode, these lines are used to send higher byte of the
generated address to the latch. This address is further latched using
ADSTB signal.
IOR
• It is an active-low bidirectional tri-state input line, which is used by
the CPU to read internal registers of 8257 in the Slave mode. In the
master mode, it is used to read data from the peripheral devices
during a memory write cycle.
IOW
• It is an active low bi-direction tri-state line, which is used to
load the contents of the data bus to the 8-bit mode register
or upper/lower byte of a 16-bit DMA address register or
terminal count register. In the master mode, it is used to load
the data to the peripheral devices during DMA memory read
cycle.
CLK
• It is a clock frequency signal which is required for the internal
operation of 8257.
RESET
• This signal is used to RESET the DMA controller by disabling
all the DMA channels.
Ao - A3
• These are the four least significant address lines. In the slave
mode, they act as an input, which selects one of the registers
to be read or written. In the master mode, they are the four
least significant memory address output lines generated by
8257.
CS
• It is an active-low chip select line. In the Slave mode, it
enables the read/write operations to/from 8257. In the
master mode, it disables the read/write operations
to/from 8257.
A4 - A7
• These are the higher nibble of the lower byte address
generated by DMA in the master mode.
READY
• It is an active-high asynchronous input signal, which
makes DMA ready by inserting wait states.
HRQ
• This signal is used to receive the hold request signal
from the output device. In the slave mode, it is
connected with a DRQ input line 8257. In Master mode,
it is connected with HOLD input of the CPU.
HLDA
• It is the hold acknowledgement signal which indicates
the DMA controller that the bus has been granted to the
requesting peripheral by the CPU when it is set to 1.
MEMR
• It is the low memory read signal, which is used to read
the data from the addressed memory locations during
DMA read cycles.
MEMW
• It is the active-low three state signal which is used to
write the data to the addressed memory location during
DMA write operation.
ADST
• This signal is used to convert the higher byte of the
memory address generated by the DMA controller into
the latches.
AEN
• This signal is used to disable the address bus/data bus.
TC
• It stands for ‘Terminal Count’, which indicates the
present DMA cycle to the present peripheral devices.
MARK
• The mark will be activated after each 128 cycles or
integral multiples of it from the beginning. It indicates
the current DMA cycle is the 128th cycle since the
previous MARK output to the selected peripheral
device.
Vcc
• It is the power signal which is required for the
operation of the circuit.