Digital Design Introduction

Digital Design:
Verilog and FPGA Course
 Yousef Sherif
FPGA Design and Verification Engineer @ PyramidTech LLC

TA @ the AUC

Digital design graduation project supervisor.

VLSI Community Founder

Field of interest:
• Digital Design
• Digital Verification
• FPGA Flow
• ASIC Flow

Digital Design:
Verilog and FPGA Course
© Eng | Yousef Sherif 2024
Tell me about yourself

Digital
Digital Design:
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 Agenda
• Electronics History

• Moore’s Law

• Analog vs Digital Signals

• Implementation Approaches

• ASIC Design Flow

• FPGA Design Flow

• Companies Classifications

• Course content overview

Digital
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Electronics are everywhere

Digital
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 Discrete vs. Integrated Electronics
Discrete Electronics
Discrete electronics are constructed of components which are manufactured separately such as resistors, capacitors, transistors, and diodes.
Later, these components are connected together by using conducted wires on a circuit board or a printed circuit board.

Integrated Electronics
Integrated electronics involves the use of integrated circuits (ICs) where multiple electronic components, such as transistors, resistors, and
capacitors, are fabricated onto a single semiconductor chip. This integration allows for compact designs, reduced power consumption, and
improved efficiency in electronic systems.

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 Electronics History
ENIAC (Electronic Numerical Integrator And Computer) was the world's first general-purpose electronic computer. ENIAC is
also considered the world's first programmable computer (1946), although programming the computer was a complex,
manual process that could take days.

Costing nearly $500,000, ENIAC weighed 30 tons and covered an area of about 1,800 square feet.

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ICs Evolution
Modern IC
First IC

Digital
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Abstraction Levels

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 Transistor Evolution

First Transistor Modern Transistors

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 Moore’s Law
Moore's law is the observation that the number of transistors in an integrated circuit (IC) doubles about every two years.
Moore's law is an observation and projection of a historical trend. Rather than a law of physics, it is an empirical relationship
linked to gains from experience in production.

• Transistor area and cost are reduced by a factor of 2

• Feature size shrinks by 30% every 2-3 years
• Transistors become cheaper
• Transistors become faster

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Moore’s Law

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 39.54 billion

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Moore’s Law
Transistor Scaling

Investment Better Performance/Cost

Market Growth

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 Moore’s Law
Will Moore’s Law run out of steam?
– Can’t build transistors smaller than an atom…
– Wires gets smaller, which increases the wires resistance…

Transistors are made of silicon. The atomic radius of silicon is 0.132 nm. Today's transistors are close to the silicon atoms
wide, so it is harder to make transistors smaller. We're getting very close to the limit of how small we can make a transistor.

The industry is now faced with the increasing importance of a new trend, “More than Moore”.

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Moore’s Law
Technology, Device, and
Transistor
Circuit Scaling
Innovations,
System Integration

Investment Increase
Better Functionality,
Performance/Cost
and / or Lower Cost

Market Growth

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Beyond Moore’s Law
More than Moore: Diversification

HV Sensors
Analog/RF Passives Actuators Biochips
Power

Baseline CMOS: CPU, Memory, Logic

io 130nm Interacting with people and environment

More Moore: Miniaturization

n
t
90nm Non-digital content
System-in-package
at
ur (SiP)
iz 65nm
a Information
ni
i Processing
M 45nm

Digital content
oo 32nm
System-on-chip
re
: (SoC)
M 22nm
re .
o .
M .
V

Beyond CMOS

Digital
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Beyond Moore’s Law

Digital
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 Analog vs Digital Signals
Analog: continuous in time and amplitude. Ex: Human Voice

Digital: discrete in time and amplitude. Ex: Binary Code

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 Why Digital?
Digital circuits are:
• Less sensitive to noise (robust)
• Easier to store (digital memories)
• Easier to process (digital signal processing: DSP)
• Amenable to automated design
• Amenable to automated testing
• Direct beneficiary of Moore’s law (down-scaling)

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 Why Analog?
• All the physical signals in the world around us are analog.
Ex: Voice, light, temperature, pressure, etc.

• We (will) always need an “analog” interface circuit to

connect between our physical world and our digital
electronics

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 Electronic System Example:
Wireless Transceiver
• The analog part interfaces with the real world.
• The digital part processes and stores the signal.

Analog Digital

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Implementation Approaches

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 Custom Approach
Full custom IC design involves creating integrated circuits from the ground up, specifying the characteristics of
individual transistors and customizing the layout for optimal performance in a specific application. It is a highly
detailed and specialized process, allowing for precise control over the design but often requiring significant time,
expertise, and resources.

AND Gate
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 Custom Approach
Advantages:
• High optimization potential for speed, power, and area.

Disadvantages:
• Challenging implementation due to limited design automation.
• Time-consuming with high design costs, leading to a lengthy time-to-market.

Usage:
Infrequently used, with typical scenarios including:
o Block reused many times (e.g., library cells).
o Cost spread across a large volume (e.g., critical blocks in a processor).
o Cost is not the prime criterion (e.g., space applications).

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 Semi-Custom
Approach
Semi-custom IC design involves two primary methods: cell-based design for ASICs (Application-Specific Integrated
Circuits), utilizing predefined cells and functional blocks for designing and fabricating the IC. The second method is
array-based design, where fabricated boards serve as a platform for implementing various designs. This can be a
one-time connection (pre-diffused array) or offer flexibility for multiple configurations, as seen in Field-Programmable
Gate Arrays (FPGAs). This approach strikes a balance between customization and efficiency, allowing designers to
optimize performance while benefiting from the reusability and time-saving advantages of pre-designed
components.

Full Adder (Implemented using pre-designed cells)

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 Semi-Custom
Approach
Advantages:
• Efficient Development: Integrates pre-designed components for faster and more efficient development.
• Cost-effectiveness: Reduces costs through the reuse of standardized components.
• Automation: Utilizing automated tools simplifies the design process.
• Enhanced Reusability: Promotes higher design reusability using standard cells and functional blocks.
• Simplified Verification: Easer to verify using simulation tools (ModelSim, VCS, etc.).

Disadvantages:
• Limited Customization: Constraints on customization may limit optimization for specific applications.
• Moderate Performance: Lower performance compared to full custom approach.
• Dependency on Standard Cells: Quality and characteristics of standard cells impact the overall design.
• Large Area: Depending on design constraints, may not achieve the same level of area optimization as full custom
designs.

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 Cell-Based Approach
Cell-Based Approach involves designing integrated circuits (ICs) by combining pre-designed and pre-verified
standard cells from a standard cell library provided by the foundry.

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 Standard Cells
• The library includes all logic gates of different fan-in and fan-out, flip-flops and latches, and more complex functions:
decoders, encoders, comparators...
• The library is available from fabs and library vendors
• Standard cells are redesigned for every technology generation
• Each cell must have:
o Circuit schematic, symbol, and physical layout
o Models: behavioral, Verilog/VHDL, detailed timing, power, routing

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Standard Cells

Standard Cell Library

Logic Gates Sequential Cells Complex Cells

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 Standard Cell Example

NAND Layout NAND Schematic NAND Symbol

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 Macro Cells
• Cells of more complex circuits such as multiplier, memories, embedded processor.
• Macro reuse should low initial design cost
• There are three types of macros:
1. Soft Macro
2. Hard Macro
3. IP

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 Soft Macro Cells
Soft macros are typically described in a hardware description language (HDL), such as Verilog or VHDL. Designers can
parameterize and customize these macros by adjusting certain parameters or settings during instantiation, allowing for
greater versatility in integrating them into different parts of the overall IC design.

• As it is an HDL without specific layout, it needs synthesis, placement, and routing. Final layout can differ each time it
is instantiated.
• Timing, power, and area are only determined after generation
• Easily exported to other technologies
• More popular than hard macros

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 Hard Macro Cells
Hard macros are fixed and pre-designed functional blocks or modules with a specific layout and functionality. Unlike
soft macros, which offer flexibility and customization during instantiation, hard macros come with a predetermined
layout that cannot be modified.

• Since their layout and functionality are fixed, they can be highly optimized for the target technology, resulting in
better performance and reduced power consumption.
• However, the trade-off is a lack of flexibility compared to soft macros, making them more suitable for well-defined
and stable functions within an integrated circuit.
• Used for processor core, memory block, or analog circuit.
• Cannot export to other technologies.

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 IPs
IPs, or Intellectual Properties, are macros supplied by third-party vendors. Functioning as black boxes, IPs cannot be
directly viewed or modified; they are utilized as integrated components in a design. IPs can exist in either soft or hard
forms.

ARM bus protocols like AHB, APB, the designs like Ethernet, SPI, USB , UART core etc. All of these can be designed stand
alone as IP cores/blocks and can be licensed to multiple design houses and for different designs.

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 Pre-Diffused Array
Pre-Diffused Arrays, also known as "mask-programmable" gate arrays, are wafers contain arrays of primitive cells with
all fabrication steps done except metal/via layers to achieve programmability through metal/via masks. The
fabrication turnaround time is fast, as it involves only the metal/via layers, resulting in cost-effectiveness due to shared
high-cost fabrication steps. Pre-Diffused Arrays offer one-time programmability, once you fabricated wires/vias, you
can’t edit them.

Properties:
• Less design time, less cost, and shorter time-to-market.
• Very limited speed / power / area optimization

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Pre-Diffused Array

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 Pre-Wired Arrays
Pre-Wired Arrays are pre-fabricated with programmable logic and programmable interconnects and achieve full
programmability in the field (location). Early versions: PROM, PAL, and PLA. Modern version: FPGA “field-programmable
gate arrays”

Configuration (program) can be stored using different techniques:

• Fuse (one-time programmability only)
• Non-volatile EPROM (can be reprogrammed, keeps program indefinitely)
• Volatile RAM (can be reprogrammed, only keeps program while powered)

Properties:
• Moderate fabrication cost since all fabrication steps are shared
Spartan 6 FPGA
• Much less design time & cost, and much shorter time-to-market
• Very limited speed / power / area optimization

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Implementation Approaches
Comparison
Pre-wired
Full-custom Cell-based
array-based
Design Cost High Lower Lowest

Design Time Long Shorter Shortest

Fabrication Cost High High Moderate

No fabrication steps
Fabrication Time Longer Longer
after design at all.
Performance
Highly Optimized Limited Very Limited
Optimization
Time
Long Shorter Shortest
To Market

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ASIC Design Flow

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FPGA Design Flow

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 ASIC Design Flow

A S I C
Application Specific Integrated Circuit

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ASIC Design Flow
Specifications
System
Architecture

Design
Flow

Fabrication
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ASIC Design Flow
Behavioral View
(RTL)
Design
Flow Structural View
(Gate-Level Netlist)

Physical View
(Layout)

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 ASIC Design Flow

Behavioral View
(RTL)

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 ASIC Design Flow

Structural View
(Gate-Level Netlist)

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 ASIC Design Flow

Physical View
(Layout)

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 ASIC Design Flow
RTL Design
• RTL stands for Register-Transfer Level, and RTL design refers to the process of designing digital circuits at the level of registers and the data
transfers between them.
• In RTL design, the behavior of the digital circuit is described in terms of registers and the operations that transfer data between these registers.
The design is typically expressed using a hardware description language (HDL) such as Verilog, SystemVerilog or VHDL.

out = A & B ;

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 ASIC Design Flow
Functional Verification
• Functional verification is the process of demonstrating the functional correctness of an RTL design with respect to the design specifications.
• Functional verification attempts to check whether the proposed design is doing what it is intended to do. This is a complex task and takes the
majority of time and effort in most large electronic system design projects. It is imperative that the design is functionally verified and any
potential bug is eliminated at an early stage. It is very common that more engineers’ time and expense is spent to verify a design than the rest
of the steps in the ASIC design cycle.
• design is essential to ensure that the fabricated chips are free from any kind of manufacturing defects.

1 2 3

A=1 A=0
Wait some time
B=1 B=1
10 ns for ex
out == 1 ??? out == 0 ???

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 ASIC Design Flow
Logic Synthesis
• Logic synthesis takes as an input a description of a circuit expressed in a high-level language such as Verilog , SystemVerilog or VHDL. Other
inputs include timing constraints for the design as well as the specific target implementation technology.
• Logic synthesis software then analyzes these inputs and maps them to a particular set of interconnected logic elements taken from standard
cell libraries that are also provided as inputs to the process. The output interconnected logic elements are called gate level netlist, which is an
HDL file, written in Verilog, SystemVerilog or VHDL, that describes the design in terms of logic gates.

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 ASIC Design Flow
Gate-Level Simulation (GLS)
• Gate level Simulation(GLS) is done at the late level of Design cycle.
• This is run after the RTL code is synthesized into Netlist.
• Backend Layout tools usually provides the delay model information in a format called SDF(Standard Delay Format) file. Simulators uses these
SDF files along with Netlist to generate simulation with timing delays . This process is called SDF back annotation.

Functional Verification Gate-Level Simulation

Glitch

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 ASIC Design Flow
Static Timing Analysis (STA)
• Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations.
• STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing
constraints inside the design and at the input/output interface.

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 ASIC Design Flow
Design For Testability (DFT)
• Design for Testability (DFT) is an approach that aims to make digital circuits easier to test during the manufacturing and debugging process.
• DFT involves incorporating additional circuitry and design features such as scan chains, built-in self-test (BIST) circuits, and boundary scan cells
into the chip design to facilitate testing.
• Design for testability in VLSI design is essential to ensure that the fabricated chips are free from any kind of manufacturing defects.
• It also reduces the overall test time and thereby the cost of testing, and debugging.
• By incorporating DFT techniques into the chip design, it becomes easier to test the structural correctness of the chip, leading to higher-quality
products and faster time-to-market.

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 ASIC Design Flow
Formal Verification
• Formal verification, is a method to find the functional equivalence of one design by comparing with the golden design.
• Another point to note here is, formal verification is always carried out using two inputs and result comes out by comparing the functionality of
these two input designs.

out = a & b ; and(out, a, b) ;

Formal
Verification

Pass/Fail

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 ASIC Design Flow
Floorplanning
• Floorplanning is the first step in the PnR flow.
• Floorplanning is the process of identifying structures that should be placed close together and allocating space for them in such a manner as to
meet the sometimes-conflicting goals of available space (cost of the chip), required performance, and the desire to have everything close to
everything else.

Floorplanning steps:
• Decide core width and height for die size estimation.
• IO pad sites are created for placement of IO pad placement.
• Placement of macros.
• The standard cell rows created for standard cell placement.
• Adding physical only cells
• apart from this aspect ratio of the core, utilization of core area, cell orientation, and core to IO clearance are also taken care of during the
floorplan stages.

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 Companies Classifications
Power Planning
• Power planning is stage typically part of the floorplanning stage, in which power grid network is created to distribute the power uniformly to
each part of the chip.
• Power planning means to provide power to every macros and standard cells and all other cells are present in the design.
• Power planning is also called Pre-routing as the Power Network Synthesis (PNS) is done before actual signal routing and clock routing.
• Power ring is designed around the core. Power rings contains both VDD and VSS rings.
• After the ring is placed a power is designed such that power reaches all the cells easily, power mesh is nothing but horizontal and vertical lines
on the chip.
• During power planning, the VDD and VSS rails also have to be defined.
• Objective of power planning is to meet IR drop budget.
• Power planning involves- calculating number of power pins required, number of rings and straps, width of rings and straps and IR drop.

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 Digital
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 Digital
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 ASIC Design Flow
Placement
• Placement is the process of placing the standard cells inside the core boundary in an optimal location. The tool tries to place the standard cell
in such a way that the design should have minimal congestions and the best timing.

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 ASIC Design Flow
Clock Tree Synthesis (CTS)
• CTS is the process of connecting the clocks to all clock pin of sequential circuits by using inverters/buffers in order to balance the skew and to
minimize the insertion delay.
• All the clock pins are driven by a single clock source. Clock balancing is important for meeting all the design constraints.

Before CTS After CTS

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 ASIC Design Flow
Routing
• Routing refers to the process of connecting various components, such as logic gates, flip-flops, and other functional blocks, using metal
interconnects.

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 ASIC Design Flow
Signoff
Signoff is used to represent the completion of the design process. It is the final stage of the design cycle, in which all aspects of the chip are
verified to make sure it meets the desired specifications.
Sign off includes:
• The physical verification of the design (LVS, and DRC).
• The timing verification of the design (STA).
• The power verification of the design (EMIR).
• The electrical verification of the design (ERC).
Once all these verifications are completed and the chip is deemed to be functioning as expected, the design can be signed off.

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 ASIC Design Flow
Design Rule Check (DRC)
Design Rule Check (DRC) is the process of checking physical layout data against fabrication-specific rules specified by the foundry to ensure
successful fabrication.
Process specific design rules must be followed when drawing layouts to avoid any manufacturing defects during the fabrication of an IC.
Process design rules are the minimum allowable drawing dimensions which affects the X and Y dimensions of layout and not the depth/vertical
dimensions.

Design Rule examples

Minimum Width: The min width rule specifies the minimum width of individual shapes on a single layer
Minimum Spacing: The minimum spacing between objects on a single layer

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 Digital
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 ASIC Design Flow
Layout Versus Schematic (LVS)
• DRC only verifies that the given layout satisfies the design rules provided by the fabrication unit. It does not ensure the functionality of layout.
Because of this, idea of LVS is originated.
• Layout Versus Schematic (LVS) verifies the connectivity of a Verilog Netlist and Layout Netlist (Extracted Netlist from GDS)
• Tool extracts circuit devices and interconnects from the layout and saved as Layout Netlist (SPICE format)
• As LVS performs comparison between 2 Netlist, it does not compare the functionalities of both the Netlist.
• LVS checks examples
• Short Net Error, Open Net Error, Extract errors, Compare errors

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Layout Extracted Netlist

Extract

Netlist

Compare

Pass/Fail

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 Digital
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 ASIC Design Flow
Electrical Rule Check (ERC)
ERC involves checking a design for all electrical connection.
Checks such as:
• Unconnected input or shorted output.
• Gates should not connect directly to supply (Must be connect through TIE high/low cells only).
• Floating gate error:
o If any gate is unconnected, this could lead to leakage issues.

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 ASIC Design Flow
Electromigration & IR drop (EMIR)
• Electromigration is the gradual displacement of metal atoms in a semiconductor. It occurs when the current density is high enough to cause the
drift of metal ions in the direction of the electron flow.
• The Power supply in the chip is distributed uniformly through metal layers (Vdd & Vss) across the design. These metal layers have finite amount
of resistance. When voltage is applied to this metal wires current starts flowing through the metal layers and some voltage is dropped due to
that resistance of metal wires and current. this drop is called as IR drop.

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 ASIC Design Flow
Tapeout
Tapeout is the final result of the design process for integrated circuits or printed circuit boards before they are sent for manufacturing. The
Tapeout is specifically the point at which the graphic for the photomask of the circuit is sent to the fabrication facility.

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 RTL Design RTL Functional Verification

Synthesis
Logical Synthesis Gate-Level Simulation

DFT Insertion
STA

Synthesis
Physical
Verification
Floorplanning
Physical Checks:
Formal ERC & DRC & LVS
Power Planning

Placement
STA

CTS

EMIR
Routing

Tapeout
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Fab

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 RTL Design

Front End
Logical Synthesis

DFT Insertion

Floorplanning

Backend
Power Planning

Placement

CTS

Routing

Tapeout
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Fab

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 FPGA Design Flow

F P G A
Field Programmable Gate Array

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FPGA Design Flow

IO IO IO

Logic Logic Logic

IO

IO
Block Block Block

Switch block

6−LUT
FF Logic Logic Logic

IO

IO
Block Block Block
…

Logic block

Logic Logic Logic

IO

IO
Block Block Block

IO IO IO
Connection block

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FPGA Design Flow
Specifications
System
Architecture

Design
Flow

Programming
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FPGA Design Flow Behavioral View
(RTL)

Design
Structural View
Flow (Gate-Level Netlist)

Physical View
(FPGA Fabric)

Configuration View
(Bitstream)

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 FPGA Design Flow

Behavioral View
(RTL)

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 FPGA Design Flow

Structural View
(Gate-Level Netlist)

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 FPGA Design Flow

Physical View
(FPGA Fabric)

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 FPGA Design Flow

Configuration View
(Bitstream)

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FPGA Design Flow
Design Entry

Functional Simulation
Schematic Capture HDL

Logical Synthesis

Implementation STA

Generating Bitstream

Programming the FPGA

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FPGA Design Flow
Feature FPGA ASIC
Fixed design (Changes are not possible
Design Flexibility Highly flexible and reprogrammable
after fabrication)

Time to Market Quick development Longer development

Performance lower Higher and optimized

Area Larger Smaller

Power
higher Lower
Consumption
Cost Lower Higher

Ideal for prototyping and testing

Prototyping and Testing is limited to simulation until the
designs before committing to ASIC
Testing development
ASIC is fabricated.

Volume
Suitable for low to medium volumes Economical for high volumes
Production

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 Companies Classifications
1) IDM (Integrated Device Manufacturer)
An integrated device manufacturer (IDM) is a semiconductor company which designs, manufactures, and sells integrated circuit (IC) products.
Examples of IDMs are Intel, Samsung.

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 Companies Classifications
2) Fabless Design House
They are companies that design and sell the hardware and semiconductor chips but don’t manufacture the silicon wafers, or chips, used in its
products; instead, they outsource the fabrication to a manufacturing plant or foundry.
Examples Nvidia, Qualcomm, Apple, and MediaTek.

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 Companies Classifications
3) IP Vendors
Semiconductor IP (Intellectual Property) vendors are companies that specialize in developing, selling, and licensing proprietary technology
components that are integrated into semiconductor chips during the design and manufacturing process.
Examples Arm, Freescale, IBM.

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 Companies Classifications
4) Design Services
These companies specialize in designing specific blocks or parts of a larger system for other companies. For example, an IP vendor may design
most blocks for an IP and ask another design services company to design some blocks of the IP.
Examples Si-Vision, PyramidTech, SCENARIO.

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 Companies Classifications
5) EDA (Electronic Design Automation)
Electronic design automation (EDA) companies, are companies that develop software tools for designing electronic systems such as integrated
circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor
chips. Examples: Cadence, Siemens (Mentor), Synopsys.

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 Companies Classifications
6) Foundry (Fabs)
It is a semiconductor manufacturer that makes chips for other companies. Semiconductor foundries make most of the chips in the world for
hundreds of "fabless" companies that design but do not manufacture, including some of the largest and well-known tech leaders such as
Qualcomm, NVIDIA and Apple.
Examples: TSMC, GlobalFoundries, UMC, SMIC.

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 Companies Classifications
7) Fab Equipment
They are companies that specialize in manufacturing and providing machinery and equipment used in foundries.
Examples ASML.

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 Companies Classifications
8) Wafer
Wafer companies manufacture semiconductor wafers. Semiconductor wafers are thin slices of semiconductor material, usually made of silicon,
on which integrated circuits (ICs) or microchips are fabricated.

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 Companies Classifications
9) Assembly
They are companies that make ICs packages. IC package is a case component attached to semiconductor chips. It serves multiple functions,
including supplying power, protecting the chip from external environmental factors, transmitting signals to and from the chip, and enhancing chip
performance. Example Mercury, ISI - Interconnect Systems, Amkor Technology.

Is This
Food?

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 Companies Classifications
10) MPC (Multi-Project Chip)
Multi-project chip (MPC), and multi-project wafer (MPW) semiconductor manufacturing arrangements allow customers to share tooling (like
mask) and microelectronics wafer fabrication cost between several designs or projects. Examples Efabless, MOSIS, CMC Microsystems.

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 Digital
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Thank You

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