CSC 425

ADVANCED COMPUTER ARCHITECTURE

SYNCHRONOUS AND ASYNCHRONOUS CONTROL

 SYNCHRONOUS AND ASYNCHRONOUS CONTROL

• The term synchronous is used to describe a continuous and consistent timed

transfer of data blocks.
• These types of connections are used when large amounts of data must be
transferred from one location to the other
• In Synchronous transmission data is sent in frames or blocks.
• In Asynchronous transmission data is sent in the form of bytes or characters.
• Synchronous transmission is faster, as a common clock is shared by the sender and
receiver.

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 Introduction
• Computer’s CPU can be divided into two parts.

• Datapath: it is a network of storage units (registers) and arithmetic and logic units (for performing
various operations on data) connected by buses (capable of moving data from place to place) where the
timing is controlled by clocks.

• Control unit: it is a module responsible for sequencing operations and making sure the correct data
are where they need to be at the correct time. These components perform the tasks of the CPU, such
as fetching instructions, decoding them, and executing the indicated sequence of operations.

• The performance of a machine is directly affected by the design of the datapath and the control unit.

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 The Control Unit

• The control unit is the traffic manager of the CPU. It monitors the execution of all instructions
and the transfer of all information.
• The control unit extracts instructions from memory, decodes these instructions, making sure
data are in the right place at the right time, tells the ALU which registers to use, services
interrupts, and turns on the correct circuitry in the ALU for the execution of the desired
operation.
• The control unit uses a program counter register to find the next instruction for execution
and a status register to keep track of overflows, carries, etc.

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 The Computer Bus

• A bus is a set of wires that acts as a shared but common datapath to connect multiple
subsystems within the system.
• The CPU communicates with the other components of the computer through a bus.
• It consists of multiple lines allowing the parallel movement of bits.
• Buses are low cost but very versatile, and they make it easy to connect new devices to
each other and to the system. At any one time, only one device (be it a register, the
ALU, memory or some other component) may use the bus.

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 The Computer Bus (Cont.)

• However, this sharing often results in a communications bottleneck.

• The speed of the bus is affected by its length as well as by the number of
devices sharing it.
• Devices are divided into master and slave categories.
• A master device is one that initiates actions and a slave is one that responds
to requests by a master

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 The Computer Bus (Cont.)
• The power lines provide the electrical power necessary.

• Typical bus transactions include

• Sending an address (for a read or write),

• Transferring data from memory to a register (a memory read) and

• Transferring data to the memory from a register (a memory write).

• In addition, buses are used for I/O reads and writes from peripheral devices. Each type of transfer occurs within
a bus cycle, the time between two ticks of the bus clock.

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 Computer Bus (Cont.)
• Using a protocol instead of the clock to coordinate transactions means that asynchronous
buses scale better with technology and can support a wider variety of devices.
• To use a bus, a device must reserve it, because only one device can use the bus at a time.
Bus masters are devices that are allowed to initiate transfer of information (control bus),
and bus slaves are modules that are activated by a master and respond to requests to read
and write data (so only masters can reserve the bus).
• Both follow a communications protocol to use the bus, working within very specific
timing requirements.

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 Types of Bus

• A bus can be point-to-point, connecting two specific components

• A multipoint bus: a common pathway that connects a number of devices
requiring these devices to share the bus

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 Types of Bus (Cont.)

Point-to-Point bus Multipoint bus

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 Computer Bus (Cont.)

• In a very simple system, the processor is the only device allowed to become a
bus master. This is good in terms of avoiding chaos, but bad because the
processor now is involved in every transaction that uses the bus.

▪ In systems with more than one master device, bus arbitration is required.
Bus arbitration schemes must provide priority to certain master devices and,
at the same time, make sure lower priority devices are not starved out.

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 Computer Bus (Cont.)

Bus arbitration schemes fall into four categories:

1. Daisy chain arbitration: This scheme uses a “grant bus” control line that is passed down the bus

from the highest priority device to the lowest priority device. (Fairness is not ensured, and it is

possible that low-priority devices are “starved out” and never allowed to use the bus.) This scheme is
simple but not fair.

2. Centralized parallel arbitration: Each device has a request control line to the bus and a centralized
arbiter selects who gets the bus. Bottlenecks can result using this type of arbitration.

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 Computer Bus (Cont.)
3. Distributed arbitration using self-selection: This scheme is similar to centralized
arbitration but

instead of a central authority selecting who gets the bus, the devices themselves determine
who has highest priority and who should get the bus.

4. Distributed arbitration using collision detection: Each device is allowed to make a request
for the bus. If the bus detects any collisions (multiple simultaneous requests), the device
must make another request. (Ethernet uses this type of arbitration).

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 Components of a Bus
• Devices share the bus hence protocol (set of usage rules) is very important

• Often the lines of a bus dedicated to moving data are called the data bus. These data lines contain the
actual information that must be moved from one location to another.
• Control lines indicate which device has permission to use the bus and for what purpose (reading or
writing from memory or from an input/output [I/O] device, for example).
• Control lines also transfer acknowledgments for bus requests, interrupts, and clock synchronization
signals.
• Address lines indicate the location (e.g., in memory) that the data should be either read from or
written to.

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 Component of a Bus

Component of a Typical Bus

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 Categories of Bus
• Because of the different types of information buses transport and the various devices that use the buses,
buses themselves have been divided into different types.

• Processor-memory buses are short, high-speed buses that are closely matched to the memory
system on the machine to maximize the bandwidth (transfer of data) and are usually design specific.

• I/O buses are typically longer than processor-memory buses and allow for many types of devices
with varying bandwidths. These buses are compatible with many different architectures.

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 Categories of Bus (Cont.)

• A backplane bus is actually built into the chassis of the machine and connects the processor,
the I/O devices, and the memory (so all devices share one bus).

• Many computers have a hierarchy of buses, so it is not uncommon to have two buses (e.g., a
processor-memory bus and an I/O bus) or more in the same system.

• High-performance systems often use all three types of buses.

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 Categories of Bus (Cont.)

Backplane Bus System

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 Clock

• A clock is a circuit that emits series of pulses with a precise pulse width and a precise interval between
consecutive pulses. This interval is called the clock cycle time.
• Clock speed is generally measured in megahertz or gigahertz.
• A clock is used by a sequential circuit to decide when to update the state of the circuit (i.e., when do
“present” inputs become “past” inputs?). This means that inputs to the circuit can only affect the storage
element at given discrete instances of time.
• Every computer contains an internal clock that regulates how quickly instructions can be executed.
• The clock also synchronizes all of the components in the system. As the clock ticks, it sets the pace for
everything that happens in the system.

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 Clock (Cont.)
• The CPU uses this clock to regulate its progress, checking the otherwise unpredictable speed of the
digital logic gates. The CPU requires a fixed number of clock ticks to execute each instruction.
• Therefore, instruction performance is often measured in clock cycles—the time between clock ticks—
instead of seconds.
• The clock frequency (sometimes called the clock rate or clock speed) is measured in megahertz (MHz)
or gigahertz (GHz).
• Most machines are synchronous: there is a master clock signal, which ticks (changing from 0 to 1 to 0
and so on) at regular intervals.
• Registers must wait for the clock to tick before new data can be loaded. It seems reasonable to assume
that if we speed up the clock, the machine will run faster.

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 Clock (Cont.)
• However, there are limits on how short we can make the clock cycles. When the clock ticks and new
data are loaded into the registers, the register outputs are likely to change.
• These changed output values must propagate through all the circuits in the machine until they reach the
input of the next set of registers, where they are stored.
• The clock cycle must be long enough to allow these changes to reach the next set of registers. If the
clock cycle is too short, we could end up with some values not reaching the registers.
• This would result in an inconsistent state in our machine, which is definitely something we must
avoid.
• Therefore, the minimum clock cycle time must be at least as great as the maximum propagation delay
of the circuit, from each set of register outputs to register inputs

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 Clock (Cont.)

Clock signal indicating discrete instances of time

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 Bus and Data Transfer
• Buses are physically little more than bunches of wires, but they have specific
standards for connectors, timing, and signaling specifications and exact
protocols for use.
• Synchronous buses are clocked, and things happen only as the clock ticks (a
sequence of events is controlled by the clock).
• Every device is synchronized by the rate at which the clock ticks, or the
clock rate. The bus cycle time mentioned is the reciprocal of the bus clock
rate.

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 Example
What will be the length of the bus cycle if the bus clock rate is 133MHz?
Solution

• 𝐿𝑒𝑛𝑔𝑡ℎ 𝑜𝑓 𝐵𝑢𝑠 𝐶𝑦𝑐𝑙𝑒 = 𝐵𝑢𝑠 𝐶𝑙𝑜𝑐𝑘 𝑅𝑎𝑡𝑒 −1

Bus clock rate = 133MHZ

Therefore, 𝐿𝑒𝑛𝑔𝑡ℎ 𝑜𝑓 𝐵𝑢𝑠 𝐶𝑦𝑐𝑙𝑒 = 133000000−1

1
=133000000

=7.5188 𝑋 10−9 𝑆𝑒𝑐𝑠

= 7.5188 𝑁𝑎𝑛𝑜𝑆𝑒𝑐𝑜𝑛𝑑𝑠
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 Types of Data Transfer
• Synchronous Data Transfer

• In a digital system, the internal operations are synchronized by means of clock pulses
supplied by a common pulse generator. In a computer, CPU and an I/O interface are
designed independently of each other.

• If the registers in the interface share a common clock with the CPU registers, the data
transfer between two units are said to be synchronous.

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 Types of Data Transfer (Cont.)

• Asynchronous Data Transfer

• In a computer, CPU and the I/O interface are designed independently of each other.
• Also, the internal timing in each unit is independent from each other.
• when the registers of the I/O interface and registers of CPU uses a separate private
clock, hence the two units are said to be asynchronous to each other. CPU and I/O
device coordinate data transfers.
• Asynchronous bus control lines coordinate the operations and a complex handshaking
protocol must be used to enforce the timing.
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 Types of Data Transfer (Cont.)
To read a word of data from memory, for example, the protocol would require steps similar to the
following:

1. ReqREAD: This bus control line is activated and the data memory address is put on the appropriate bus
lines at the same time.

2. ReadyDATA: This control line is asserted when the memory system has put the required data on the
data lines for the bus.

3.ACK: This control line is used to indicate that the ReqREAD or the ReadyDATA has been
acknowledged.

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 Methods Used in Asynchronous Data Transfer
• Strobe Control: This is one way of data transfer i.e. by means of strobe pulse supplied
by one of the units to indicate to the other unit when the transfer has to occur.

• Handshaking: This method is used to accompany each data item being transferred
with a control signal that indicates the presence of data in the bus.

• The unit receiving the data item responds with another control signal to acknowledge
receipt of the data.

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 Strobe Control
• Strobe control method of data transfer uses a single control signal for each transfer.

• The strobe may be activated by either the source unit or the destination unit.

• a. Source Initiated Strobe

• b. Destination Initiated Strobe

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 Source Initiated Strobe

Source Initiated Strobe Block Diagram

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 Source Initiated Strobe
a. The data bus carries the binary information from source unit to the destination unit as shown.

b. The strobe is a single line that informs the destination unit when a valid data word is available in the bus.

c. The source unit first places the data on the bus.

d. After a brief delay to ensure that the data settle to a steady value, the source activate the strobe pulse.

e. The information on the data bus and the strobe signal remain in the active state for a sufficient time to
allow the destination unit to receive the data.

f. The source removes the data from the bus for a brief period of time after it disables the strobe pulse.

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 Source Initiated Strobe

Timing Diagram
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 Destination Initiated Strobe
a. First, the destination unit activate the strobe pulse, informing the source to provide the data.

b. The source unit responds by placing the requested binary information on the unit to accept it.

c. The data must be valid and remain in the bus long enough for the destination unit to accept it.

d. The falling edge of the strobe pulse can be used again to trigger a destination register.

e. The destination unit then disables the strobe. The source removes the data from the bus after a
predetermined time interval.

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 Destination Initiated Strobe

Block Diagram for Destination Initiated Strobe

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 Timing Diagram

Timing Diagram

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 Handshaking

• For the source-initiated data transfer under strobe control method, the source unit has
no way of knowing whether destination unit has received the data or not.

• Similarly, the destination-initiated transfer has no method of knowing whether the

source unit has placed the data on the data bus.

• Handshaking mechanism solves this problem by introducing a second control signal that
provides a reply to the unit that initiate the transfer.

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 Handshaking (Cont.)

• There are two control lines in handshaking technique:

• a. Source to destination unit

• b. Destination to source unit

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 Source Initiated Transfer

• Handshaking signals are used to synchronize bus activities.

• The two handshaking lines are:

• Data valid: This is generated by the source unit

• Data accepted: This is generated by the destination unit.

• The timing diagram shows exchange of signals between two units.

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 Handshaking Source Initiated

Hand Shaking Source Initiated Transfer Block Diagram

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 The sequence of events for Handshaking Source-
Initiated Transfer

1. The source unit initiates the transfer by placing the data on the bus and enabling its data valid signal.

2. The data accepted signals is activated by the destination unit after it accepts the data from the bus.

3. The source unit then disables its data valid signal, which validates the data on the bus.

4. The destination unit the enables its data accepted signal and the system goes into its initial state.

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 Handshaking Source Initiated Timing Diagram

Hand Shaking Source Initiated Transfer Timing Diagram

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 Destination Initiated Transfer Using Handshaking

• In this case the signal generated by the destination unit is ready for data.

• The source unit does not place the data on the bus until it receives the ready for data signal
from the destination unit.

• The handshaking procedure follows the same pattern as in source-initiated case. The sequence
of events in both cases is almost the same except that the ready for signal has to be converted
from data accepted in case of source initiated.

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 Block Diagram for Destination

Block Diagram for Destination Initiated Using Handshaking

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 Timing Diagram for Destination Initiated Transfer
Using Handshaking

Timing Diagram for Destination Initiated Transfer Using Handshaking

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