Chapter 9

Asynchronous Sequential Logic

9.1 INTRODUCTION
A sequential circuit is specified by a time sequence of inputs, outputs, and internal states, In
synchronous sequential circuits, the change of internal state occurs in response to the syn-
chronized clock puIses, Asynchronous sequential circuits do not use clock pulses. The change
of internal state occurs when them is a change in the input variables. The memory elements in
synchronous sequential circuits are clocked flip-flops, The memory elements in asynchronous
sequential circuits are either unclocked flip-flops or time-delay elements. The memory capa-
bility of a time-delay device hpends on the finite amount of time it takes for the signal to
propagate through digital gates. An asynchronous sequential circuit quite often resembles a
combinational circuit with feedback.
The design of asynchronous sequential circuits is more difficult than that of synchronous cir-
cuits because of the timing problems involved in the feedback path. In a properly designed
synchronous system,timing problems are eliminated by triggering all flip-flops with the pulse
edge. The change from one state to the next occurs during the short lime of the pulse transi-
tion. Since the asynchronous circuit does not use a clock, the state of the system is allowed to
change immediately after the input changes. Care must be taken to ensure that each new state
keeps the circuit in a stable condition even though a feedback palh exists.
Asynchronous sequentid circuits are useful in a variety of applications. They are used when
speed of operation is important, especially in those cases where h e digital system must re-
spond quickly without having to wait for a clock pulse. They are more economical to use in
small independent systems that require only a few components, as it may not be practical to
go to the expense of providing a circuit for generating clock pulses. Asynchronous circuits are
useful in applications where the input signals to the system may change at any time, inde-
pendently of an internal dock.The communication between two units, each having its own
 Chapter 9 Asynchronous SquentIal Loglc

independent clock, must be done with asyncbrown*rc h i t s , Digital designers produce

a mixed system in whicb some part of the syPchrowus system has the chmtahtics of an a s p
chnous circuit. Icnowledge of a s ~ o u sequential
s logic behavior is heIpful in verifying
tbat the total digital system i in th p p r maaner.
Figure 9.1 shows the black diagram of an asymhron~ seqwda! circuit that consists of
a combinational circuit and delay elemen&connected to form feedback Imps. There are n
input variables, m output variables, d k in- states.The delay elementscap be v i s d k d
as providing short-term memory for the m p n W cimrit. In a g-type circuit, the pmpga-
tion delay that exists in the combhtimal circuitpath hinput to wtput provides sufIIcitnt
delay along the feedback -1 so that no w c delay eleme~ts are rtctually hscned iPto the
feedback path. The prcsent4te ltrtd next- variables in asydmmus sequential Wts
are cummarily called seem variabks md m'mion whzbles, m d y . The excita-
tion variables should not be confusedwith the excitable table used in the of clocked se-
quential circuits.

Steady-State Condition
y=Y
 Sectton 9.2 Analysis Procedure 41 7

When an input variable changes in value, the y secondary variables do not change instan-
taneously. It takes a certain amount of time for the signal to propagate from the input termi-
nals, thruugh the combinationalcircuit, to the Y excitation variables, which generate new values
for the next state. These values propagate through the delay elements md become the new
present state for the secondary variables. Note the distinction between the y's and the Ys.In
the steady-state condition, they are the same, but during transition they are not. For a given value
of input variables, the system is stable if the circuit reaches a steady-statecondition with yi =
for i = 1,2, . . . , k. Otherwise, the circuit is in a continuous transition and is said to be unsta-
ble. It is important to realize that a transition from one stable state to another occurs only in re-
sponse to a change in an input'variable. This is in contrast to synchronous systems,in which
state transitions occur in response to the application of a clock pulse.
To ensure proper operation, asynchronous sequential circuits must be allowed to attain a sta-
ble state before the input is changed to a new value. Because of &lays in the wires and the gate
circuits, it is impossible to have two or more input variables change at exactly the same instant
of time without anuncertainty as to which one changes first. Therefore, simultaneous changes of
two or more variables are usually prohibited, This restriction means that only one input variable
can change at any one time and the time between two input changes must be longex than the time
it takes the circuit to reach a stable state. Such operation, defined asfidndmntak mode, assumes
that the input signals change one at a time and only when the circuit is in a stable condition.

9.2 A N A L Y S I S PROCEDURE
The analysis of asynchronous sequential circuits consists of obtaining a table or a diagram that
describes the sequence of internal states and outputs as a function of changes in the input vari-
ables. Alogic diagram manifests the behavior of an asynchronous sequential circuit if it has one
or more feedback loops or if it includes unclocked flip-flops. In this section,we will investi-
gate the behavior of asynchronous sequential circuits that have feedback paths without em-
ploying flip-flops, Unclocked flip-flops are called latches, and their use in asynchronous
sequential circuits will be explained in the next section.
The analysis procedure will be presented by means of three specific examples.The f i s t ex-
ample introduces the transition tabIe, the second defines the flow table, and the third investi-
gates the stability of asynchronous sequential circuits.

TramMon Tabla
An example of an asynchronous sequential circuit with only gates is shown inFig. 9.2. The di-
agram clearly shows two feedback loops from the OR gate outputs back to the AND gate in-
puts. The circuit consists of one input variable x and two intend states. The intend states
have two excitation variables, 5 and Yz,and two secondary variables, yl and n.The delay as-
sociated with each feedback loop is obtained from the propagationdelay h e e n eachy input
and its corresponding Y output. Each logic gate in the path introduces a propagation delay of
about 2 to 10 ns. The wires that conduct electrical signals intrduce approximately a 1-ns delay
for each foot of wire. Thus, w additional external delay elements are necessary when the com-
binati~nalcircuit and the wires in the feedback path provide sficient delay.