Memory Test System Training Course

Elementary
Course
ASC-SE
2004.4.28.
 Dynamic Functional Test

DC Parametric Test

Overview
Overview
1. Overview
LIST OF PROGRAM REFERENCE MANUALS
Manual No. Manual Name
ATL-51 Test Plan Program Reference Manual:
8256281 VOL1 ATL-51 Pin Specifications
8256282 VOL2 ATL-51 Measurement Results Processing
8256283 VOL3 ATL-51 Power Supplies, Input/output levels, and
terminator levels
8256284 VOL4 ATL-51 Clock pulse generation
8256285 VOL5 ATL-51 DC Parametric Tests
8256286 VOL6 ATL-51 Reference ON/OFF, Timing Control
8256287 VOL7 ATL-51 System Interface Control
8256288 VOL8 ATL-51 Setting for ALPG Operations, Functional Test
8256289 VOL9 ATL-51 Nontester Statements
8256290 VOL10 ATL-51 Failure Analysis Memory
8262613 VOL11 ATL-51 DBM/CBM
8256291 ATL-51 Overall Index, Overall Table of Contents
8256292 ATL-51 Pattern Program Reference Manual
8256293 ATL-51 SOCKET Program Reference Manual
8256294 ATL-51 SCRAMBLE Program Reference Manual
8269038 T5500 Series Programming Reference Manual
8256295 ATL-51 Tester Utility Program Reference Manual
8141091 Error Code Table Reference Manual
8179111 T5363 Performance Board Assembly Procedure Reference
Manual
82xxxxx T55xx Product Description Manual
1. Overview

1.1 Hardware Overview

1.1.1 Kind of LSI Test
① DC Parametric
② Dynamic Function Test
③ AC Parametric Test
1. Overview

① DC Parametric
ADVANTEST
d evice ISVM
VSIM
DC test unit ICC1, ICC2, IIH/L,
IOH/L, VOH/VOL,
MUT VIH/VIL and so on.

PPS
Programmable
Power Supply
MUT: Memory Under Test
1. Overview

① DC Parametric Source current

measure voltage
ADVANTEST
d evice ISVM
VSIM
DC test unit
Source voltage
MUT measure current

PPS
Programmable
Power Supply
MUT: Memory Under Test
1. Overview

① DC Parametric
ADVANTEST
d evice ISVM
VSIM 1. Power supply
DC test unit 2. Source voltage
MUT measure current

PPS
Programmable
Power Supply
MUT: Memory Under Test
1. Overview

② Dynamic Functional Test

0/1 write read test

Read/modify/write test
Page mode function test
Refresh function test
Bump test
Pause time function test
1. Overview

② Dynamic Functional Test

ADVANTEST

d evice
Pulse Generator Pulse Checker

Load Circuit
TG, ALPG,
TG, ALPG, PDS, PDS, SC, VO,
PPS
FC, VI comparator

Load
current,
voltage
1. Overview

③ AC Parametric Test

AC parametric test performs the functional

test based on the time element conditions,
Including access time, hold time, setup
time and input pulse duration according to
the timing conditions specified to MUTs.
1. Overview

③ AC Parametric Test
For example!

Din tDH

/WE
1. Overview

1.1.2 Type of wave-form mode

What is 3 elements of pulse?

1. Overview

1.1.2 Type of wave-form mode

Three elements of pulse:
1. Logic data 1, 0
2. Voltage information Vh: High voltage Vl: Low voltage
3. Time information t1: Logic data changes from 0 to 1.
t2: Logic data changes from 1 to 0.
1. Overview

1.1.2 Type of wave-form mode

For example
Logic data .............1, 0, 0, 1, 1
Voltage .................Vh=2V, VL=0.5V
Time .....................10ns, 20ns, 30ns, 40ns, 50ns, 60ns
1. Overview

1.1.2 Type of wave-form mode

NRZ waveform 1 0
(Non Return to
Zero)
When pulse is NRZ
set to 1 in a
cycle, this
waveform is
never reset to 0
within the same
cycle. (ACLKn)

ACLKn
BCLKn
CCLKn
1. Overview

1.1.2 Type of wave-form mode

1 0
NZ waveform
(Return to Zero)
When pulse is
set to 1 in a NRZ
cycle, this
waveform is
reset to 0 within RZ
the same cycle.
(BCLKn, CCLKn)
Types:
RZO, RZZ, RZX
ACLKn
BCLKn
CCLKn
1. Overview

1.1.2 Type of wave-form mode

1 0
NZ waveform
(Return to Zero)
When pulse is
set to 1 in a NRZ
cycle, this
waveform is
reset to 0 within RZO
the same cycle.
(BCLKn, CCLKn)
Types:
RZO, RZZ, RZX
ACLKn
BCLKn
CCLKn
1. Overview

1.1.2 Type of wave-form mode

1 0
NZ waveform
(Return to Zero)
When pulse is
set to 1 in a NRZ
cycle, this
waveform is
reset to 0 within RZZ
the same cycle.
(BCLKn, CCLKn)
Types:
RZO, RZZ, RZX
ACLKn
BCLKn
CCLKn
1. Overview

1.1.2 Type of wave-form mode

1 0
NZ waveform
(Return to Zero)
When pulse is
set to 1 in a NRZ
cycle, this
waveform is
reset to 0 within RZX
the same cycle.
(BCLKn, CCLKn)
Types:
RZO, RZZ, RZX
ACLKn
BCLKn
CCLKn
1. Overview

1.1.2 Type of wave-form mode

1 0

NRZ
XOR waveform
(Exclusive OR)
A waveform in
RZX
which each 1 is
always surrounded
by 0s or each 0 is XOR
always surrounded
by 1s.
(ACLKn, BCLKn, ACLKn
CCLKn)
BCLKn
CCLKn
1. Overview

1.1.2 Type of wave-form mode

1 0

/NRZ

RZX
Reverse the whole
wave-form.
XOR

ACLKn
BCLKn
CCLKn
1. Overview

1.1.2 Type of wave-form mode

Please try it!

(1) /RZZ (1, 0, 0, 1)

(2) /XOR (1, 1, 0, 0)

1. Overview

1.1.3 Hardware configuration

How to generate wave-form

by our test system?

RATE = 100NS
/WE 2.4V

30NS

0.5V
70NS
1. Overview

1.1.3 Hardware configuration

(1) Driver channel RATE = 100NS
/WE 2.4V

Timing generator 30NS

0.5V
70NS
BCLKn, CCLKn
TG

TSn RATE

ＡＤＶＡＮＴＥＳＴ
device
A
1. Overview

1.1.3 Hardware configuration

(1) Driver channel
100NS 100NS
RATE = 100NS RATE
/WE 2.4V

30NS
1 0
0.5V
30NS
70NS
70NS
BCLKn
CCLKn

Now we have the timing information!

1. Overview

1.1.3 Hardware configuration

(1) Driver channel RATE = 100NS
/WE 2.4V

Timing generator 30NS

0.5V
70NS
BCLKn, CCLKn
TG

TSn RATE

ＡＤＶＡＮＴＥＳＴ
MPAT

device
…W
…
ALPG A

Algorithmic
pattern generator
1. Overview

1.1.3 Hardware configuration

(1) Driver channel
100NS 100NS
RATE = 100NS RATE
/WE 2.4V

30NS
1 (W) 0 (no W)
0.5V
30NS
70NS
70NS
BCLKn
CCLKn

Now we have the timing information!

Now we have the Logic data !
1. Overview

1.1.3 Hardware configuration

(1) Driver channel RATE = 100NS
/WE 2.4V

Timing generator 30NS

0.5V
70NS
BCLKn, CCLKn
TG

TSn RATE

/RZO

ＡＤＶＡＮＴＥＳＴ
MPAT

device
PD1 XOR PD1
…W
NRZ
…
ALPG PDS TGFC A

Algorithmic Programmable Timing generator

pattern generator data selector format control
1. Overview

1.1.3 Hardware configuration

(1) Driver channel
100NS 100NS
RATE = 100NS RATE
/WE 2.4V

30NS
1 (W) 0 (no W)
0.5V
30NS
70NS
70NS
BCLKn
CCLKn

Now we have the timing information! /RZO

Now we have the Logic data !

Now we have the wave-form mode !
1. Overview

1.1.3 Hardware configuration

(1) Driver channel RATE = 100NS
/WE 2.4V

Timing generator 30NS

0.5V
70NS
BCLKn, CCLKn
TG

TSn RATE

/RZO

ＡＤＶＡＮＴＥＳＴ
MPAT

device
PD1 XOR PD1
…W
NRZ VIH VIL
…
ALPG PDS TGFC A
VI

Algorithmic Programmable Timing generator

pattern generator data selector format control Voltage Input
1. Overview

1.1.3 Hardware configuration

(1) Driver channel
100NS 100NS
RATE = 100NS RATE
/WE 2.4V

30NS
1 (W) 0 (no W)
0.5V
30NS
70NS
70NS
BCLKn
CCLKn

Now we have the timing information! /RZO

Now we have the Logic data ! VIH=2.4V

Now we have the wave-form mode ! VIH=0.5V

Now we have the Voltage information !

We get the /WE pulse.

1. Overview

1.1.3 Hardware configuration

(1) Driver channel
100NS 100NS
RATE = 100NS RATE
/WE 2.4V

30NS
1 (W) 0 (no W)
0.5V
30NS
70NS
70NS
BCLKn
CCLKn

Statements:
/RZO

RATE = 100NS
VIH=2.4V
BCLKn = 30NS
VIH=0.5V
CCLKn = 70NS
INn = 2.4V, 0.5V
PD1 = INn, /RZO, BCLKn, CCLKn, <WT>
1. Overview

1.1.3 Hardware configuration

(1) Driver channel RATE = 100NS
/WE 2.4V

Timing generator 30NS

0.5V
70NS
BCLKn, CCLKn
TG

TSn RATE

Performance
/RZO board

ＡＤＶＡＮＴＥＳＴ
MPAT

device
PD1 XOR PD1
…W
NRZ VIH VIL P.B
…
ALPG PDS TGFC A
VI
Programmable
PPS power supply

Algorithmic Programmable Timing generator

pattern generator data selector format control Voltage Input
1. Overview

1.1.3 Hardware configuration

(2) Comparator channel

TG

Comparator

ALPG PDS
P.B

ＡＤＶＡＮＴＥＳＴ
device
VOH VOL

AFM
VO

Voltage output
1. Overview

1.1.3 Hardware configuration

(2) Comparator channel

“1”
VOH=2.0V
DOUT “HZ”
VOL=0.8V
“0”
STRBn
1. Overview

1.1.3 Hardware configuration

(2) Comparator channel
STRBn=80NS
TG
CPEn

Comparator

ALPG PDS
P.B
MPAT

ＡＤＶＡＮＴＥＳＴ
device
…
…R P33
VOH VOL

AFM VO

Voltage output
1. Overview

1.1.3 Hardware configuration

(2) Comparator channel

“1”
VOH=2.0V
DOUT “HZ”
VOL=0.8V
“0”
80NS 80NS
STRBn

R (CPEn) “0” “1”

1. Overview

1.1.3 Hardware configuration

(2) Comparator channel
STRBn=80NS
TG
CPEn

Comparator

ALPG PDS
P.B
MPAT Expected

ＡＤＶＡＮＴＥＳＴ
device
…R value

… P33

SC VOH VOL

AFM VO

Sense Control Voltage output

1. Overview

1.1.3 Hardware configuration

(2) Comparator channel

“1”
VOH=2.0V
DOUT “HZ”
VOL=0.8V
“0”
STRBn
80NS 80NS Statements:

R (CPEn) “0” “1” STRBn = 80NS

OUTn = 2.0V, 0.8V
PC33 = OUTn, STRBn, <D0>
Expected “1” “0”
value

SC PASS
1. Overview

1.1.4 DC parametric test

OPEN PD1
①

ＡＤＶＡＮＴＥＳＴ
device
FIXH
② FIXL DC Test
V
Pulse
③
Generator
P.B PS1 ISVM
Condition of pins except the measurement pin A A

① Connect DCTU with target pin.

VSIM
PPS
② Select ISVM or VSIM. DCTU

③ Other pins: - OPEN

- FIXH/FIXL (ex: IN1=3V,0V & PD3=IN1,FIXL)
- Pulse generator
1. Overview

1.1.5 Configuration of entire test system

Main functions
- User I/O
Network (standard)
- File management
Monito Screen Floppy disket Hard disk
- Edition & compilation
of programs Environment processor

- Peripheral resource Sun

management
- Networking
disk CDROM CMT Printer
-Tester processor
（Option）
control
Tester processor
Mainframe Test unit

Main functions
- Interfaces between the environment processor
and tester hardware.
- Compiles and executes the test program.
- Controlling the external devices through
standard bus
1. Overview

1.2 Software Overview

1.2.1 Operating system (ASX/U)

File Monitor
textedit filename TEST
C shell
Vi filename test

ESC
CTRL/Z
*EXIT TRANS filename
:wq trans filename

Editor Compiler Controller

filename

Utilities
1. Overview

1.2 Software Overview

COMMAND LANGUAGE INTERPRETER

See file content  %more <filename>

See file listing  %ls
See directory  %pwd
Change directory  %cd <path>
Rename a file  %mv <old filename> <new filename>
Delete a file  %cp <source file> <dest file>
Append a file  %cat <new file> >> <old file>
Copy a file  %cp <source file> <dest file>
Create directory  %mkdir <foldername>
Process status  % ps -ef│grep test
1. Overview

1.2 Software Overview

1.2.2 Test program types

Sub program
1. Overview

1.2 Software Overview

1.2.2 Test program types
Main program
Main program describes voltage conditions, timing conditions, pin conditions, and
a measurement start instruction, and also controls the entire test sequence.
1. Overview

1.2 Software Overview

1.2.2 Test program types
Memory pattern program
Memory pattern (MPAT) program is used to describe ALPG (algorithmic pattern
generator) operation control instruction and test pattern generation instruction and
is executed in main program.
1. Overview

1.2 Software Overview

1.2.2 Test program types
Socket program
Socket program is essential to execute parallel test with multiple DUTs, and also
used to assign the pin number and pin name, or to create a conversion table that
can describe reserved character string.
1. Overview

1.2 Software Overview

1.2.2 Test program types
Scramble program
In many IC memories, the actual address in a chip is different from the external
address, because they are designed to achieve compatibility with similar product
of other companies or to reduce the chip size. In this case, even if the program is
executed using the assumed addresses, precise testing cannot be performed.
1. Overview

1.2 Software Overview

1.2.2 Test program types
Scramble program
The Scramble program translates logical addresses generated by the ALPG on the
basis of the MPAT program into physical addresses.
wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww
wwwwwww
1. Overview

1.2 Software Overview

1.2.2 Test program types

Sub program
Subroutine program of the test plan programs. This program is called form the
main program or another subroutine program. When the same processing must be
executed many times, the processing can be written in this subroutine to simplify
the test plan programs.
1. Overview

1.2 Software Overview

1.2.3 Memory test system operation
☆ How to Compile a Test Program (trans Command)
☆ How to Execute a Test Program (test, O command)
☆ Runtime Error (/ERR error code)
☆ How to Initialize the User Area (U Command)
☆ How to Verify the Test Condition Using the Pin Monitor (/PM)
☆ How to Obtain a Shmoo Plot (/SHM2)
☆ How to Verify the Pattern Program Operation (/MTRACE)
☆ How to Save Screen Data to a Text File (/LOG ON, /LOG OFF)
☆ How to Initialize the Memory Test System (/INIT)
☆ How to Execute the Tester Diagnostic Program (/PRO model_name)
DC Parametric Test
2. DC Parametric Test

In this part describes programming

for executing the DC test.

Let’s study basic programming for input current

measurement of 1Mx4-bit DRAM as an example!

☆ Input Current Measurement

☆ Power Current Measurement in Non-operating Mode
☆ Power Current Measurement in Operating Mode
2. DC Parametric Test

2.1 Input Current Measurement

2.1.1 Pin assignment & test condition
A measurement conditions shown in Table 2-1 and 2-2 are extracted
from a device data sheet.
2. DC Parametric Test

2.1.1 Pin assignment & test condition

According to the above data sheets, measurement conditions are

arranged as follow.

- Applied voltage : 5.5 V

- Power supply voltage: 5.5 V
- Measured pin : all the input pins
- Pins except measured pin: 0 V
- Pass/fail criteria : ±10µA
2. DC Parametric Test

2.1.1 Pin assignment & test condition

- Applied voltage : 5.5 V
- Power supply voltage: 5.5 V VSIM = 5.5V, R8V, M80UA

- Measured pin : all the input pins

DQ1 1 26 Vss
P33 GND
DQ2 2 25 DQ4
- Pins except measured pin: 0 V P34
WE 3 24 DQ3
P36
PD13 P35
IN1 = 2V, 0V

1M×4Bit DRAM
RAS 4 23 CAS
- Pass/fail criteria : ±10µA PD11
A9 5 22 OE
PD12

ADVANTEST
PD10 PD14
VIH
A0 9 18 A8
PD1 PD9
A1 10 17 A7 FIXL
PD2 PD8
A2 11 16 A6
V PD3 PD7 VIL
A3 12 15 A5
PD4 PD6
Vcc 13 14 A4
PPS1 PD5
ISVM
PDn = IN1, FIXL
A

A PD1 = DC
VSIM
DCTU VS1 = 5.5V
PPS
LIMIT DC = 10UA, -10UA
2. DC Parametric Test

2.1.2 Program example

1. PRO IIH
2. VS1=5.5V
3. IN1=2.5V,0V PRO IIH
4. VSIM=5.5V,R8V,M80UA
⑴ ⑵
5. LIMIT DC=10UA,-10UA ⑴ Program title
6. PD1-14=IN1,FIXL ⑵ The program name is
7. P33-36=IN1,FIXL a character string up
8. TIME1=2MS:VS1 to eight Alphanumeric
9. TIME2=3MS:IN1,DC characters
10. PD1=DC
11. TEST 100
12. MEAS DC
13. END
2. DC Parametric Test

2.1.2 Program example

1. PRO IIH
2. VS1=5.5V
3. IN1=2.5V,0V VS1 = 5.5v
4. VSIM=5.5V,R8V,M80UA
⑶ ⑷
5. LIMIT DC=10UA,-10UA ⑶ Set the power supply
6. PD1-14=IN1,FIXL voltage
7. P33-36=IN1,FIXL ⑷ Applied voltage
8. TIME1=2MS:VS1
9. TIME2=3MS:IN1,DC
10. PD1=DC
11. TEST 100
12. MEAS DC
13. END
2. DC Parametric Test

2.1.2 Program example

1. PRO IIH
2. VS1=5.5V
3. IN1=2.5V,0V IN1 = 2.5v , 0V
4. VSIM=5.5V,R8V,M80UA
⑸ ⑹ ⑺
5. LIMIT DC=10UA,-10UA ⑸ Set the driver output
6. PD1-14=IN1,FIXL voltage
7. P33-36=IN1,FIXL ⑹ VIH
8. TIME1=2MS:VS1
⑺ VIL
9. TIME2=3MS:IN1,DC
10. PD1=DC
11. TEST 100
12. MEAS DC
13. END
2. DC Parametric Test

2.1.2 Program example

VSIM = 5.5V, R8V, M80UA
⑻ ⑼ ⑽ ⑾
1. PRO IIH
⑻ Setting of DCTU
2. VS1=5.5V
(Voltage source current I
3. IN1=2.5V,0V measurement unit)
4. VSIM=5.5V,R8V,M80UA
⑼ Applied voltage
5. LIMIT DC=10UA,-10UA
6. PD1-14=IN1,FIXL ⑽ Applied voltage range
7. P33-36=IN1,FIXL ⑾ Measurement range
8. TIME1=2MS:VS1 Note:
9. TIME2=3MS:IN1,DC Applied voltage range and measurement range are
depended on the applied voltage, limit value and
10. PD1=DC
system spec.
11. TEST 100 VSIM=5.5V,R8V,M(AUTO, 80UA)
12. MEAS DC
80UA is initial range. When the measured value
13. END exceeds the initial range, the range is automatically
switched to the high range by one level and
measurement is executed again.
2. DC Parametric Test

2.1.2 Program example

1. PRO IIH
LIMIT DC = 10UA, -10UA
2. VS1=5.5V
⑿ ⒀ ⒁ ⒂
3. IN1=2.5V,0V
4. VSIM=5.5V,R8V,M80UA ⑿ Setting of Judgment
criterion
5. LIMIT DC=10UA,-10UA
6. PD1-14=IN1,FIXL ⒀ Name of the unit to be
7. P33-36=IN1,FIXL measured (VSIM)
8. TIME1=2MS:VS1 ⒁ Upper limit value
9. TIME2=3MS:IN1,DC
⒂ Lower limit value
10. PD1=DC
11. TEST 100 Note:
12. MEAS DC If no limit setting, “0” or “NEGLECT” can be set.
13. END Pay attention to the different between “0” and “0MA”.
2. DC Parametric Test

2.1.2 Program example

1. PRO IIH
2. VS1=5.5V This is an instruction to select the hardware to
3. IN1=2.5V,0V be connected with each pin.

4. VSIM=5.5V,R8V,M80UA
5. LIMIT DC=10UA,-10UA PDn = … … the driver channel
6. PD1-14=IN1,FIXL
PCn = … … the comparator channel
7. P33-36=IN1,FIXL
Pn = … … the I/O channel
8. TIME1=2MS:VS1
9. TIME2=3MS:IN1,DC
PD1-14 and P33-36 hold low level.
10. PD1=DC
Target pin PD1 is connected to DCTU.
11. TEST 100
12. MEAS DC
13. END
2. DC Parametric Test

2.1.2 Program example

1. PRO IIH
2. VS1=5.5V
3. IN1=2.5V,0V
4. VSIM=5.5V,R8V,M80UA
5. LIMIT DC=10UA,-10UA
6. PD1-14=IN1,FIXL
7. P33-36=IN1,FIXL
8. TIME1=2MS:VS1
9. TIME2=3MS:IN1,DC
10. PD1=DC
11. TEST 100
12. MEAS DC The instruction to define an order of
13. END ON and OFF of hardware. (Default: 3MS)
2. DC Parametric Test

2.1.2 Program example

1. PRO IIH
TIME1 = 2MS:VS1
2. VS1=5.5V
TIME2 = 3MS:IN1,DC
3. IN1=2.5V,0V
4. VSIM=5.5V,R8V,M80UA
5. LIMIT DC=10UA,-10UA
6. PD1-14=IN1,FIXL VS1

7. P33-36=IN1,FIXL ... ...

8. TIME1=2MS:VS1
9. TIME2=3MS:IN1,DC IN1, DC

10. PD1=DC
2MS 3MS 2MS
11. TEST 100 NEXT
SRON SROF
12. MEAS DC STEP

13. END
2. DC Parametric Test

2.1.2 Program example

1. PRO IIH
Another mode:
2. VS1=5.5V
3. IN1=2.5V,0V
4. VSIM=5.5V,R8V,M80UA
5. LIMIT DC=10UA,-10UA
6. PD1-14=IN1,FIXL
7. P33-36=IN1,FIXL
8. TIME1=2MS:VS1
9. TIME2=3MS:IN1,DC
10. PD1=DC
11. TEST 100
12. MEAS DC
13. END
2. DC Parametric Test

2.1.2 Program example

1. PRO IIH
2. VS1=5.5V TEST statement is used in various
3. IN1=2.5V,0V processes on measurement. For
example, at data logging, a report
4. VSIM=5.5V,R8V,M80UA
which is easy to observe can be
5. LIMIT DC=10UA,-10UA
obtained.
6. PD1-14=IN1,FIXL
Always use one TEST statement for
7. P33-36=IN1,FIXL
one MEAS statement.
8. TIME1=2MS:VS1
9. TIME2=3MS:IN1,DC
10. PD1=DC
11. TEST 100
12. MEAS DC
13. END
2. DC Parametric Test

2.1.2 Program example

MEAS DC
1. PRO IIH
2. VS1=5.5V MEAS VSn
3. IN1=2.5V,0V MEAS MPAT filename
4. VSIM=5.5V,R8V,M80UA
5. LIMIT DC=10UA,-10UA
Note:
6. PD1-14=IN1,FIXL
MEAS/T/C DC(PD1-14)
7. P33-36=IN1,FIXL
/T: change test number automatically according to
8. TIME1=2MS:VS1
the measurement pin.
9. TIME2=3MS:IN1,DC
/C: overridden, however, in the data log mode.
10. PD1=DC
MEAS DC & MEAS VSn: SRON> test> judge pass/fail>
11. TEST 100
display result
12. MEAS DC
MEAS MPAT filename: SEND MPAT> SRON> START
13. END
MPAT> test> judge pass/fail>
display result
2. DC Parametric Test

2.1.2 Program example

1. PRO IIH
2. VS1=5.5V
3. IN1=2.5V,0V
4. VSIM=5.5V,R8V,M80UA
5. LIMIT DC=10UA,-10UA
6. PD1-14=IN1,FIXL Compilation stop instruction
7. P33-36=IN1,FIXL
8. TIME1=2MS:VS1
9. TIME2=3MS:IN1,DC
10. PD1=DC
11. TEST 100
12. MEAS DC
13. END
2. DC Parametric Test

2.2 Stand-by Current Measurement

2.2.1 Pin assignment & test condition
A measurement conditions shown are extracted from a device data
sheet.

● DC Characteristics （Vcc = 5V±10% Ta = 0～70℃）

Items Symbol Measurement conditions Min. Max. Unit Notes

Standby current Icc2 RAS,CAS=VIH(2.4V) - 2 mA 1

Notes）１． Specified values are obtained with outputs unloaded.

2. DC Parametric Test

2.2.1 Pin assignment & test condition

According to the above data sheets, measurement conditions are

arranged as follow.

- Power supply voltage: 5.5 V

- ADDRESS,/OE: 0.8 V
- /RAS,/CAS,/WE: 2.4 V
- DQ: OPEN
- Pass/fail criteria: MAX. 2.0 mA
2. DC Parametric Test

2.2.1 Pin assignment & test condition

2. DC Parametric Test

2.2.2 Program example

1. PRO ICC2
2. VS1=5.5V,R10V,M4MA
3. IN1=2.4V,0.8V
4. TIME1=2MS:VS1 VS1 = 5.5V, R10V, M4MA
5. TIME2=2MS:IN1 ⑴ ⑵ ⑶ ⑷
6. PD1-10=IN1,FIXL ;ADDRESS
⑴ VS1 to VS2 or VS9 to VS12
7. PD11=IN1,FIXH ;RAS
(option).
8. PD12=IN1,FIXH ;CAS
9. PD13=IN1,FIXH ;WE ⑵ Applied voltage.
10. PD14=IN1,FIXL ;OE
⑶ Applied voltage range.
11. P33-36=OPEN ;DQ
12. PCON=0 ⑷ Current measuring range.
13. VCON=0
14. LIMIT VS1=2MA,NEGLECT
15. TEST 200
16. MEAS VS1
17. END
2. DC Parametric Test

2.2.2 Program example

1. PRO ICC2
2. VS1=5.5V,R10V,M4MA
3. IN1=2.4V,0.8V
4. TIME1=2MS:VS1 /RAS, /CAS = VIH (2.4V)
5. TIME2=2MS:IN1
6. PD1-10=IN1,FIXL ;ADDRESS
7. PD11=IN1,FIXH ;RAS Outputs unloaded:
8. PD12=IN1,FIXH ;CAS P33-36=OPEN
9. PD13=IN1,FIXH ;WE
10. PD14=IN1,FIXL ;OE
11. P33-36=OPEN ;DQ
12. PCON=0
13. VCON=0
14. LIMIT VS1=2MA,NEGLECT
15. TEST 200
16. MEAS VS1
17. END
2. DC Parametric Test

2.2.2 Program example

1. PRO ICC2
2. VS1=5.5V,R10V,M4MA
3. IN1=2.4V,0.8V
4. TIME1=2MS:VS1
5. TIME2=2MS:IN1
6. PD1-10=IN1,FIXL ;ADDRESS
7. PD11=IN1,FIXH ;RAS
8. PD12=IN1,FIXH ;CAS
9. PD13=IN1,FIXH ;WE
10. PD14=IN1,FIXL ;OE C1(1000~10000PF): reduce high frequency
noise and connect with Vcc pin as close as
11. P33-36=OPEN ;DQ
possible.
12. PCON=0
C2(several UF): reduce low frequency noise.
13. VCON=0
14. LIMIT VS1=2MA,NEGLECT
15. TEST 200
16. MEAS VS1
17. END
2. DC Parametric Test

2.2.2 Program example

1. PRO ICC2
2. VS1=5.5V,R10V,M4MA
3. IN1=2.4V,0.8V
4. TIME1=2MS:VS1
5. TIME2=2MS:IN1
6. PD1-10=IN1,FIXL ;ADDRESS
7. PD11=IN1,FIXH ;RAS
8. PD12=IN1,FIXH ;CAS
9. PD13=IN1,FIXH ;WE In general, a bypass capacitor is connected to
reduce a noise, however, a capacitor having big
10. PD14=IN1,FIXL ;OE
capacity affects a measured value at power current
11. P33-36=OPEN ;DQ measurement. Therefore, a bypass capacitor can be
12. PCON=0 disconnected by a relay using PCON statement..
13. VCON=0
14. LIMIT VS1=2MA,NEGLECT PCON=0: The relay is disconnected.
15. TEST 200
(Initial value)
16. MEAS VS1
17. END
PCON=VS1: The relay is connected to
the VS1.
2. DC Parametric Test

2.2.2 Program example

1. PRO ICC2
2. VS1=5.5V,R10V,M4MA
3. IN1=2.4V,0.8V
4. TIME1=2MS:VS1 ①VCON=0 ②VCON=VS1
5. TIME2=2MS:IN1

ＡＤＶＡＮＴＥＳＴ

ＡＤＶＡＮＴＥＳＴ
device

device
6. PD1-10=IN1,FIXL ;ADDRESS ON OFF
7. PD11=IN1,FIXH ;RAS PPS PPS
Vcc Vcc
8. PD12=IN1,FIXH ;CAS
A A
9. PD13=IN1,FIXH ;WE
10. PD14=IN1,FIXL ;OE
11. P33-36=OPEN ;DQ
12. PCON=0
13. VCON=0
14. LIMIT VS1=2MA,NEGLECT
15. TEST 200
16. MEAS VS1
17. END
2. DC Parametric Test

2.2.2 Program example

1. PRO ICC2
2. VS1=5.5V,R10V,M4MA
3. IN1=2.4V,0.8V
4. TIME1=2MS:VS1
5. TIME2=2MS:IN1
6. PD1-10=IN1,FIXL ;ADDRESS
7. PD11=IN1,FIXH ;RAS
8. PD12=IN1,FIXH ;CAS
9. PD13=IN1,FIXH ;WE
10. PD14=IN1,FIXL ;OE Set the limit value for pass/fail
11. P33-36=OPEN ;DQ criteria for the value measured
12. PCON=0
by MEAS VS statement.
13. VCON=0
14. LIMIT VS1=2MA,NEGLECT
15. TEST 200
16. MEAS VS1
17. END
2. DC Parametric Test

2.3 Operating Current Measurement

2.3.1 Pin assignment & test condition
A measurement conditions shown are extracted from a device data
sheet.

● DC Characteristics （Vcc = 5V±10% Ta = 0～70℃）

Items Symbol Measurement conditions Min. Max. Unit Notes

Operating current Icc1 RAS,CAS cycling

- 80 mA 1,2
tRC=Min

Notes） 1．Specified values are obtained with outputs unloaded.

2．Icc1 is measurd assuming that address can be changed once or less during RAS = VIL
2. DC Parametric Test

2.3.1 Pin assignment & test condition

According to the above data sheets, measurement conditions are

arranged as follow.
2. DC Parametric Test

2.3.2 Program example

1. PRO ICC1
2. VS1=5.5V,R10V,M400MA
3. IN1=2.4V,0.8V
4. TIME1=1MS: VS1
5. TIME2=4MS: IN1
6. PD1-10=IN1,FIXL;ADDRESS
7. PD11=IN1,/RZ0,BCLK4,CCLK4,<C0>;/RAS
8. PD12=IN1,/RZ0,BCLK5,CCLK5,<C1>;/CAS
9. PD13=IN1,FIXH;/WE
10. PD14=IN1,FIXL;DIN Voltage condition:
11. P33-36=OPEN;DOUT
12. RATE=130NS IN1 = 2.4V, 0.8V
13. BCLK4=15NS & CCLK4=115NS ⑴ ⑵ ⑶
14. BCLK5=60NS & CCLK5=115NS
15. PCON=VS1 ⑴ 1 to 16
16. LIMIT VS1=80MA,NEGLECT
17. CALL CALB("CICC1","NORMAL") ⑵ VIH
18. SEND MPAT PICC1
19. REG MPAT PC=#0 ⑶ VIL
20. START MPAT*
21. WAIT TIME 1MS
22. TEST 300
23. MEAS VS1
24. STOP MPAT
25. END
2. DC Parametric Test

2.3.2 Program example

1. PRO ICC1
2. VS1=5.5V,R10V,M400MA
3. IN1=2.4V,0.8V
4. TIME1=1MS: VS1
5. TIME2=4MS: IN1
6. PD1-10=IN1,FIXL;ADDRESS
7. PD11=IN1,/RZ0,BCLK4,CCLK4,<C0>;/RAS
8. PD12=IN1,/RZ0,BCLK5,CCLK5,<C1>;/CAS
9. PD13=IN1,FIXH;/WE
10. PD14=IN1,FIXL;DIN Timing condition:
11. P33-36=OPEN;DOUT
12. RATE=130NS tRC(min)=130ns  RATE=130NS
13. BCLK4=15NS & CCLK4=115NS
14. BCLK5=60NS & CCLK5=115NS
BCLK4, CCLK4  /RAS
15. PCON=VS1
BCLK5, CCLK5  /CAS
16. LIMIT VS1=80MA,NEGLECT
17. CALL CALB("CICC1","NORMAL") RATE setting must before all the
18. SEND MPAT PICC1
timing setting.
19. REG MPAT PC=#0
20. START MPAT*
21. WAIT TIME 1MS
22. TEST 300
23. MEAS VS1
24. STOP MPAT
25. END
2. DC Parametric Test

2.3.2 Program example

1. PRO ICC1
2. VS1=5.5V,R10V,M400MA
3. IN1=2.4V,0.8V
4. TIME1=1MS: VS1
5. TIME2=4MS: IN1
6. PD1-10=IN1,FIXL;ADDRESS
7. PD11=IN1,/RZ0,BCLK4,CCLK4,<C0>;/RAS
8. PD12=IN1,/RZ0,BCLK5,CCLK5,<C1>;/CAS
9. PD13=IN1,FIXH;/WE
10. PD14=IN1,FIXL;DIN
11. P33-36=OPEN;DOUT
PD11=IN1, /RZ0, BCLK4, CCLK4, <C0>
12. RATE=130NS
13. BCLK4=15NS & CCLK4=115NS ⑷ ⑸ ⑹ ⑺
14. BCLK5=60NS & CCLK5=115NS
15. PCON=VS1 ⑷ voltage condition for waveform.
16. LIMIT VS1=80MA,NEGLECT
17. CALL CALB("CICC1","NORMAL") ⑸ specify a waveform shaping circuit.
18. SEND MPAT PICC1
19. REG MPAT PC=#0 ⑹ the number of clock.
20. START MPAT*
21. WAIT TIME 1MS ⑺ Pin data, which are names of signals
22. TEST 300
23. MEAS VS1
generated by ALPG.
24. STOP MPAT
25. END
2. DC Parametric Test

2.3.2 Program example

1. PRO ICC1
2. VS1=5.5V,R10V,M400MA
3. IN1=2.4V,0.8V
4. TIME1=1MS: VS1
5. TIME2=4MS: IN1
6. PD1-10=IN1,FIXL;ADDRESS
7. PD11=IN1,/RZ0,BCLK4,CCLK4,<C0>;/RAS
8. PD12=IN1,/RZ0,BCLK5,CCLK5,<C1>;/CAS
9. PD13=IN1,FIXH;/WE
10. PD14=IN1,FIXL;DIN
Pin data:
11. P33-36=OPEN;DOUT
12. RATE=130NS (a) X0 - X15, Y0 - Y15 ; address signals.
13. BCLK4=15NS & CCLK4=115NS
(b) C0 - C15, RD, WT, M1, M2, FH, FL ; control signals
14. BCLK5=60NS & CCLK5=115NS
15. PCON=VS1 such as /RAS, /CAS, /WE.
16. LIMIT VS1=80MA,NEGLECT
17. CALL CALB("CICC1","NORMAL") (c) D0 - 17, SD0 - 17 ; write data and comparison data.
18. SEND MPAT PICC1
19. REG MPAT PC=#0
20. START MPAT*
21. WAIT TIME 1MS
22. TEST 300
23. MEAS VS1
24. STOP MPAT
25. END
2. DC Parametric Test

2.3.2 Program example

1. PRO ICC1
2. VS1=5.5V,R10V,M400MA
3. IN1=2.4V,0.8V
The tester calibrates:
4. TIME1=1MS: VS1
5. TIME2=4MS: IN1 - Skew between driver pins
6. PD1-10=IN1,FIXL;ADDRESS
7. PD11=IN1,/RZ0,BCLK4,CCLK4,<C0>;/RAS
- Skew between comparator pins (includes edge and
8. PD12=IN1,/RZ0,BCLK5,CCLK5,<C1>;/CAS window strobe)
9. PD13=IN1,FIXH;/WE
10. PD14=IN1,FIXL;DIN - Comparator skew corresponding to driver
11. P33-36=OPEN;DOUT
- Driver I/O timing
12. RATE=130NS
13. BCLK4=15NS & CCLK4=115NS
14. BCLK5=60NS & CCLK5=115NS
15. PCON=VS1
16. LIMIT VS1=80MA,NEGLECT
17. CALL CALB("CICC1","NORMAL")
18. SEND MPAT PICC1
19. REG MPAT PC=#0
20. START MPAT*
21. WAIT TIME 1MS
22. TEST 300
23. MEAS VS1
24. STOP MPAT
25. END
2. DC Parametric Test

2.3.2 Program example

1. PRO ICC1
2. VS1=5.5V,R10V,M400MA
3. IN1=2.4V,0.8V
CALL CALB("CICC1","NORMAL")
4. TIME1=1MS: VS1
5. TIME2=4MS: IN1 ⑻ ⑼ ⑽
6. PD1-10=IN1,FIXL;ADDRESS
7. PD11=IN1,/RZ0,BCLK4,CCLK4,<C0>;/RAS ⑻ Activates the calibration program with
8. PD12=IN1,/RZ0,BCLK5,CCLK5,<C1>;/CAS
9. PD13=IN1,FIXH;/WE the CALL statement.
10. PD14=IN1,FIXL;DIN
11. P33-36=OPEN;DOUT ⑼ Specify the name of the file that stores
12. RATE=130NS
13. BCLK4=15NS & CCLK4=115NS calibration data. When the test condition
14. BCLK5=60NS & CCLK5=115NS
15. PCON=VS1
is changed and the calibration is
16. LIMIT VS1=80MA,NEGLECT
executed again, it is necessary to use a
17. CALL CALB("CICC1","NORMAL")
18. SEND MPAT PICC1
different file name.
19. REG MPAT PC=#0
20. START MPAT*
⑽ Specify the normal calibration.
21. WAIT TIME 1MS
22. TEST 300
23. MEAS VS1
24. STOP MPAT
25. END
2. DC Parametric Test

2.3.2 Program example

1. PRO ICC1 Normal Calibration:
2. VS1=5.5V,R10V,M400MA
3. IN1=2.4V,0.8V
The normal calibration is executed by using the output
4. TIME1=1MS: VS1
level of 50% as the calibration point.
5. TIME2=4MS: IN1
6. PD1-10=IN1,FIXL;ADDRESS
7. PD11=IN1,/RZ0,BCLK4,CCLK4,<C0>;/RAS
8. PD12=IN1,/RZ0,BCLK5,CCLK5,<C1>;/CAS
9. PD13=IN1,FIXH;/WE
10. PD14=IN1,FIXL;DIN
11. P33-36=OPEN;DOUT
12. RATE=130NS
13. BCLK4=15NS & CCLK4=115NS
14. BCLK5=60NS & CCLK5=115NS
15. PCON=VS1
16. LIMIT VS1=80MA,NEGLECT
17. CALL CALB("CICC1","NORMAL")
18. SEND MPAT PICC1
19. REG MPAT PC=#0
20. START MPAT*
21. WAIT TIME 1MS
22. TEST 300
23. MEAS VS1
24. STOP MPAT
25. END
2. DC Parametric Test

2.3.2 Program example

1. PRO ICC1
2. VS1=5.5V,R10V,M400MA
In the following cases, calibration must be executed
3. IN1=2.4V,0.8V
again.
4. TIME1=1MS: VS1
5. TIME2=4MS: IN1 1. When waveform mode is changed.
6. PD1-10=IN1,FIXL;ADDRESS
7. PD11=IN1,/RZ0,BCLK4,CCLK4,<C0>;/RAS
2. When level of driver is changed.
8. PD12=IN1,/RZ0,BCLK5,CCLK5,<C1>;/CAS
9. PD13=IN1,FIXH;/WE
3. When clock selection or strobe selection is changed.
10. PD14=IN1,FIXL;DIN
11. P33-36=OPEN;DOUT
12. RATE=130NS
13. BCLK4=15NS & CCLK4=115NS
14. BCLK5=60NS & CCLK5=115NS
15. PCON=VS1
16. LIMIT VS1=80MA,NEGLECT
17. CALL CALB("CICC1","NORMAL")
18. SEND MPAT PICC1
19. REG MPAT PC=#0
20. START MPAT*
21. WAIT TIME 1MS
22. TEST 300
23. MEAS VS1
24. STOP MPAT
25. END
2. DC Parametric Test

2.3.2 Program example

18. SEND MPAT PICC1 * no*
19. REG MPAT PC=#0 Pattern program:
20. START MPAT*
21. WAIT TIME 1MS 1. MPAT PICC1
2. START #0
22. TEST 300 3. JMP. C0 C1
23. MEAS VS1 4. STPS
5. END
24. STOP MPAT
25. END

Transfer the patterns stored in a disk into the ALPG memory.

The REG MPAT PC statement determines the address to access the instruction memory.

The START MPAT statement is used to operate ALPG according to MPAT program in
instruction memory. This instruction contains SRON function. This statement doesn't
judge PASS/FAIL. When "*" is added like START MPAT*, the main program is continued
at the same time with ALPG start.

Settling time from starting of ALPG to starting of measurement.

The pattern can be forcibly stopped with the STOP MPAT statement.
Dynamic Functional Test
3. Dynamic Functional Test

3.1 Main Program for Function Test

3.1.1 Test condition
Write cycle Read cycle
200 200

RAS
(PD11) 15 115 15 115 Row address strobe
CAS
(PD12) 60 115 60 115 Column address strobe
0 10 30 40 50 120 0 10 30 40 50 120
ADDRESS
(PD1-10)
R C R C Address input

WE
(PD13) 55 150 Write enable
OE
(PD14) 40 135 Output enable
45 145
DQ Data-in Data-out Data input/output
(P33-36)
130
STRB1 Data strobe

(ns)
3. Dynamic Functional Test

3.1 Main Program for Function Test

3.1.1 Test condition
● Recommended Operation Conditions （Ta = 0～70℃）
Items Symbol Min. Typ. Max. Unit
Power supply VCC 4.5 5.0 5.5 V
voltage
VSS 0 0 0 V

“H”input voltage VIH 2.4 - 6.5 V

“L”input voltage VIL - 0.1 - 0.8 V

● DC Characteristics （Vcc = 5V±10% Ta = 0～70℃）

Items Symbol Measurement conditions Min. Max. Unit Notes
MSCAN pattern
“H”input voltage VOH IOH=-5.0mA 2.4 - V Address W0 R0 W1 R1
“L”input voltage VOL IOL=4.2mA - 0.4 V

注記） ４． 測定負荷条件は２ＴＴＬと１００ｐＦです。

W0 R0 W1 R1
W0 R0 W1 R1
0 W0 R0 W1 R1
W0:Write 0 W1:Write 1 t
R0:Read 0 R1:Read 1
3. Dynamic Functional Test

3.1.2 Main program example

PRO DRAM4M Program title
VS1=5.5V
IN1=2V,0V
OUT1=2V,0.4V Voltage condition
IL1=-5MA,4.2MA
VT1=1.4V
RATE=200NS ;RATE
ACLK1= 0NS & BCLK1=10NS & CCLK1= 30NS ;ROW ADDRESS
ACLK2=40NS & BCLK2=50NS & CCLK2=120NS ;COL ADDRESS
ACLK3= 0NS & BCLK3=35NS & CCLK3= 155NS ;DQ0-3
BCLK4=15NS & CCLK4=115NS ;/RAS
BCLK5=60NS & CCLK5=115NS ;/CAS Timing condition
BCLK6=55NS & CCLK6=150NS ;/WE
BCLK7=40NS & CCLK7=135NS ;/OE
DREL1= 45NS
DRET1=145NS
STRB1=130NS
SELECT DCLK ACLK1 BCLK1 CCLK1

Note: Don’t need this statement in T55XX system.

3. Dynamic Functional Test

3.1.2 Main program example

PINLIST AD =PD1-10 ;A0-A9
PINLIST RAS =PD11 ;/RAS
Pin list setting PINLIST CAS =PD12 ;/CAS
PINLIST WE =PD13 ;/WE
PINLIST OE =PD14 ;/OE
PINLIST IOPIN=P33-36 ;DQ0-3
AD =IN1,XOR,ACLK1,BCLK1,CCLK1,SDM,<X0-9,Y0-9>
RAS =IN1,/RZO,BCLK4,CCLK4,<C0>
CAS =IN1,/RZO,BCLK5,CCLK5,<C1>

Pin condition WE =IN1,/RZO,BCLK6,CCLK6,<WT>

OE =IN1,/RZO,BCLK7,CCLK7,<RD>
IOPIN=IN1,XOR,ACLK3,BCLK3,CCLK3,DRERZ,DRE1,DRECLK1,IOC,@
OUT1,STRB1,CPE1,IL1,VT1,<D0-3>
TIME1=2MS:VS1
Power sequence TIME2=2MS:IN1
TIME3=2MS:VT1,IL1
Bypass capacitance setting PCON=VS1
Auto calibration CALL CALB("FUNC","NORMAL")

Test number setting TEST 400

Measure control REG MAPT PC=#0

MEAS MPAT P4MDRAM

Test number setting END

3. Dynamic Functional Test

3.1.2 Main program example

Key statement SELECT DCLK ACLK1 BCLK1 CCLK1

We don’t need this statement in T55XX test system.

T53

Pin data A,B A B Dr A A A B B B

DCLK
A1 B1 C1
A2 B2 C2
FC

T55

A OR
Pin data A Dr A A A B B B

CLK(2n-1)
A1 B1 C1

B
Pin data B

CLK(2n)
A2 B2 C2
TGFC
3. Dynamic Functional Test

3.1.2 Main program example

Key statement AD =IN1,XOR,ACLK1,BCLK1,CCLK1,SDM,<X0-9,Y0-9>

If the SDM statement is specified within a pin condition statement, pin data A and pin data B
are assigned to CLK(2n-1) and CLK(2n), respectively.

<X0-9,Y0-9>
3. Dynamic Functional Test

3.1.2 Main program example

Key statement

IOPIN=IN1,XOR,ACLK3,BCLK3,CCLK3,DRERZ,DRE1,DRECLK1,IOC,@
OUT1,STRB1,CPE1,IL1,VT1,<D0-3>

☆ IOC is the specification to enable the I/O control using the DRE pattern.

☆ DRE1 and DRE2 patterns specify DRE patterns and enable the pin drivers specified DRERZ or DRENRZ.
(default control signal: W)
☆ DRELn and DRETn are timing clocks that determine the valid range of those pins that have either
DRERZ or DRENRZ specified. DREL1 to DREL128 and DRET1 to DRET128 are available.
☆ DRECLKn is an I/O control clock selection statement.
3. Dynamic Functional Test

3.1.2 Main program example

Key statement

IOPIN=IN1,XOR,ACLK3,BCLK3,CCLK3,DRERZ,DRE1,DRECLK1,IOC,@
OUT1,STRB1,CPE1,IL1,VT1,<D0-3>

☆ DRERZ & DRENRZ mode:

DRE1

DREL1
DRET1

Pout（DRERZ）

Pout（DRENRZ）
3. Dynamic Functional Test

3.1.2 Main program example

Key statement

IOPIN=IN1,XOR,ACLK3,BCLK3,CCLK3,DRERZ,DRE1,DRECLK1,IOC,@
OUT1,STRB1,CPE1,IL1,VT1,<D0-3>

☆ OUTn sets the connects the comparator to the device.

It also selects channel n of the VO as the comparison voltage. There are 16 channels: OUT1 to OUT16.
When OUTLm is described, the device output can be terminated .
3. Dynamic Functional Test

3.1.2 Main program example

Key statement

IOPIN=IN1,XOR,ACLK3,BCLK3,CCLK3,DRERZ,DRE1,DRECLK1,IOC,@
OUT1,STRB1,CPE1,IL1,VT1,<D0-3>

☆ Comparison types

Dout

Edge strobe 1. Edge strobe:

Comparison PC33 = OUT1, STRB1, <D0>

Double strobe 2. Double strobe:

Comparison
PC33 = OUT1, STRB1, STRB2, <D0>

Window strobe 3. Window strobe:

Comparison WSTRB1 = 30NS, 40NS
PC33 = OUT1, WSTRB1, <D0>
Hz comparison
3. Dynamic Functional Test

3.1.2 Main program example

Key statement

IOPIN=IN1,XOR,ACLK3,BCLK3,CCLK3,DRERZ,DRE1,DRECLK1,IOC,@
OUT1,STRB1,CPE1,IL1,VT1,<D0-3>

☆ Comparison types

4. HZ comparison:
Dout
Mode1:
SELECT HZSNESE ENABLE
Edge strobe PC33 = OUT1, STRB2, <D0> ;even strobe
Comparison SELECT HZSNESE ENABLE

Double strobe Mode2:

Comparison PC33 = OUT1, STRB1, <D0>
PC34 = OUT1, STRB2, HZ2 <D0>
Window strobe PC35 = OUT1, STRB3, HZ1 <D0>
Comparison PC36 = OUT1, STRB4, <D0>

Hz comparison
3. Dynamic Functional Test

3.1.2 Main program example

Key statement

IOPIN=IN1,XOR,ACLK3,BCLK3,CCLK3,DRERZ,DRE1,DRECLK1,IOC,@
OUT1,STRB1,CPE1,IL1,VT1,<D0-3>

☆ CPE pattern controls the comparison process.

Define one of CPE1 to CPE4 in the REGISTER division of the pattern program.
(default control : R)
3. Dynamic Functional Test

3.1.2 Main program example

Key statement

IOPIN=IN1,XOR,ACLK3,BCLK3,CCLK3,DRERZ,DRE1,DRECLK1,IOC,@
OUT1,STRB1,CPE1,IL1,VT1,<D0-3>

☆ The process of connecting and

disconnecting the programmable load
can be controlled by using ILn or
ILALLn statement of pin conditions.
Note that it is used with VTn statement.
3. Dynamic Functional Test

3.1.2 Main program example

Key statement
PC33=OUT1,STRB1, LOAD, <D0> ;Use D0 as an expected pattern value.
OUT1=2V,0.4V
LCON=1 ;Load circuit connection control instruction

☆ Excepting load circuits (programmable load) incorporated in test systems, other load circuits can
also be connected to the test systems as a peripheral circuit.
Use LOAD and LCON instructions for pin conditions statement.
3. Dynamic Functional Test
3.2 Pattern Program for Function Test
3.2.1 Format of MPAT program
MPAT JUSTIN
SDEF definition MPAT JUSTIN

REGISTER Pattern program name. It must be a character string

within eight alphanumeric characters starting with an
alphabetical character. Name described here becomes
file name of object program.
MODULE BEGIN
REGISTER

START #0

STPS Pattern A
MODULE END

MODULE BEGIN
REGISTER

START #10

STPS Pattern B
MODULE END

END
3. Dynamic Functional Test

3.2.1 Format of MPAT program

MPAT JUSTIN
SDEF definition SDEF definition

REGISTER Address generator and data generator programs

can be defined as any character strings with the
SDEF statement.
MODULE BEGIN
REGISTER
Sample:
START #0
SDEF RD1 = R C0 C1 /D

Pattern A SDEF TARG = X<XB Y<YB

STPS
MODULE END SDEF DIST = X<XC Y<YC
MODULE BEGIN SDEF AINV = /X /Y
REGISTER
SDEF CLER = XB<0 YB<0 TP<0
START #10

STPS Pattern B
MODULE END

END
3. Dynamic Functional Test

3.2.1 Format of MPAT program

MPAT JUSTIN
SDEF definition MODULE pattern

REGISTER The MODULE statement allows you to describe

several patterns in one MPAT program. The initial
register setting can be redefined in a module with
the MODULE statement.
MODULE BEGIN
REGISTER
The priority of register definition:
START #0
High

Pattern A REG MPAT PC statement in main program

STPS
MODULE END Register definition in module
MODULE BEGIN Common register definition
REGISTER
Low
START #10

STPS Pattern B
MODULE END

END
3. Dynamic Functional Test

3.2.1 Format of MPAT program

MPAT JUSTIN
SDEF definition END

REGISTER
Stops the compilation.

MODULE BEGIN
REGISTER

START #0

STPS Pattern A
MODULE END

MODULE BEGIN
REGISTER

START #10

STPS Pattern B
MODULE END

END
3. Dynamic Functional Test

3.2.2 Setting of pattern storage address

The pattern to be used is specified with the REG MPAT PC statement of the main program.
Set REG MPAT PC statement for each MEAS.

PRO MABC MPAT PABC

START #0
TEST 100
REG MPAT PC=#0
Pattren A
MEAS MPAT PABC
STPS

TEST 200 START #10

REG MPAT PC=#10
MEAS MPAT PABC
Pattren B
STPS
3. Dynamic Functional Test

3.2.3 Common sequence control instructions

NOP instruction

This instruction increments the program counter by one.

3. Dynamic Functional Test

3.2.3 Common sequence control instructions

JNI instruction

This instruction repeats executing a program of several lines for the number of times of the index
register value plus 2.

Dot (.) means relative address specifying, indicating PC itself.

3. Dynamic Functional Test

3.2.3 Common sequence control instructions

JZD instruction

This instruction changes the execution sequence of a program by using the value set in
the DFLG. Used to generate a background pattern.
3. Dynamic Functional Test

3.2.3 Common sequence control instructions

IDXIn instruction

The IDXI instruction repeats executing its

own line the number of times specified by
an operand plus two times.
3. Dynamic Functional Test

3.2.3 Common sequence control instructions

JSR & RTN instruction

These instructions branch to the address

specified by an operand. The RTN
instruction in the destination subroutine
returns control to the line next to the JSR
instruction. Up to four levels of
subroutines can be nested.
3. Dynamic Functional Test

3.2.3 Common sequence control instructions

JMP instruction

The JMP instruction performs a

conditional branch to the address
specified by an operand. It is
used to form a permanent loop
such as when measuring the
operating supply current.
3. Dynamic Functional Test

3.2.4 Address generator

D3B
1. XB, YB: Base registers (16bits) D4B
2. XH, YH: Hold registers (16bits, default value #0)
3. D1, D2: Constant register (16bits)
4. D3, D4: Variable register (16bits) XH D1 D3 XS

5. XC, YC: Current register (16bits) D2 D4

XK
6. XS, YS
XK, YK: Save register (16bits)
XB XC
7. D3B,D4B: Stores the initial values of D3, D4 register.
(16bits)
8. LMAX : MAX register for conditional operation of register MUX
XB and XC. (16 bits)
/X
9. HMAX : MAX register for conditional operation of register
XOR
YB and YC. (16 bits)
10.XMAX : Determines an effective bit of each register of XB and XC.
(16 bits) X0-X15

11.YMAX : Determines an effective bit of each register of YB and YC. (16 bits)
Note: Bits of registers is depending on the test system.
3. Dynamic Functional Test

3.2.4 Address generator

D3B

Note: D4B

XB and YB can only transfer data to XC and YC.

For example:
XH D1 D3 XS
XC < XB + 1 is right. D2 D4
XK
XB < XC + 1 is wrong.

XB XC
Base register and current register can’t be
Mixed to generate address.
For example: MUX

/X
NOP X < XB Y < YB is right.
XOR
NOP X < XB Y < YC is wrong.

X0-X15
3. Dynamic Functional Test

3.2.4 Address generator

• XB<0 YB<0 XC<0 YC<0
Clears the base register and the current register. This operation must be executed before applying
any test patterns.

• XB<XB+1 YB<YB+1 ^BX

Increments the base register. ^BX indicates that the operation of the YB register is executed when
the XB register is loaded with the same value as the LMAX register.
3. Dynamic Functional Test

3.2.4 Address generator

• XB<XB+1 YB<YB+1 ^ BX /X /Y
Decrements the address from the maximum value using a base register.
/X and /Y invert the result of operation.
3. Dynamic Functional Test

3.2.4 Address generator

• XC<XC+1 YC<YC+1 ^ CY
Increments the current register. ^CY indicates that the operation of the YC register is
executed when data in the XC register exceeds the value set in the LMAX register.
Especially, when the current register is operated with the D register, data in the XC
register may not match that of the LMAX register depend on the value set the D register. In
this case, use ^CY.
3. Dynamic Functional Test

3.2.4 Address generator

• XC<XC-1 YC<YC-1 ^CY
Operation of the current register decrement.
IF XC-1 < 0
THEN YC < YC-1
ELSE YC < YC

Please try it!!!

3. Dynamic Functional Test

3.2.4 Address generator

• XB<XB-1 YB<YB-1 ^BX
IF XB = LMAX
THEN YB < YB-1
ELSE YB < YB

Please try it!!!

3. Dynamic Functional Test

3.2.4 Address generator

• XB<XB-1 YB<YB-1 ^BX
IF XB = LMAX
THEN YB < YB-1
ELSE YB < YB

12 11 10 13

8 7 6 9

4 3 2 5

16 15 14 1

Please try it!!!

3. Dynamic Functional Test

3.2.5 Data generator

TP data is inverted when DFLG=1. TP data is not inverted when DFLG=0.

The value of DFLG is controlled by JZD instruction.
At DFLG=0 (initial value): 1 is set to the DFLG and program control jumps to the label.
At DFLG=1: 0 is set to the DFLG and PC is incremented by 1.
3. Dynamic Functional Test

3.2.5 Data generator

Assuming that TP=0

MPAT PWAVEC
TP is inverted to obtain 1 for expected
.....
value in the first cycle.
NOP /D
In the second cycle, /D is not necessary
NOP
because the expected value is 0.
3. Dynamic Functional Test

3.2.5 Data generator

Used to invert data in TP register. The inverted data is loaded into the TP.
The load operation takes one cycle, so the inverted data is available from the next cycle.
3. Dynamic Functional Test

3.2.6 Pattern program example

1 MPAT P4MDRAM Pattern program name
2 REGISTER
3 XMAX=#3FF
4 YMAX=#3FF
5 LMAX=#3FF
6 HMAX=#3FF Set register
7 TPH=#0
8 IDX1=#5
9 IDX2=#FFFFE
10 DRE1=W
11 CPE1=R
12 MODE MUX Mode statement
13 START #0 The first address of pattern storage
14 NOP XB<0 YB<0 TP<TPH C0
15 HS1: JNI1 HS1 C0
Pattern generation controller
16 HS2: JNI2 HS2 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 W
17 HS3: JNI2 HS3 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 R
18 JZD HS2
19 STPS Stop pattern generation
20 END Stop compilation
3. Dynamic Functional Test

3.2.7 Basic of pattern

Address Control signal Data
X 0 0 1 1 X1
0 1 0 1 X0 Col Row RAS CAS WE DQ
Y 00 00 1 1 1 0
0 0
W W W W
00 01 1 1 1 0
R R R R
00 10 1 1 1 0
0 1 W W W W Write
00 11 1 1 1 0
R R R R cycle
W W W W
1 0 R
R R R
11 11 1 1 1 0
W W W W
1 1
R R R R
Col Row RAS CAS OE DQ
Y1 Y0 00 00 1 1 1 0
00 01 1 1 1 0
00 10 1 1 1 0
Read 00 11 1 1 1 0
cycle

11 11 1 1 1 0
3. Dynamic Functional Test

3.2.7 Basic of pattern

Come true by statements!
Address Control signal Data
Address Address output Address RAS CAS WE DQ
#0 X<XB Y<YB XB<XB+1 YB<YB+1^BX
operation C0 C1 W 0
#1 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 W 0
#2 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 W 0
Write #3 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 W 0
cycle

#F X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 W 0

Address Address output Address operation RAS CAS OE DQ
#0 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 R 0
#1 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 R 0
#2 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 R 0
Read #3 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 R 0
cycle

#F X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 R 0

3. Dynamic Functional Test

3.2.7 Basic of pattern

2 REGISTER . Register declarative statement. Specify initial value of each
register after the register declarative statement.
3 XMAX=#3FF
4 YMAX=#3FF
5 LMAX=#3FF
6 HMAX=#3FF
7 TPH=#0
8 IDX1=#5
9 IDX2=#FFFFE
10 DRE1=W
11 CPE1=R
3. Dynamic Functional Test

3.2.7 Basic of pattern

2 REGISTER
3 XMAX=#3FF
4 YMAX=#3FF . Setting for the XMAX and YMAX registers. Normally, the
maximum row address and the maximum column address are
5 LMAX=#3FF
set in XMAX and YMAX respectively. LMAX and HMAX are set
6 HMAX=#3FF for address carry.

7 TPH=#0 HMAX
MSB LSB

LMAX
MSB LSB

XB=LMAX ?
8 IDX1=#5 MSB LSB MSB LSB
YB XB
9 IDX2=#FFFFE
ALU ALU
10 DRE1=W MSB LSB MSB LSB

YMAX XMAX
11 CPE1=R
MSB LSB MSB LSB

Y X

Y1,Y0 X1,X0
3. Dynamic Functional Test

3.2.7 Basic of pattern

2 REGISTER
3 XMAX=#3FF
4 YMAX=#3FF
5 LMAX=#3FF
6 HMAX=#3FF
. The TPH initializes register TP.
7 TPH=#0
8 IDX1=#5
9 IDX2=#FFFFE
10 DRE1=W
11 CPE1=R
3. Dynamic Functional Test

3.2.7 Basic of pattern

2 REGISTER
3 XMAX=#3FF
4 YMAX=#3FF
5 LMAX=#3FF
6 HMAX=#3FF
7 TPH=#0
8 IDX1=#5 . The IDXm registers store the number of loops.
And the actual executing time is IDXn plus 2.
9 IDX2=#FFFFE
10 DRE1=W
11 CPE1=R
3. Dynamic Functional Test

3.2.7 Basic of pattern

2 REGISTER
3 XMAX=#3FF
4 YMAX=#3FF
5 LMAX=#3FF
6 HMAX=#3FF
7 TPH=#0
8 IDX1=#5
9 IDX2=#FFFFE
10 DRE1=W . Setting control signal for DRE1 and CPE1, normally W is
default for DREn and R is default for CPEn.
11 CPE1=R
3. Dynamic Functional Test

3.2.7 Basic of pattern

12 MODE MUX

Specify the special ALPG operation mode.

MUX specifies address multiplex mode.
The following modes are often used:

MODE PAUSE : Specifies the pause test.

MODE REFRESH : Specifies the automatic refresh mode.
MODE TPMn (n=18 or 36): Specifies bit size of TP register.
3. Dynamic Functional Test

3.2.7 Basic of pattern

13 START #0
14 NOP XB<0 YB<0 TP<TPH C0
15 HS1: JNI1 HS1 C0
16 HS2: JNI2 HS2 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 W
17 HS3: JNI2 HS3 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 R
18 JZD HS2
19 STPS

Specify the start address used to store the pattern program into the instruction memory. In
this program, START #0 stores the program from the 14th line down from address 0 of the
instruction memory.
3. Dynamic Functional Test

3.2.7 Basic of pattern

13 START #0
14 NOP XB<0 YB<0 TP<TPH C0
15 HS1: JNI1 HS1 C0
16 HS2: JNI2 HS2 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 W
17 HS3: JNI2 HS3 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 R
18 JZD HS2
19 STPS

DRAMs must be initialized before a pattern is applied for testing. Normally, several refresh
operations must be executed. This statement also sets initial values of XB, YB, and TP. These
registers must be set with the initial values.
3. Dynamic Functional Test

3.2.7 Basic of pattern

13 START #0
14 NOP XB<0 YB<0 TP<TPH C0
15 HS1: JNI1 HS1 C0
16 HS2: JNI2 HS2 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 W
17 HS3: JNI2 HS3 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 R
18 JZD HS2
19 STPS

Writes 0 into all memory cells. (current TP=#0)

Read 0 to all memory cells.
HS2 & HS3: indicate the jump label name.

HS2: JNI2 HS2 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 W

(A) (B) (C) (D) (E) (F)

(A) (B) (C): Sequence control field (A) Label name

(D) (E) (F): ALPG instruction field (B) Sequence controller
(C) Operand
(D) Address output command
(E) Address operation command
(F) Control signal output command
3. Dynamic Functional Test

3.2.7 Basic of pattern

13 START #0
14 NOP XB<0 YB<0 TP<TPH C0
15 HS1: JNI1 HS1 C0
16 HS2: JNI2 HS2 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 W
17 HS3: JNI2 HS3 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 R
18 JZD HS2
19 STPS

Generates a background pattern with the JZD instruction.

The value of DFLG is controlled by JZD instruction.

Role of JZD HS2:

At DFLG=0 (initial value):
1 is set to the DFLG and program control jumps to HS2 and reverse TP output value.
At DFLG=1:
0 is set to the DFLG and PC is incremented by 1 and reverse TP output value.
3. Dynamic Functional Test

3.2.7 Basic of pattern

13 START #0
14 NOP XB<0 YB<0 TP<TPH C0
15 HS1: JNI1 HS1 C0
16 HS2: JNI2 HS2 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 W
17 HS3: JNI2 HS3 X<XB Y<YB XB<XB+1 YB<YB+1^BX C0 C1 R
18 JZD HS2
19 STPS

Sets the result to Pass then returns program execution to the main program.
Thank
You!
ASC-SE
2004.4.28.