EC792 HPCA

Modelling of Digital Systems

EC806

Objectives
• At the end of the lecture the student
must be able to
– Appreciate top-down design methodology,
need for HDL
– Model combinational circuits using verilog

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Digital System implementation options

DIGITAL SYSTEMS

STANDARD
COMPONENTS ASIC

TTL, CMOS P SEMI CUSTOM FULL CUSTOM PROGRAMMABLE

CELL GATE SPLD

CPLD FPGA
BASED ARRAY (PAL)

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Evaluation criteria
• Size • Speed
• Power • Reliability
• NRE
• Security
• Component cost
• Assembly cost • Flexibility
• Time to market
• Risk

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FPGA
◼ Logic blocks
◼ Implement combinational
and sequential logic
◼ Interconnect
◼ Wires to connect inputs
and outputs to logic
blocks
◼ I/O blocks
◼ Special logic blocks at
periphery of device for
external connections

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Design Flow
Design Entry Schematic, HDL, State diagrams

Analysis Behavioural simulation

HDL to Gate level netlist

Synthesis
Functional simulation

Implementation Mapping to CLBs, Place & Route

Timing simulation

Download to device
Configure device
In circuit verification

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FPGA based Design Flow

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What is inside an ASIC or an FPGA?

You are writing HDL code to get this image automatically using the tools

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Design Tools for Electronic Design Automation

• Cadence
• Synopsys
• Siemens/Mentor Graphics
• AMD – Xilinx Vivado
• Intel - Altera Quartus
• Open source tools

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Fabrication facilities
• SCL Chandigarh
• UMC
• TSMC
• Global foundries

• Intel
• Samsung ….etc.

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Modeling digital systems

• Model
– Represents info that is relevant and abstracts away details
– Context dependent
• Reasons for modeling
– Requirements specification
– Documentation
– Testing using simulation
– Formal verification
– Synthesis
– Design reuse
• Goal
– Most reliable design process, with minimum cost and time
– Avoid design errors!

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Domains
• Digital systems modeled in 3 principal domains and
at different levels of abstraction
• Behavioral
– What does it do?
– Truth table, state diagram, waveform, algo
• Structural
– What are the components and how are they connected ?
– Schematic, net list
• Physical
– Where are the components located on Si/PCB ?
– Placement & routing

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Behavioural view
• What the system does
• Info on how this will be achieved is hidden
• Inputs and outputs are defined along with
the relationship between them
• Examples
– Truth table
A
– State diagram B
Y=A+B Y

– Waveform
– Algorithm

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Structural
• What the design is
– What components are used
– How are they interconnected
• No info on what the system does nor how it will be
made
• Example
– Schematic
– Net list
• The components may be defined using behavioral or
structural description
– hierarchical description

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Physical
• How the design is made
• Placement & routing or Manufacturing info
• No info on what components are being made nor on how they
behave
• PCB manufacture
– GERBER files
• Etching tracks, drilling holes
• IC layout
– GDS2 files
• Mask layout: diffusion, metal …
• PLDs
– JEDEC files
• Define internal connections

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Domains and Levels of Modeling

Structural Behavioral

high level of
abstraction

low level of
abstraction

Physical “Y-chart” due to

Gajski & Kahn

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Domains and Levels of

Modeling
Structural Behavioral
Algorithm
(behavioral)

Register-Transfer
Language

Boolean Equation

Differential Equation

Physical “Y-chart” due to

Gajski & Kahn
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Behavioral domain - levels

• Algorithm
– The set of operations to be performed
• Register Transfer Language
– How data will be moved and stored
• Boolean Equations
– How individual signals are manipulated
• Differential equations
– How currents and voltages in the transistors
behave

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Domains and Levels of

Modeling
Structural Behavioral
Processor-Memory
Switch

Register-Transfer

Gate

Transistor

Physical “Y-chart” due to

Gajski & Kahn
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Domains and Levels of

Modeling
Structural Behavioral

Polygons

Sticks

Standard Cells

Floor Plan

Physical “Y-chart” due to

Gajski & Kahn
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Basic Design Flow

• Design Concept Design
Concept

– What is the system

supposed to do? Design Entry

Synthesis and
Optimisation

Simulation

Physical
Design

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Design Entry
• General structure of how system performs desired Design
function Concept

• Methods
– Truth tables
• Text File Design Entry

• Waveform Editor
• Practical only for small designs or subcircuits
– Schematic capture Synthesis and
• Graphical tool Optimisation

• Enables hierarchical design

• Better than truth tables for larger designs, still has
limitations
Simulation
– State Diagrams
– Hardware Description Language
• Designer can use a mix of design entry methods Physical
– Automatically merged Design

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Design entry with HDLs

• Similar to a computer program
• Describes underlying hardware
• Two main HDLs
– VHDL
– Verilog
• Advantages
– Widely supported
– Enables portability
• Underlying implementation can differ without having to change the
design specification
– Text based
• Easy to include in documentation
– Modular implementation possible
• Enables hierarchical implementation of circuits
– Sharing and reuse

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Synthesis and Optimisation

• Translate design entry into intermediate
format, netlist of equations
Design
Concept

– We assume logic function

– Realistically intermediate formats vary depending Design Entry
on tool
• Optimisation Synthesis and
– Manipulating design to produce equivalent, but Optimisation

better circuit
– What makes circuit better?
• Size/area, performance, cost, power etc … Simulation

Physical
Design

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Synthesis
System Description
High level Synthesis

Register Transfer level

Logic Synthesis
Gate level netlist
Layout Synthesis
Physical layout

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Functional Simulation
• Check if the design actually works Design
• Tools Concept

– Questasim, Modelsim, Synopsys VCS

• Method Design Entry
– Designer provides input values
– Functional simulator applies these values to the
equations Synthesis and
– Simulator produces corresponding outputs Optimisation

• Truth table or timing diagram

– Examine output to verify design
Gate Delay
Simulation
•
– Functional simulator assumes zero delay
– Timing simulator accounts for delays related to specific Physical
technology Design

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Physical Design
• Implement intermediate format Design
Concept

into technology dependent format Design Entry

Synthesis and
Optimisation

Simulation

Physical
Design

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Hardware description languages

• Origin
– Very High Speed ICs (VHSIC) program – 1980s
• What’s an HDL?
– Textual description of a circuit
– Model the intended operation of a piece of hardware
– Human and machine readable
– Hierarchical
• NOT A PROGRAM
– Describe what the circuit IS
– Not what is DOES
• Used to describe hardware for the purpose of specification,
modeling, synthesis, verification & documentation

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History - VHDL
• 1980 – VHSIC program (US DoD)
• 1983 – IBM, TI, Intermetrics
– VHSIC HDL (VHDL) Language & simulation tools
• 1987 – IEEE 1076 standard
– F22 aircraft – 1st design
– Lack of tools – deployment slow
• 1993 – Revised IEEE 1076 ’93
• 1996 – commercial tools for simulation & synthesis
– IEEE 1076.3 VHDL for synthesis – portability of design
libraries
– IEEE 1076.4 VITAL modeling of ASIC & FPGA libraries
• VHDL Initiative Towards ASIC Libraries

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Verilog
• 1981 – Gateway design automation
• 1983 – Verilog HDL & simulator
• 1985 – Verilog XL
• 1983-87 – popular for high end designs
• 1987
– Gateway – ASIC foundry endorsement
– Synopsys – synthesis tools
• 1989 – Cadence bought Gateway
• 1990 – public domain
• 1993 – 85% ASIC designers used verilog
• 1995 – IEEE 1364

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Verilog/VHDL
System

Behavioral
System
(Algorithmic)

VHDL
Algorithm V
Functional V H
E D

Verilog
(RTL, RTL R
Boolean) L
I
Logic L
Structural O
VITAL VITAL
(Gate, Switch) Gate G

- Relatively easy to learn - Relatively difficult to learn

- Fixed data types - Abstract data types
- Interpreted constructs - Compiled constructs
- Good gate-level timing - Less good gate-level timing
- Limited design reusability - Good design reusability
- Limited design management - Good design management
- No structure replication - Supports structure replication

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VHDL/Verilog
• Concurrent hardware description
language
– Expresses parallelism in the hardware
• DO NOT code HDL like a C program
– Serializes the hardware operations
– Leads to a BIG increase in the amount of
the hardware

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Concurrent vs sequential
a=6; In C/C++
b=2; a=b=2
c=9; a=b;
b=a;

In HDL
a =2 & b = 6
a=b;
b=a;

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Multiple levels of HDL

U1: xor2 port map(a(0), b(0), x(0)); aeqb <= (a(0) XOR b(0)) NOR
U2: xor2 port map(a(1), b(1), x(1)); (a(1) XOR b(1));
U3: nor2 port map(x(0), x(1), aeqb);

netlist Boolean equations

aeqb <= ‘1’ when a=b else ‘0’; If a=b then aeqb <=‘1’;
else aeqb <= ‘0’;
Concurrent statement end if;

Sequential statement

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Simulation vs. programming

• Simulation tags computations with
times.
– Must know when signals change to
properly simulate hardware.
• Simulation is parallel.
– Many statements can execute at the same
(simulation) time.
– Just like hardware.

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Types of simulation
• Compiled code simulation
– Generate code that evaluates a hardware block
– Operational details/temporal behavior within the
hardware block are lost
– Must evaluate events in the right order
• Event-driven simulation
– Propagate events through simulation.
– Don’t simulate a block until its inputs change

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Event-driven simulation
• An event is a
change in a net’s
value.

net1
• An event has two
components: t=35 ns time
– value; net
– time.
net1=0 @ 35 ns

event
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Events on a gate
• Propagate events
only when nets
change value.
• If an input change 0 1
1 no0
doesn’t cause an 1 0 event
output change, no
event is propagated.

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Timewheel
• The timewheel is a data structure in the
simulator that efficiently determines the
order of events processed.
• Events are placed on the timewheel in
time order.
• Events are taken out of the head of the
timewheel to process them in order.

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Timewheel operation

c=0 @ 2 ns
a c
1
1 0 b=1 @ 1 ns time
0 1
b
a=1 @ 0 ns

netlist timewheel

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Order of evaluation
• Order of evaluation is important.
– Causality must be obeyed.
• Evaluating events in the wrong order
can cause inaccurate results.

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Order of evaluation example

a e=0 @ 3 ns
0 c 1

1 0
0 1 e d=1 @ 2 ns time
b
0 1 b=1 @ 1 ns
d

netlist timewheel

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Synthesis subsets
• VHDL and Verilog were designed for
simulation
• A synthesis subset is:
– synthesizable
– produces consistent simulation results
• Different tools may use different
synthesis subsets

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System level languages

• Common system level language for h/w & s/w
• Abstracting complex system functionality
• Enables h/w-s/w co-design & co-verification
– System C
– System Verilog

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