National University of Technology

Computer Engineering Department

COA lab

Submitted To:
Abdul Qadeer Khan
Submitted By:
Shahid Manzoor | F23604004
Date: 18,june, 2025
Lab report # 02
Objective:

● To get introduction about implementation of Adder circuits.

Software tool:

● XILinx/ VIVADO
Explanation:

In electronics, adder circuit performs addition of the binary numbers.in various computers and
other types of processors. Adder circuits are not only used in ALUs, but also used in various
processors to calculate increment or decrement operations, table indices, addresses, etc. A
typical adder circuit generates sum and carry as the output. The main purpose of these
addresses is used to add the different formats like XS-3, binary coded decimal (BCD) and gray
code. When the or two’s compliment are being used to specify negative numbers, it is small to
alter adder to subtractor. A more complex adder is used to represent other signed numbers.
The applications of adder circuit are, adder circuits are not only used to add binary numbers,
but also used in digital applications such as address, table index, decoding and calculation etc.
Types of Adders Half Adder

The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C).
The carrysignal represents an overflow into the next digit of a multi-digit addition. The value of
the sum in decimal system is 2C + S. The simplest half-adder design, pictured on the right,
incorporates an XOR gate for S and an AND gate for C. The Boolean logic for the sum (in this
case S) will be A'B+AB' whereas for carry (C) will be AB. With the addition of an OR
gate to combine their carry outputs, two half adders can be combined to make a full adder. [1]
The half adder adds two input bits and generates a carry and sum, which are the two outputs of
a half adder. The input variables of a half adder are called the augend and addend bits. The
output variables are the sum and carry.
Full Adder

A full adder is a digital circuit that performs the addition of three one-bit binary numbers,
typically denoted as A, B, and Cin (carry-in). The circuit produces two outputs: Sum (S) and
Carry-out (Cout). Boolean Equations: The full adder can be described using the following
Boolean equations:

Sum (S) = A ⊕ B ⊕ Cin

Carry-out (Cout) = (A ∧ B) ∨ (A ∧ Cin) ∨ (B ∧ Cin)

where represents the XOR operation, represents the AND operation, and represents the
OR operation.⊕ ∧ ∨
Adders Supporting Multiple Bits

Ripple-Carry Adder

It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each full
adder inputs a C in , which is the C out of the previous adder. This kind of adder is called a
ripple-carry adder, since each carry bit "ripples" to the next full adder. Note that the
first (and only the first) full adder may be replaced by a half adder (under the assumption that C
in = 0). The layout of a ripple-carry adder is simple, which allows fast design time; however, the
ripple- carry adder is relatively slow, since each full adder must wait for the carry bit to be
calculated from the previous full adder. The gate delay can easily be calculated by inspection of
the full adder circuit. Each full adder requires three levels of logic. In a 32-bit ripple-carry adder,
there are 32 full adders, so the critical path (worst case) delay is 3 (from input to carry in first
adder) +

31*2 (for carry propagation in latter adders) = 65 gate delays

Carry-Lookahead Adder

To reduce the computation time, engineers devised faster ways to add two binary numbers by
using carry-lookahead adders. They work by creating two signals (P and G) for each bit
position, based on whether a carry is propagated through from a less significant bit position (at
least one input is a 1), generated in that bit position (both inputs are 1), or killed in that bit
position (both inputs are 0). In most cases, P is simply the sum output of a half adder and G is
the carry output of the same adder. After P and G are generated, the carries for every bit
position are created. Some advanced carry-lookahead architectures are the Manchester carry
chain, Brent–Kung adder, and the Kogge–Stone adder. Some other multi-bit adder
architectures break the adder into blocks. It is possible to vary the length of these blocks based
on the propagation delay of the circuits to optimize computation time. These block based
adders include the carry-skip (or carry-bypass) adder which will determine P and G values for
each block rather than each bit, and the carry select adder which pre-generates the sum and
carry values for either possible carry input (0 or 1) to the block, using multiplexers to select the
appropriate result when the carry bit is known. By combining multiple carry-lookahead adders,
even larger adders can be created. This can be used at multiple levels to make even larger
adders. For example, the following adder is a 64-bit adder that uses four 16-bit CLAs with two
levels of LCUs. Other adder designs include the carry-select adder, conditional sum adder,
carry-skip adder, and carry-complete adder.

Carry Select Adder

The carry-select adder generally consists of two ripple carry adders and a multiplexer. Adding
two n-bit numbers with a carry-select adder is done with two adders (therefore two ripple carry
adders), in order to perform the calculation twice, one time with the assumption of the carry-in
being zero and the other assuming it will be one. After the two results are calculated, the correct
sum, as well as the correct carry-out, is then selected with the multiplexer once the correct
carry- in is known. The number of bits in each carry select block can be uniform, or variable. In
the uniform case, the optimal delay occurs for a block size of ⌊ n ⌋. When variable, the block size
should have a delay, from addition inputs A and B to the carry out, equal to that of the
multiplexer chain leading into it, so that the carry out is calculated just in time. The O ( n ) delay
is derived from uniform sizing, where the ideal number of full-adder elements per block is equal
to the square root of the number of bits being added, since that will yield an equal number of
MUX delays.
Lab Tasks:

Task 1:

CODE
WORKBENCH:

TASK 2:
CONCLUSION:

In conclusion, the Verilog code for a 4-bit adder using half and full adders was
successfully implemented and simulated. The testbench results verified the correctness
of the design, demonstrating the expected behavior for various input combinations.