EC2.

101 – Digital Systems and Microcontrollers

Lecture 12 – Sequential
circuits 2
Dr. Aftab M. Hussain,
Assistant Professor, PATRIoT Lab, CVEST

Chapter 5

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Flip flops
• Enter: the Flip flop!
• Flip-flops are constructed in such a way as to make them operate properly when
they are part of a sequential circuit that employs a common clock
• The problem with the latch is that it responds to a change in the level of a clock
pulse
• A positive level response in the enable input allows changes in the output when
the D input changes while the clock pulse stays at logic 1
• The key to the proper operation of a flip-flop is to trigger it only during a signal
transition
• A clock pulse goes through two transitions: from 0 to 1 and the return from 1 to 0
• The positive transition (0->1) is defined as the positive edge and the negative
transition (1->0) as the negative edge
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Flip flops
• The first latch is called the master
and the second the slave
• The circuit samples the D input and
changes its output Q only at the
negative edge of the synchronizing
or controlling clock (designated as
Clk)
• When the Clk = 0, the slave latch is
enabled, and its output Q is equal to
the master output Y
• When the input pulse changes, the
data from the external D input are
transferred to the master

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Flip flops
• The slave, however, is disabled as long
as the clock remains at the 1 level,
because its enable input is equal to 0
• Any change in the input changes the
master output at Y, but cannot affect
the slave output
• When the clock pulse returns to 0, the
master is disabled and is isolated from
the D input
• At the same time, the slave is enabled
and the value of Y is transferred to the
output of the flip-flop at Q
• Thus, a change in the output of the
flip-flop can be triggered only by and
during the transition of the clock from
1 to 0
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Setup and Hold
• This the most important concept for you to get placed in VLSI companies!
• Here is the problem: we discussed a latch can be converted into edge triggered
using the master-slave configuration
• However, when the clock edge arrives, the master flip flop should have settled on
to the steady output
• The time for which the data should be stable before the clock edge is called setup
time
• In some cases, it is important to keep the data stable for a certain time after the
clock edge has gone to make sure all the combinational/sequential circuit outputs
are stable
• The time for which the data should be stable after the clock edge is called hold
time
• The propagation delay time of the flip-flop is defined as the interval between the
trigger edge and the stabilization of the output to a new state

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Graphical symbols

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JK Flip Flop
• There are four operations we are looking
to perform in a flip-flop: Set it to 1, reset it
to 0, retain or complement its output
• With only a single input, the D flip-flop can
set or reset the output, depending on the
value of the D input immediately before
the clock transition
• Synchronized by a clock signal, the JK flip-
flop has two inputs and performs all four
operations
• The J input sets the flip-flop to 1, the K
input resets it to 0, and when both inputs
are enabled, the output is complemented
• This can be obtained if the D input is:
𝐷 = 𝐽𝑄′ + 𝐾𝑄

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JK Flip Flop
𝐷 = 𝐽𝑄′ + 𝐾′𝑄
• When J = 1 and K = 0, D = Q’ + Q = 1, so
the next clock edge sets the output to 1
• When J = 0 and K = 1, D = 0, so the next
clock edge resets the output to 0
• When both J = K = 1 and D = Q’, the
next clock edge complements the
output
• When both J = K = 0 and D = Q, the
clock edge leaves the output
unchanged
• Because of their versatility, JK flip-flops
are called universal flip-flops

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T Flip Flop
• The T (toggle) flip-flop is a
complementing flip-flop and can be
obtained from a JK flip-flop when
inputs J and K are tied together
• When T = 0 (J = K = 0), a clock edge
does not change the output
• When T = 1 (J = K = 1), a clock edge
complements the output
• The complementing flip-flop is
useful for designing binary counters

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T Flip Flop
• The T flip-flop can also be
constructed using a D flip-flop
• The expression for the D input is:
𝐷 = 𝑇 ′ 𝑄 + 𝑇𝑄 ′
• When T = 0, D = Q and there is no
change in the output
• When T = 1, D = Q’ and the output
complements
• The graphic symbol for this flip-flop
has a T symbol in the input

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Asynchronous inputs
• Some flip-flops have asynchronous inputs
that are used to force the flip-flop to a
particular state independently of the clock
• The input that sets the flip-flop to 1 is
called preset or direct set
• The input that clears the flip-flop to 0 is
called clear or direct reset
• When power is turned on in a digital
system, the state of the flip-flops is
unknown
• The direct inputs are useful for bringing all
flip-flops in the system to a known starting
state prior to the clocked operation.
• When the reset input is 0, it forces output
Q’ to stay at 1, which, in turn, clears output
Q to 0, thus resetting the flip-flop

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Analysis
• Analysis describes what a given circuit will do under certain operating
conditions
• The behavior of a clocked sequential circuit is determined from the inputs,
the outputs, and the state of its flip-flops
• The outputs and the next state are both a function of the inputs and the
present state
• The analysis of a sequential circuit consists of obtaining a table or a diagram
for the time sequence of inputs, outputs, and internal states
• It is also possible to write Boolean expressions that describe the behavior of
the sequential circuit
• These expressions must include the necessary time sequence, either directly
or indirectly

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Analysis
• Consider this sequential circuit
• It consists of two D flip-flops A and
B, an input x and an output y
• Since the D input of a flip-flop
determines the value of the next
state (i.e., the state reached after
the clock transition), it is possible to
write a set of state equations for the
circuit as:
𝐴(𝑡 + 1) = 𝐴(𝑡)𝑥(𝑡) + 𝐵(𝑡)𝑥(𝑡)
𝐵(𝑡 + 1) = 𝐴’(𝑡)𝑥(𝑡)

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State equations
• A state equation is an algebraic expression
that specifies the condition for a flip-flop
state transition
• The left side of the equation, with (t + 1),
denotes the next state of the flip-flop one
clock edge later
• The right side of the equation is a Boolean
expression that specifies the present state
and input conditions
• Since all the variables in the Boolean
expressions are a function of the present
state, we can omit the designation ( t )
after each variable for convenience and
can express the state equations in the
more compact form
𝐴 𝑡 + 1 = 𝐴𝑥 + 𝐵𝑥
𝐵 𝑡 + 1 = 𝐴′𝑥

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State equations
• The Boolean expressions for the state
equations can be derived directly from
the gates that form the combinational
circuit part of the sequential circuit,
since the D values of the combinational
circuit determine the next state
• Similarly, the present-state value of the
output can be expressed algebraically
as
𝑦(𝑡) = [𝐴(𝑡) + 𝐵(𝑡)]𝑥′(𝑡)
• By removing the symbol (t) for the
present state, we obtain the output
Boolean equation:
𝑦 = (𝐴 + 𝐵)𝑥′

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State tables
• Similar to truth tables, the derivation of
a state table requires listing all possible
binary combinations of present states
and inputs
• In this case, we have eight binary
combinations from 000 to 111
• The next-state values are then
determined from the logic diagram or
from the state equations
• The next state of flip-flops must satisfy
the state equations:
𝐴 𝑡 + 1 = 𝐴𝑥 + 𝐵𝑥
𝐵 𝑡 + 1 = 𝐴′𝑥
Output is derived from:
𝑦 = (𝐴 + 𝐵)𝑥′

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State tables
• In general, a sequential circuit with m
flipflops and n inputs needs 2m+n rows in
the state table
• The binary numbers from 0 through 2m+n -
1 are listed under the present-state and
input columns
• The next-state section has m columns, one
for each flip-flop
• The binary values for the next state are
derived directly from the state equations
• The output section has as many columns
as there are output variables
• Its binary value is derived from the circuit
or from the Boolean function in the same
manner as in a truth table
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State tables
• It is sometimes convenient to express the
state table in a slightly different form
having only three sections: present state,
next state, and output
• The input conditions are enumerated
under the next-state and output sections

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State diagram
• The information available in a state
table can be represented graphically in
the form of a state diagram
• In this type of diagram, a state is
represented by a circle, and the (clock-
triggered) transitions between states
are indicated by directed lines
connecting the circles
• The binary number inside each circle
identifies the state of the flip-flops
• The directed lines are labeled with two
binary numbers separated by a slash
• The input value during the present
state is labeled first, and the number
after the slash gives the output during
the present state with the given input
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State diagram
• For example, the directed line from
state 00 to 01 is labeled 1/0, meaning
that when the sequential circuit is in
the present state 00 and the input is 1,
the output is 0
• After the next clock cycle, the circuit
goes to the next state, 01
• If the input changes to 0, then the
output becomes 1, but if the input
remains at 1, the output stays at 0
• This information is obtained from the
state diagram along the two directed
lines emanating from the circle with
state 01
• A directed line connecting a circle with
itself indicates that no change of state
occurs
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