1.

Enumerations in system Verilog are a user-defined data type that consist

of a set of named values called enumerators.
Uses:- they improve
1) Code readability
2) Type safety
3) Debugging, by allowing you to represent symbolic
names instead of raw integers
Syntax:- typedef enum{RED,GREEN,BLUE} colot_t;
Example:-
module enum_example;
typedef enum{RED,YELLOW,GREEN} traffic_light;
Traffic_light_t light;
Initial begin
Light =RED;
$display(“current light: %s”,light.name());
Light=GREEN;
$display(“current light: %s”,light.name());
Case (light)
RED: $display(“stop!”);
YELLOW:$display(“get ready!”);
GREEN:$display(“GO!”);
end case
end
end module

2.Assigning default or overriding implicit values in enums-system Verilog:-

By default,system Verilog assigns incremental integer values starting
from 0 to enum members.however,you can override these values by
assigning explicit constants.
 1) Overriding implicit enum values:- you can assign integer values to
any or all enum members unassigned members will increment from
the last explicity assigned values.
2) Partial overrides with implicit increment:- you can mix explicit and
implicit values.
3) Assigning a default enym variable value:-in system Verilog,enum
variables can be assigned a default value in the declaration or within
an intial block.
Example:-
Module enum_override_example;
Typedef enum{
RED =3,
GREEN
BLUE=10,
YELLOW
}colot_t;
Color_t light=RED;
Initial begin
$display(“initial color:%s=%0d”,light.name(),light);
Light=YELLOW;
$display(“updated color:%s=%0d”,light.name(),light);
end
end module

3.using enumes in a case statement in system verilog is cleaner,safer and

more readable than using palin constants.When you use enums,the
simulator/compiler can :-

• Check for missing case

• Show symbolic names in debugging
• And prevent invalid assignments at compile time
Benefits of enums in case vs constants:

Features Enums Constants

Readability IDLE,START,DONE 0,1,2
Compiler safety Type checking Easy to mix wrong
enforced values
Debugging/simulation Shows symbolic Shows just numbers
names
Code maintance Easy to update Requires tracking
manual values
Example:-
Module fsm_enum_case;
Typedef enum logic[1:0] {
IDLE=2’b00;
START=2’b01;
Process=2’b10;
Done=2’b11;
}state_t;
State_t state;
Initial begin
State=START;
Case(state)
IDLE: $display(“state is IDLE”);
START: $display(“state is START”);
PROCESS: $display(“state is PROCESS”);
DONE: $display(“state is DONE”);
Default:($diaplay(“unknown state”);
end case
end
end module

4.yes,enumes can absolutely be used with arrays and queues in system

Verilog and doing so provides clarity,type safety,and easy indexing using
meaningful names instead of raw integers
Enum as index in array:-
 Module enum_array_tb;
Typedef enum logic [1:0] {RED=0,GREEN=1,BLUE=2.
YELLOW=3} color_t;
Int color_values [color_t];
Initial begin
Color_values[RED]=10;
Color_values[GREEN]=20;
Color_values[BLUE]=30;
Color_values[YELLOW]=40;
For each(color_values[color])
$display(“color:%s,value:%0d”,color.nane(),color_values[color]):
end
end module
enum elements in a queue:-
Module enum_queue_tb;
Typedef enum{IDLE,START,PROCESS,DONE} state_t;
State_t state_queue[$];
Initial begin
State_queue.Push_back(IDLE);
State_queue.push_back(START);
State_queue.push_back(process);
For each (state_queue[i])
$display(“queue[% 0d]:%s”,I,state_queue[i] name());
$display(“popped %s”,state_queue.pop_front ().name())
end
end module
5.In system verilog,you can iterate over an enum using the built in first
(),last(),next(),and prev()methods.These methods are automatically
available to all typedef enum types and make looping over enum values
easy and readable

Method Description
First() Returns the first enum value
Last() Returns the last enum value
 Next(val) Returns the next enum value after
val
Prev(val) Returns the previous enum value
before val
Val.name() Returns the string name of the
enum value

Ex:
Module enum-iteration-tb;
Typedef enum{IDLE,START,PROCESS,DONE}
Statue-t;
State-t state;
Intial begin
&display(“Iterating through enum values:);
For(state=state first();state<= state.last();state=state next())begin
&display (“state:%s(value=yDd)”,
State.name(),state);
End
End
Endmodule
6.yes,enums can be used in class-based test benches-with constraints in
system Verilog-and they are commonly used in randomized stimulus
generation
It improves,code redability
Controlled randomization
Constrained stimulus generation
Ex:module enum-class-tb;
Packet pkt;
Intial begin
Pkt=new();
Repeat(5)begin
If(pkt.randomize())
Pkt.display();
Else
$display(“Randonization failed”);
End end endmodule
7.A structure in system Verilog is a composite data type groups together
variables of different types under one name it is similar to c/c++ structures
and is often used to represented related data fileds as a single unit
Ex:a packet,transaction ,or register

Feature struct class union

Memory Static(stack) Dynamic(heap using static(all
alloation new) fields
share
space)
Object- No inheritance or Inheritance,polymorp Inheritanc
oriented methods hism e
encapsola limited Full oop features None
tion
randomiza supported Fully supported with Limited
tion constraints (only one
active
field)
Use lose Register modeling Test Static(all
packets benches,sequences fields
Ex:typedefstruct{bit[3:0 agents share
]oplode; Ex:class space)
Bit[7:0]operand;} transition;randbit[3:0] Inheritanc
Instr-t; oplode; e
Instr-t inst Randbit[7:0]operand; None
End class Limited(on
Transitiont=new(); ly one
active
field)
Overlay
different
 interpretat
ions
Ex.typedef
union[
Bit[15:0]w
ord;
Struct{
Bit[7:0]low
Bit[7:0]hig
h
}bytes;
}data-u;
Data-ud;

8.system verify supports passing structs to modules functions and tasks to

grap and transfer related data efficiency and cleanly
Ex:struct passed by value to a task:
Typedef struct{
Bit[7:0]addr;
Bit[7:0]data;
Bit write;
}packe-t;
Task send-packet(packet-t pkt);
Passed by value
$display(“address=%h,Data =%h,write =%b”,pkt.addr,pkt.data,pkt.write);
Module test-struct-task;
Packet-tp;
Intial begin
P={addr:8′ Hao,data:8′h55,write:1};
Send-packet(p);
Struct
End
Endmodule

9.Yes,in system Verilog structs can be either packed or unpacked,and this

distriction has important synthesis simulation and memory layout
implications
Packed struct:-A packed struct is stored as a contiguous set of bits(like a
bit vector),with a defined bit order.its typically used for:-

• bit level operations

• interfacing with hardware
• serialization
unpacked struct:- an unpacked struct stores its field separately (not as
continuous bit field),similar to how c structs are stored in memory
Ex- module struct-example;
typedef struct packed {
logic. [3.0] oplode,
logic (110) operand;
Sparked. Inster-t;
typedef struct &
logic (3:0] oplodes
logic 17:01 operand,
}unpacked_instr_t
packed-instr-t p-Post;
unpacked inety-tu-last;
initial begin
P_inst = 12’b1000-10101010,
$display ("packed opcode='%b, operand = %b", p_inst.opcode,
P-Inst.operand);
u_inst opcode-4'b0011;
 U-inst.operand-8'b11110000,
end
end module

10. system verilog allows structs to be elements of arrays and queues,

which is very useful for organizing and managing Complex data like
transactions, packets, il reguler sets
using struct to Array:-
typedef struct {
bit [7:0] addr;
bit [7:0] data;
bit write;
}packet-t
module Struct-array-tb;
packet_t pkt_array [3];
Initial, begin
PKt_ array[0] = {axir: 8h10, data: 8'hAA, write: 1};
Pkt_array[1]= '{addr: 8'h20 data: 8'hBB, write: 0};
Pkt-array[2]= {addr: 8'h30 data: 8'hcc, write: 1};
foreach (PKt array[i] begin;
$display ("packet [%0d] Addr: %h, data=%h, write=%b", i, pkt_ array[1].
Addr ,pkt_array[i].data,pkt_array[i].write);
end
end
end module.
11. yes, structs can be randomized in System verilog – either directly if
declared as r and inside a typedef struck or indirectly, by embedding a
struct inside a class and randomizing the class.
Ex- Randomizable struct with constraints
typedef struck {
rand bit [3:0]opcode;
rand bit [7:0] operand;
}instr_t;
Class instrgen;
instr-t i;
Constraint Valid_inster {i.opcode inside {4'h1, 4'h2, 4’hA};
i.operard > = 8'h10 && i.operand <= 8'hf0;}
function Void display();
$display (“opcode =%h, operand = %h", i. opcode, i.operand);
end
end class
module struct-random_tb;
Instrgen gen;
Intial begin
gen = new();
repeat (5) begin
if (gen, randomize())
gen. display();
else
$display ("randomization failed").
 end
end
end module

12. in system Verilog, structs can be used inside covergroups to group

related fields and simplify the Coverage model. However, since Covergroup
fields must be individual expressions or Variables, you cannot directly
sample the entire struck in a single coverpoint, instead you can acces
Individual fields of the struct within the covergroup.
Ex:- using structs in covergroups
typedef struct {
bit [3:0] opcode;
bit [7:0] operand;
bit enable;
}instr_t;
Class my-env;
Instr_t instr;
Covergroup cg_instr @(posedge clK);
Coverpoint instr.opcode;
Coverpoint instr.operand,
Coverpoint instr. enable,
Cross instr.opcode
instr. enable;
end group
function new();
cg-instr-new;
 end fuction
end class

13. Assign values to a Struct efficiently:-

in system, verilog, assigning values to a struct can be done efficiently in
several ways, depending on your use case.
1. Aggregate Assignment : You cam assign all fields in one line using struct
literals
typedef struct {
bit [3.0] opcode;
bit [7:0] operand;
bit enable
}instr_t;
Instr_t my instr;
my-instr = '{opcode: 4’b1010, operand: 8’hff, enable: 1’b1};
2. Field -by- freld assignment:- if you need to assign fields separately (e.g:-
when values come from different sources)
My_instr. Opcode= 4'boo11;
My_instr. operand = 8'hA5;
My_instr.enable = 1'bo;
3. Copying from Another Stuck (Same type):- Fast and clean when
duplicating values from another struct instance
Instr_t instr1, instr2;
instr1 = '{opcode: 4'b1oo1, operand: 8'hC3, enable: 1’b1};
instr2 = instr1;
4.constructor-like assignment in classes:-(If struct is a class property):-for
class-based testbenches,you can assign values in the constructor.
class env;
instr_t instr;
function new ();
instr = '{ opcode; 4'b0001, operand: 8’h10, enable: i'b1);
endfunction
endclas

14. Different types of Arrays in System verilog and Their usage:-

system verilog supports four main types of arrays, each designed for
different sienarios in modeling and verification.
1.Fixed size Arrays (Static arrays):-
size is defined at compile-time and connot change
Syntax:-bit [7:0] data_array [0:15];
2. Dynamic arrays:-
size can be changed at run time using Dew [].
Syntax:- int dyn_array [];
dyn_array =new[10];
dyn_array [0] = 5;
3. Associativa Array:- indexed using arbitary data types (e.g., integers
Strings)
Syntax:- int assoc_ array [String];
Assoc_array [“addr 1"] = 10;
4. Queues:- Variable-size ordered collections (FIF0-like behaviour)
Systax:- int q[$];
 queue
q.push-back (102
end
q.push-front (5),
front
int x= q.pop-front ();
front

15. manipulate dynamic arrays in System Verilog:-

Dynamic arrays in system verilog and resizable one-dimensional arrays is
determined at runtime. They are powerful for modeling testbenches and
variable site data.
Ex:- module th;
int dyn_array[];
initial begin
dyn array =new [4];
for each (dya array[i])
dyn array [i] = 1*2;
$display ("size = %0d", dyn_array.site());
Dyn_array = new [6]
(dyn-array):-

dyn _array[4]=99;
dyn_array [5]= 100;
for each (dyn_array(i)).
$display ("dyn _array [%0d] = %0d, i, dyn_array [i]);
 dyn-array = null;
end
endmodule.

16.Associativa array:-an associativa array in system verileg is an

unbounded, sparse array where The index can be any scalar data type - not
just integers, instead of using Continuous indices, like [0], [1], [2], you can
use custom keys, like strings or enumerations.
Syntax;- int my_array [String];
my- array ["addr1”]=10;
my array ["addr2"]= 20;

Features Associative Dynamic Fixed array queue

array array
Index type Any scalar Integer only Integer Integer(ordered)
lint,string only
Size enum Dynamic Fixed at Dynamic,ordered
dynamic and compile-
and sparse contiguous time
Memory- Yes No yes yes
efficient
Useful for yes no No No
maps/keys

17. operations on queues in System Verilog:-

in system Verilog, a queue is a variable - size; ordered collection of
elements similar to a dynamic array, but with powerful insertion and
deletion capabilities

operation Syntan examples

insert at end q.push-back (10);
insert at front q.push _front (5);
Remove from front int x=q.pop_front();
 Remove from back Int y=pop_back();
Access by index q[2]=42;
delete by index q.delete(l);
Get size q.size()
empty the queve 9={}; or q.delete();
iterate elemente For each (q[i])

Example:-
module tb;
int q[$];
initial begin
q.push-bark (10);
9 push-front(5);
$display ("queue size: %od", q.size());
$display (“First clement: %o0d", q[0];
int val = q.pop-front ();
$display ("popped: %0d", val);
q. push-back (20);
q.push-back (30);
q. delete (1);
element:-
foreach (q[i])
$display ("q[%0d] - %0d", q[0]);
q. deletel ();
end
end module
18. system verilog provides several powerful and flexible ways to iterate
through arrays, depending on the type of array (fixed, dynamic, associative,
queue)
1.using for each loop-most recommended:- works with any array type and
is clean and readable
Syntax:- for each (array_name [index])begin
2 . Traditional for loop:- best when you need full control over the index or
iterate in reverse
Syntax-
for (int i=0; i<arr. Size(); i++)
begin
$display ('arr [%0d] ", arr[i]);
End
3. iterating Associative arrays:- associative arrays require the use of for
each, since they are not indexed numerically
Syntax:-
Int assoc_arr[string];
Assoc_arr[“a”] = 10;
Assoc_arr[“b”]=20;
For each (assoc_arr[key])
$display ("Key :%s, Value :%0d”, Key, assoc_ r [key]);

4. Reverse iteration:- for queues or arrays you want to access in reverse...

Syntax:-
For (int i= arr. Size( ) -1; i>=0; i--)
Begin
$display ("Reverse arr[%od]=%0d", i, arr[i]);
End

19. Yes, array can be passed to tasks, functions or modules passing fixed
size arrays you must declare the exact size in the function/task signature p
Function int sum _array (input int a[4]);
int sum =0;
foreach (a[i])
Sum += a[i];
Return sum;
endfunction
passing Dynamic arrays:- you can pass by reference or handle, especially if
the size isn’t known in advance
System Verilog:-
task print_dyn arway (input int da[]);
for each (da[i])
$display ("da [%0d] = %0d", i, da[i]);
end task
passing associative array:-pass by reference only
task print _assoc _array (ref int aa [string]);
foreach (aa (key)
$display ("key:%s, Value: %0d”, Key, aa[key]) ;
end task
passing to modules:-only fixed -size arrays can be passed as ports
module m(input logic. [7:0]
data_bus [4]);
end module

20. Arrays can be very useful in both functional coverage and

randomization with constraints.
1) Assays in coverage:-you can write a coverpoint on individual array
elements.
Syntax:-
int arr[4];
Covergroup of @(posedge CIK);
Coverpoint arr[0];
Coverpoint arr[1];"
Cross arr[0], arr[1];
Endgroup
2)Arrays in constraints:- you can randomize arrays inside a class:-
Syntax:-
class my_class;
rand bit [7:0] arr [4]:
constraint range _c { for each
(arr[i]) arr[i] inside {[10:100]};}
end class