JSS MAHAVIDYAPEETHA

JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA

MICROPROCESSOR & MICROCONTROLLER

(8085, 8086 & 8051)
KEC-502
V SEMESTER
Electronics & Communication Engineering
UNIT-3
16-bit Microprocessor and Peripheral
devices
As per the syllabus of
Dr. A.P.J. Abdul Kalam Technical University, UTTAR PRADESH

JSS Academy of Technical Education,

NOIDA.

Dr. ARUN KUMAR. G

Professor & HOD, Dept. of ECE
Mr. GANESHA H S
Assistant Professor, Dept. of ECE
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

UNIT
16-bit Microprocessor and
Peripheral devices
SYLLABUS
16-bit Microprocessors (8086): Architecture, Pin Description, Physical address, Segmentation,
Addressing modes.
Peripheral Devices: 8237 DMA Controller, 8255 Programmable Peripheral Interface,
8253/8254 Programmable Timer/Counter, 8259 Programmable Interrupt Controller, 8251
USART and RS 232C.
16-BIT MICROPROCESSOR
3.1 Introduction to 16-bit Microprocessor 8086

• The 8086 microprocessor is an 8-bit/16-bit microprocessor designed by Intel in the late

1970s.
• The architecture of the 8086 microprocessor is based on a complex instruction set
computer (CISC) architecture, which means that it supports a wide range of instructions,
many of which can perform multiple operations in a single instruction.

3.1.1 8086 Internal Architecture:

Draw the architecture of 8086 Microprocessors and explain its all blocks.
AKTU Question Paper 2022-23, 10 MARKS

Figure 3.1: 8086 Microprocessor Internal Architecture

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
Figure 3.1 shows the 8086 Microprocessor internal architecture.
The 8086 microprocessor has two main execution units:
i. The Bus Interface Unit (BIU) and
ii. The Execution Unit (EU).
The BIU is responsible for fetching instructions from memory and decoding them, while the
EU executes the instructions. The BIU also manages data transfer between the
microprocessor and memory or I/O devices.

1. The Bus Interface Unit (BIU):

BIU performs the following functions:
• It generates the 20-bit physical address for memory access.
• It fetches instructions from the memory.
• It transfers data to and from the memory and I/O.
• Maintains the 6-byte pre-fetch instruction queue (supports pipelining).
BIU mainly contains the 4 Segment registers, the Instruction Pointer, Instruction Queue, and an
Address Generation Circuit.
Memory Segmentation
Memory segmentation is the method where whole memory is divided into the smaller parts called
segments, and each segment can be up to 64 KB (kilobytes) in size. This segmentation allows the
processor to access a total of 1 MB (megabyte) of memory.
• DATA SEGMENT
• CODE SEGMENT
• STACK SEGMENT and
• EXTRA SEGMENT.
Each segment can be up to 64 KB (kilobytes) in size. Segment registers store starting address of
each segments in memory.

Maximum size of segment:

• All offsets are limited to 16-bits. It means that the maximum size possible for segment is
216= 65,535 bytes (64 KB).
• The offset of the first location within the segment is 0000 H. The offset of the last location
in the segment is FFFF H i.e. the address within each segment is ranging between 0000 H
to FFFF H (64 KB).

Segment Registers:
The 8086 has four primary segment registers: CS (Code Segment), DS (Data Segment), SS (Stack
Segment), and ES (Extra Segment). Each of these registers holds a 16-bit value that represents
the base address of a specific segment in memory.
Code Segment (CS) register : CS is a 16 Bit register, holds the base address for the Code
(64 KB) Segment. All programs are stored in the Code Segment and
accessed via the IP.
Data Segment (DS) register : DS is a 16 Bit register, holds the base address for the Data
(64 KB) Segment.
Stack Segment register : SS is a 16 Bit register, holds the base address for the Stack
(64 KB) Segment.

Extra Segment register : ES is a 16 Bit register, holds the base address for the Extra
(64 KB) Segment.

Instruction Pointer (IP):

• It is a 16-bit special-purpose register.
• It points to the memory location of the next instruction to be executed.
• It is automatically incremented after each instruction fetch.
• IP gets a new value whenever a branch instruction occurs.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
• The code segment (CS) is multiplied by 10H to give the 20-bit physical address of the Code
Segment.
• The address of the next instruction is calculated by using the formula CS x 10H + IP.

Investigate the need of pre-fetch instruction queue in 8086.

AKTU Question Paper 2021-22, 2 MARKS
Instruction Queue:
• It is a 6-byte queue (FIFO).
• Fetching the next instruction (by BIU from CS) while executing the current instruction is
called pipelining.
• Gets flushed whenever a branch instruction occurs.
• The pre-Fetch queue is of 6-Bytes only because the maximum size of instruction that can
have in 8086 is 6 bytes. Hence to cover up all operands and data fields of maximum size
instruction in 8086 Microprocessor there is a Pre-Fetch queue is 6 Bytes.

Address Generation Circuit:

• The BIU has a Physical Address Generation Circuit. It generates the 20-bit physical address
using Segment and Offset addresses using the formula:
• In Bus Interface Unit (BIU) the circuit shown by the symbol ‘Σ’ is responsible for the calculation
unit which is used to calculate the physical address of an instruction in memory.
Physical Address = (Segment Address x 10H) + Offset Address

Address Bus:
The 8086 microprocessor has a 20-bit address bus, which can address up to 1 MB of memory (220
= 1,048,576), and a 16-bit data bus, which can transfer 16-bit data between the microprocessor
and memory or I/O devices.

Data Bus:
The data bus is used to transfer data between the microprocessor and memory. The data bus is
16 bits wide, allowing the 8086 to transfer 16-bit data words at a time.

Control Bus: The control bus is used to transfer control signals between the microprocessor and
other components in the computer system. The control bus is used to send signals such as read,
write, and interrupt requests, and to transfer status information between the microprocessor and
other components.

The Execution Unit (EU):

The main components of the EU are General purpose registers, the ALU, Special purpose registers,
the Instruction Register and Instruction Decoder, and the Flag/Status Register.

The functional parts of EU are explained as below.

Arithmetic Logic Unit (ALU): The ALU is responsible for performing 8-bit and 16-bit arithmetic
and logical operations on data. It can handle operations such as addition, subtraction,
multiplication, division, bitwise AND, OR, XOR, and more.

General-Purpose Registers:
8086 has four 16-bit general purpose registers AX, BX, CX, and DX which store intermediate
values during execution. Each of these has two 8-bit parts (higher and lower) i.e. AH, AL, BH, BL,
CH, CL, DH and DL to store 8-bit data.

AX register: (Combination of AL and AH Registers)

It holds operands and results during multiplication and division operations. Also, an accumulator
during String operations.
BX register: (Combination of BL and BH Registers)
It holds the memory address (offset address) in indirect addressing modes.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
CX register: (Combination of CL and CH Registers)
It holds the count for instructions like a loop, rotates, shifts and string operations.
DX register: (Combination of DL and DH Registers)
It is used with AX to hold 32-bit values during multiplication and division

Index and Pointer registers:

• EU has two 16-bit index register and two 16-bit pointer registers designated as SI (Source
Index Register), DI (Destination Index Register), SP (Stack Pointer Register) and BP (Base
Pointer Register).
• SI is often used as an offset or index when accessing source data during string operations.
• DI serves as an offset or index for destination data during string operations.
• The SP register points to the top of the stack in memory. It's crucial for managing the stack,
including push and pop operations.
• BP serves as a base pointer in stack frame operations and is often used for accessing
parameters and local variables within functions.

Control Unit:
The Control Unit in the 8086 microprocessor is a component that manages the overall operation
of the microprocessor. It interprets the opcode of an instruction, determines the operation to be
performed, and generates control signals to execute that operation.

Instruction Decode:
• The EU decodes the instruction fetched from memory to understand what operation needs to
be performed and which operands to use.
• It works in parallel with the Prefetch Unit, which fetches instructions from memory and stores
them in a queue.

Flag Register:
The 8086 flag register contents indicate the results of computation in the ALU. It also contains
some flag bits to control the CPU operations.
It consists of 9 active flags out of 16. The remaining 7 flags marked ‘X’ are undefined flags.
These 9 flags are of two types:
• Conditional flags (6) and
• Control flags (3)

Figure 3.2: 8086 Flag register format

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
The conditional flags are:
Carry Flag (CF) : CF=1; Whenever there is a carry or borrow out of the MSB (most
significant bit) of a result
CF=0; Otherwise.

Parity Flag (PF) : PF=1; If the number of 1’s in the result are even.
PF=0; If the number of 1’s in the result are odd.

Auxiliary Carry : AF=1; If a carry is generated out of the lower nibble (out of D3 bit)
Flag (AF) AF=0; Otherwise.

Zero Flag (ZF) : ZF=1; If the result of an operation is zero.

ZF=0; Otherwise.

Sign Flag (SF) : SF=1; if the MSB of the result is 1. For signed operations such a
number is treated as negative.
SF=0; Otherwise.

Overflow Flag (OF) : It is used to detect signed arithmetic overflow in operations.

OF=1; If the result of a signed operation is too large to fit in the
number of bits available to represent it.
OF=0; Otherwise.
The Control flags are:

Trap Flag (TF) : TF=1; the execution will be done step by step where it executes one
instruction at a time i.e. start single stepping mode. This is useful for
debugging.
TF=0; Otherwise (the free-running operation will be done).

Interrupt Flag (IF) : IF=1; interrupts are enabled and can be serviced by the CPU.
IF=0; interrupts are disabled.

Direction Flag (DF) : This flag is used for string operations.

DF=1; SI and DI are in auto-decrementing mode in string operations.
DF=0; SI and DI are in auto-incrementing mode in string operations.

Features of 8086 microprocessor:

• 16-bit architecture.
• Segmented memory model.
• 16-bit registers for data and addressing.
• Rich instruction set.
• Operated at a clock frequency of 5 MHz
• Versatile memory addressing modes.
• Multitasking potential due to segmentation.
• Up to 1 MB addressable memory.
• 16-bit data bus, 20-bit address bus.
• Eight general-purpose registers.

3.1.2. Pin Description of 8086 Microprocessor

An 8086 microprocessor is also a 40 pin IC but has few separate pin configurations for minimum
and maximum mode.
The 8086 microprocessor operates in 2 modes that are
• Minimum mode and
• Maximum mode.
The minimum mode is a single processor configuration while the maximum mode is a multiple
processor configuration.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
The figure below represents the pin diagram of 8086 microprocessor:

Figure 3.3: 8086 microprocessor Pin diagram

From figure 3.3, it is clear that from pin number 24 to 32, we have shown the different
configuration for minimum and maximum mode. Excluding these 8 pins, the rest 32 pins are the
same for both minimum as well as maximum mode.

The pin description of 8086 Microprocessor

Pin
Pin Name Description
No.
1& These two pins acts as the ground.
VSS
20
These are the multiplexed address and data bus.
2 to AD0 – The 8086 microprocessor has 20-bit address bus and 16-bit data bus.
16 AD14 and So, the 16 lines of the address and data bus are multiplexed together
& 39 AD15 At a particular time only either the address or the data bus will be
enabled from the multiplexed buses.
NMI is Non-maskable interrupt. These interrupts are generated inside
the processor. When an NMI occurs, then an interrupt service routine
17 NMI
is generated by the interrupt vector table.

INTR stands for an interrupt request.

The INTR pin in the 8086 microprocessor is used to allow external
18 INTR
hardware devices to request the CPU's attention for processing
specific tasks or data. When a device sends an interrupt request to the

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
INTR pin, the CPU acknowledges it, pauses its current operation, and
processes the interrupt. This enables efficient communication
between the CPU and external devices.
It provides timing to the microprocessor for operations. Its frequency
19 CLK is different for different versions, i.e. 5MHz, 8MHz and 10MHz.
̅̅̅̅̅̅̅̅̅ pin is used to reset the microprocessor, returning it to its
The 𝐑𝐄𝐒𝐄𝐓
̅̅̅̅̅̅̅̅̅ initial or default state. When a low-level signal (logic 0) is applied to
21 𝐑𝐄𝐒𝐄𝐓
the ̅̅̅̅̅̅̅̅̅
𝐑𝐄𝐒𝐄𝐓 pin, it forces the 8086 CPU to restart its operation from the
beginning, clearing all registers.
READY signal is used by the peripherals and memory devices in order
to show the readiness for the next operation.
22 READY It is an active high signal. When it is high, it indicates that the device is
ready to transfer data. When it is low, it indicates wait state.

̅̅̅̅̅̅̅ pin is Low, execution continues otherwise the processor

If the 𝐓𝐄𝐒𝐓
23 ̅̅̅̅̅̅̅
𝐓𝐄𝐒𝐓
waits in an "idle" state.
QS0 and QS1: These two pins indicate the status of the 6-byte pre-fetch
queue present in the architecture of 8086.
QS0 QS1 STATUS
24 & 0 0 No operation
QS0 and QS1
25 0 1 First byte from instruction queue
1 0 Empty instruction queue
1 1 Subsequent byte from instruction queue

These are basically 3 status pins and are active low. This means that if
the status at all the 3 pins is 0 then it shows that multiple interrupts
are to be handled in maximum mode.
The table below is representing the status of the processor in
different combinations
̅̅̅̅
𝐒𝐨 ̅̅̅̅
𝐒𝟏 ̅̅̅̅
𝐒𝟐 Status
26 ̅̅̅̅ 0 0 0 Interrupt acknowledgement (INTA)
𝐒𝐨 , ̅̅̅̅
𝐒𝟏 & ̅̅̅̅
𝐒𝟐
to
0 0 1 I/O Read
28
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 None

When this signal is active, it indicates to the other processors not to

ask the CPU to leave the system bus. It is activated using the LOCK
29 ̅̅̅̅̅̅̅̅
𝐋𝐎𝐂𝐊 prefix on any instruction.
Example: LOCK XCHG reg., Memory; Register is any register and
memory are the address.
These are the Request/Grant signals used by the other processors
30 & ̅̅̅̅ ̅̅̅̅̅̅
𝐑𝐐 /𝐆𝐓 𝟎 and requesting the CPU to release the system bus. When the signal is
31 ̅̅̅̅ ̅̅̅̅̅̅
𝐑𝐐 /𝐆𝐓𝟏 received by CPU, then it sends acknowledgment. ̅̅̅̅ ̅̅̅̅̅̅
𝐑𝐐 /𝐆𝐓 𝟎 has a
̅̅̅̅ ̅̅̅̅̅̅
higher priority than 𝐑𝐐 /𝐆𝐓𝟏 .
̅̅̅̅
𝐑𝐃 =0; The microprocessor is performing read operation with either
32 ̅̅̅̅
𝐑𝐃
memory or I/O devices.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
The MN/𝐌𝐗 ̅̅̅̅̅ pin shows whether the 8086 microprocessor is
operating in the minimum mode or maximum mode.

̅̅̅̅̅ = 0; the 8086 is operating in maximum mode i.e., multiple

MN/𝐌𝐗
33 ̅̅̅̅̅
MN/𝐌𝐗
processors.
̅̅̅̅̅ = 1; the 8086 is operating in minimum mode i.e., single
MN/𝐌𝐗
processor.

̅̅̅̅̅̅
𝐁𝐇𝐄 is an acronym for Bus High Enable. The combination of the ̅̅̅̅̅̅
𝐁𝐇𝐄
signal and S7 status informs about the existence of the data on the bus.
Also, different combinations show whether the bus is containing
overall 16-bit, upper byte or lower byte of the data.
34 ̅̅̅̅̅̅/ S7
𝐁𝐇𝐄 𝐁𝐇𝐄 S7 Status
̅̅̅̅̅̅
0 0 All 16-bit data will be accessed
0 1 Upper byte of the data will be accessed
1 0 Lower byte of the data will be accessed
1 1 None or Idle
35 A16/S3, Out of 20 address bits, 4 are present in the multiplexed form with the
to A17/S4, status signals. In the case of memory operations, these pins act as an
38 A18/S5 and address bus and contain the memory address of any particular
A19/S6 instruction or data.
However, from I/O operations these pins are low that shows the status
of the processor.
Basically, the signal at S3 and S4 show that which segment is currently
accessed by the microprocessor among the four segments present in
it.
S3 S4 STATUS
0 0 Extra Segment access
0 1 Stack segment access
1 0 Code segment access
1 1 Data segment
S5: when enabled, shows the presence of an interrupts in the
microprocessor. So, basically, it serves as an interrupt flag.

S6: Shows the status of the bus master for the current operation i.e.
Whether the 8086 is the bus master or any other proficient device is
acting as the bus master.
When S6= 0; it indicates the 8086 is holding the access of the bus
otherwise it is high i.e., 1.
40 VCC The external power supply of +5V is connected to the microprocessor

The Pin description of 8086 Microprocessor minimum mode:

Pin
Pin Name Description
No.

̅̅̅̅̅̅̅ is an interrupt acknowledgement signal. When the

𝐈𝐍𝐓𝐀
24 ̅̅̅̅̅̅̅
𝐈𝐍𝐓𝐀
microprocessor receives this signal, it acknowledges the interrupt.

ALE stands for address enable latch.

ALE=1; The AD0 to AD15 are acting as address lines A0 to A15 during T1
ALE
25 clock.
ALE=0; The AD0 to AD15 are acting as data lines D0 to D15 during later
clock

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

̅̅̅̅̅̅
𝐃𝐄𝐍 is used for data enable and this is an active low pin.
26 ̅̅̅̅̅̅
𝐃𝐄𝐍 ̅̅̅̅̅̅
𝐃𝐄𝐍0; then the transceiver gets enabled and it separates the data from
the multiplexed address and data bus.

DT/𝐑̅ pin is used to show whether the data is getting transmitted or is

̅ received.
27 DT/𝐑 ̅ =1; provides the information regarding the transmission of data.
DT/𝐑
DT/𝐑̅ =0; indicates reception of data.

̅̅̅ pin indicates whether the processor is performing an operation

M/𝐈𝐎
̅̅̅ with memory or I/O devices.
28 M/𝐈𝐎 ̅̅̅ = 1; operation is carried out through the memory.
M/𝐈𝐎
̅̅̅ = 0; operation is carried out through the I/O devices.
M/𝐈𝐎

̅̅̅̅̅ =0; indicates that the processor is performing write operation

𝐖𝐑
29 ̅̅̅̅̅
𝐖𝐑
from either memory or I/O devices.
This pin is used as a response pin for the hold request. Once request for
accessing the buses is produced by an external entity. Then the
30 HLDA
microprocessor acknowledges the device that its request will be
considered once it gets over by the current operation.
HOLD signal indicates to the processor that external devices are
31 HOLD
requesting to access the address/data buses.

3.1.3. Memory Segmentation and Physical Address

Explain the memory segmentation of 8086 in details.

AKTU Question Paper 2022-23, 10 MARKS
Discuss the various memory segments in 8086.
AKTU Question Paper 2021-22, 2 MARKS
Discuss the memory segmentation in 8086 and the various segments of the memory.
AKTU Question Paper 2020-21, 2 MARKS
Memory Segmentation
Memory segmentation is the method where whole memory is divided into the smaller parts called
segments, and each segment can be up to 64 KB (kilobytes) in size. This segmentation allows the
processor to access a total of 1 MB (megabyte) of memory.
• DATA SEGMENT
• CODE SEGMENT
• STACK SEGMENT and
• EXTRA SEGMENT.
Each segment can be up to 64 KB (kilobytes) in size. Segment registers store starting address of
each segments in memory.

Maximum size of segment:

• All offsets are limited to 16-bits. It means that the maximum size possible for segment is
216= 65,535 bytes (64 KB).
• The offset of the first location within the segment is 0000 H. The offset of the last location
in the segment is FFFF H i.e. the address within each segment is ranging between 0000 H
to FFFF H (64 KB).

The 8086 microprocessor has 20 lines address bus. With 20 address lines, the memory, allowing
it to address memory of up to 220 bytes i.e. 220= 1,048,576 bytes (1 MB). 8086 can access memory
with address ranging from 00000 H to FFFFF H.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

Figure 3.4: 8086 Memory segmentation

Explain the physical address, offset address and segment address in context to 8086.
AKTU Question Paper 2021-22, 2 MARKS

The starting (base) address and end address (top) of each segment are as below:

Segment Starting address End (top) address Total Size

Data Segment 2000 H 2FFF H 64 KB
Code Segment 3000 H 3FFF H 64 KB
Stack Segment 5000 H 5FFF H 64 KB
Extra Segment 7000 H 7FFF H 64 KB

Segment Register:
The 8086 has four primary segment registers: CS (Code Segment), DS (Data Segment), SS (Stack
Segment), and ES (Extra Segment). Each of these registers holds a 16-bit value that represents
the base address of a specific segment in memory.

Offset Address:
Within each segment, memory is addressed using an offset value. The offset is a 16-bit value that
specifies the location of data or instructions within the segment. It's essentially a displacement
from the base address of the segment.

Physical Address:
The 20-bit address of a data or instructions is called its Physical Address i.e. a physical address
represents a specific location in the memory where data or instructions are stored. To calculate
the physical address of a memory location, the 8086 combines the value in the segment register
with the offset. This 20-bit physical address allows access to up to 1 MB of memory.

Physical address = (Base address×10H) + Effective address

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

Figure 3.5: Formation of 20-bit physical address

Default segment registers and offset registers used to calculate physical address are as shown in
table 3.1.
Table 3.1: Default segment registers and offset registers
Segment
Offset Register Function
Register
CS IP Address of the next instruction
DS BX, DI, SI Address of the data
SS SP, BP Address in the stack
ES BX, DI, SI Address of the destination data (for string operations)

Rules of Segmentation
• The starting address of a segment should be such that it can be evenly divided by 16.
• Minimum size of a segment can be 16 bytes and the maximum can be 64 kB.

Advantages of the Segmentation:

The main advantages of segmentation are as follows:
• It provides a powerful memory management mechanism.
• Data related or stack related operations can be performed in different segments.
• Code related operation can be done in separate code segments.
• It allows to processes to easily share data.
• It allows to extend the address ability of the processor, i.e. segmentation allows the use of
16-bit registers to give an addressing capability of 1 Megabytes. Without segmentation, it
would require 20-bit registers.
• It is possible to enhance the memory size of code data or stack segments beyond 64 KB
by allotting more than one segment for each area.

Example 1: If [CS]=234AH, [IP]=1234H find the physical address.

Solution: CS×10H = 234A0H
+
IP = 1234H
------------------------------------------
Physical Address =246D4H
------------------------------------------
Example 2: The value of Code Segment CS Register is 4042H and the value of different offsets is
as follows: BX:2025H, IP: 0580H, DI: 4247H. Calculate the physical address of the memory
location pointed by the CS register.

Solution:
The offset of the CS Register is the IP register. Therefore, the effective address of the memory
location pointed by the CS register is calculated as follows:
Physical address = (Base address of CS register X 10H) + Address of IP
Physical address = 4042 X 10H + 0580
=40420+0580
Physical address =409A0H

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
Example 3: Calculate the effective address for the following register: SS: 3640H, SP: 1735H, BP:
4826H

Solution:
Both SP and BP are the offsets for Stack Register (SS). The address calculated when BP is taken as
the offset gives the starting address of the stack. The address when SP is taken as the offset
denotes the memory location where the top of the stack lies.
Therefore, the effective address for both these cases is:
(SS X 10H) + SP = 3640H X 10H + 1735H
= 36400H + 1735H
= 37B35H
(SS X 10H) + BP = 3640H X 10H + 4826H
= 36400H + 4826H
= 3AC26H

Example 4: The value of the DS register is 3032H. And the BX register contains a 16-bit value
which is equal to 3032H. 0008H is added to BX. ADD BX, 0008H, the register AX contains some
value which needs to be stored at a location as follows: MOV [BX], AX
Calculate the address at which the value of the AX will be stored

Solution:
After executing the first instruction, the value of BX Register is as follows:
BX = 303AH
The BX register is an offset of the Data Segment (DS) register. So, the location at which the value
of the AX register will be stored is calculated as follows:
(DS X 10H) + BX = 3032H X 10H +303AH
= 30320H + 303AH
= 3335AH

Example 5: You are provided the following values: DS: 3056H, IP: 1023H, BP: 2322H and SP:
3029H. Can you calculate the effective address of the memory location as per the DS register?

Solution:
No, the effective address of the DS register cannot be calculated from the given values because
none of the given offset is an offset of the DS Register.

3.1.4. Instruction format of 8086

An 8086 instruction consists of different fields. One filed is called the operation code or op code.
Opcode indicates the operation to be performed by the instruction. The other fields are called the
operands. Operands indicate the data or the address of the data to be operated upon by the
instruction.
A general instruction format is shown in the figure 3.6.
Opcode Operand . . . . Operand
Figure 3.6: General instruction format

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
3.1.5. Addressing Modes of 8086
Discuss the various addressing modes in 8085 along-with examples.
AKTU Question Paper 2020-21, 10 MARKS
Discuss the various addressing modes available in 8086 along-with examples.
AKTU Question Paper 2021-22, 10 MARKS

The Intel 8086 microprocessor supports various addressing modes, which determine how
operands (data) are accessed or addressed in instructions. These addressing modes provide
flexibility in how data is fetched or manipulated during program execution. The commonly used
addressing modes of the 8086 are as follows:

1 Immediate In this addressing mode, the operand is a constant value specified in the
Addressing: instruction itself.
Example: MOV AX, 1234; loads the value 1234 H into the AX register.

2 Register In this addressing mode, the operand is stored in one of the CPU registers.
Addressing: Example: ADD AX, BX; adds the value in the BX register to the AX
register.
3 Direct In this addressing mode, the operand's address is directly specified in the
Addressing: instruction.
Example: MOV AX, [1592H]
MOV AL, [0A00H]; moves the value at memory address 0A00H into the
AL register.
4 Register In this addressing mode addressing mode allows data to be addressed at
Indirect any memory location through an offset address held in any of the
Addressing: following registers: BP, BX, DI & SI.
Example: MOV AX, [BX]; Suppose the register BX contains 4895H, then
the contents 4895H are moved to AX
5 Based In this addressing mode, the offset address of the operand is given by the
Addressing: sum of contents of the BX/BP registers and 8-bit/16-bit displacement.
Example: MOV DX, [BX+04]

6 Based-index In this addressing mode, the operands offset address is found by adding
addressing the contents of SI or DI register and 8-bit/16-bit displacements.
mode: Example: MOV BX, [SI+16]
7 Based In this addressing mode, the operands offset is computed by adding the
indexed with base register contents and Index registers contents and 8 or 16-bit
displacement displacement.
mode: Example: MOV AX, [BX+DI+08]

8 Scaled Index In this addressing mode, an index register is multiplied by a scaling factor
Addressing and added to a base register to form an address.
Mode Example: MOV AL, [BX+SI*2] moves the value at the memory location
pointed to by (BX+SI*2) into the AL register.

Page | 13
 Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
EVOLUTION OF MICROPROCESSORS:
Explain the various generations of microprocessor.
AKTU Question Paper 2022-23, 10 MARKS

Microprocessors have evolved through several generations, each marked by significant

improvements in processing power, architecture, and capabilities. Here's an overview of the
major generations of microprocessors:

First Generation (1971-1976):

• The first microprocessor was the Intel 4004, released in 1971.
name • These early microprocessors had limited processing power and were primarily used
in calculators and simple control systems.
yr
• They featured 4-bit data buses and clock speeds measured in kilohertz.
bit • The 8085 was released in 1976. It is 8-bit microprocessor and can operate with 3 MHz.
processing pwr This microprocessor is used for general purpose applications (example: Traffic signal
etc.)
clock
application Second Generation (1976-1990):
• The Intel 8086, released in 1978, marked the beginning of this generation.
• 8-bit and 16-bit microprocessors were common, offering increased processing power
and expanded memory addressing capabilities.
• Key microprocessors included the Intel 8088, 8086, and Motorola 68000 series.
• Clock speeds increased into the megahertz range, and microprocessors started to be
used in early personal computers.

Third Generation (Late 1980s-1990s):

• The introduction of 32-bit microprocessors, such as the Intel 80386 and 68020,
signaled the third generation.
• These processors offered greater processing power, 32-bit memory addressing, and
support for multitasking and protected memory.
• Advanced instruction sets and cache memory were introduced to boost performance.
• This era saw the rise of personal computers and workstations.

Fourth Generation (1990s-Present):

• The fourth generation includes the Pentium series (e.g., Intel Pentium) and other 32-
bit and 64-bit processors.
• Clock speeds continued to rise, and processors incorporated advanced features like
MMX, SSE, and SIMD instructions for multimedia applications.
• Mobile processors (e.g., ARM-based processors) and server processors (e.g., Intel
Xeon) became prominent.
• The microarchitecture became more complex, with multiple cores and hyper-
threading.

Fifth Generation (Present and Beyond):

• The fifth generation is characterized by the proliferation of multi-core processors,
increased energy efficiency, and advancements in parallel processing.
• Processors are designed for artificial intelligence (AI), machine learning, and Internet
of Things (IoT) applications.
• Graphics Processing Units (GPUs) and specialized accelerators play a crucial role in
data-intensive workloads.
• Quantum computing, neuromorphic computing, and other emerging technologies are
pushing the boundaries of what's possible in computing.

These generations represent the major milestones in the development of microprocessors,

with each generation building upon the advancements of the previous one.

Page | 14
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
As technology continues to evolve, microprocessors are expected to become more powerful,
energy-efficient, and versatile, enabling a wide range of applications in both consumer and
industrial domains.

PREVIOUS YEAR AKTU EXAM QUESTIONS ON 8086

MICROPROCESSOR

8086 ARCHITECTURE
Draw the architecture of 8086 Microprocessors and explain its all blocks.
AKTU Question Paper 2022-23, 10 MARKS

Investigate the need of pre-fetch instruction queue in 8086.

AKTU Question Paper 2021-22, 2 MARKS

MEMORY SEGMENTATION

Explain the memory segmentation of 8086 in details.

AKTU Question Paper 2022-23, 10 MARKS

Discuss the various memory segments in 8086.

AKTU Question Paper 2021-22, 2 MARKS

Discuss the memory segmentation in 8086 and the various segments of the memory.
AKTU Question Paper 2020-21, 2 MARKS

PHYSICAL ADDRESS
Explain the physical address, offset address and segment address in context to 8086.
AKTU Question Paper 2021-22, 2 MARKS

ADDRESSING MODES OF 8086

Discuss the various addressing modes in 8085 along-with examples.
AKTU Question Paper 2020-21, 10 MARKS

Discuss the various addressing modes available in 8086 along-with examples.

AKTU Question Paper 2021-22, 10 MARKS

EVOLUTION OF MICROPROCESSORS
Explain the various generations of microprocessor.
AKTU Question Paper 2022-23, 10 MARKS

Page | 15
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

PERIPHERAL DEVICES
Peripheral Devices: 8237 DMA Controller, 8255 Programmable Peripheral Interface,
8253/8254 Programmable Timer/Counter, 8259 Programmable Interrupt Controller, 8251
USART and RS 232C.

3.2 Peripheral devices

Peripheral interfacing devices are hardware components or integrated circuits (ICs) designed to
facilitate the connection and communication between a microprocessor and external peripheral
devices.

3.2.1 Direct Memory Access Controller 8237:

With the help of a functional block diagram and working of 8257 DMA controller.
AKTU Question Paper 2022-23, 10 MARKS
Explain Direct Memory Access (DMA).
AKTU Question Paper 2022-23, 2 MARKS
Explain Direct Memory Access (DMA).
AKTU Question Paper 2020-21, 2 MARKS
Illustrate the process of DMA with the help of 8237 DMA controller.
AKTU Question Paper 2020-21, 10 MARKS
Direct Memory Access is a process where data is transferred between two peripherals
directly without the involvement of the microprocessor.

This process employs the 2 signals HOLD and HLDA pin on the microprocessor.

HOLD: This is an active high input signal to the 8085 microprocessor from another master
requesting the use of the address and data buses. After receiving the Hold request, the
microprocessor relinquishes the buses. The Hold Acknowledge (HLDA) signal is sent out. The
microprocessor regains the control of the buses after HOLD goes low.

HLDA (Hold Acknowledge): This is an active high output signal indicating that the
microprocessor is relinquishing control of the buses.

A DMA controller uses these signals as if it were a peripheral requesting the MPU for the control
of the buses. The MPU communicates with the controller by using the Chip Select line, buses, and
control signals. Once the controller has gained control, it plays the role of a processor for data
transfer.

To perform data transfer operation, the DMA should have the following
1 a data bus,
2 an address bus,
3 Read/Write control signals, and
4 control signals to disable its role as a peripheral and to enable its role as a processor.

This process is called switching from the slave mode to the master mode.

The 8237 DMA Controller:

• The 8237 is a programmable Direct Memory Access controller (DMA) with a 40-pin
package.
• It has four independent channels with each channel capable of transferring 64 K bytes.

Page | 16
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
DMA CHANNEL AND INTERFACING:

Figure 3.7: 8237A DMA controller with Internal Registers

Figure 3.7 shows a logical pin out and internal registers of the 8237A and interfacing with the
8085 using a 3-to-8 decoder.

The 8237 has four independent channels, CHO to CH3. Internally, two 16-bit registers are
associated with each channel: One is used to load a starting address of the byte to be copied
and the second is used to load a count of the number of bytes to be copied.

Figure 3.7 shows eight such registers that can be accessed by the MPU. The addresses of these
registers are determined by four address lines, A3 to A0, and the Chip Select (CS) signal.
Address lines Hex
Selected Channels/Register etc.
A3 A2 A 1 A0 Address
0000 00 H CHO Memory Address Register (MAR)
0001 01 H CH0 Count Register
0010 02 H CH1 Memory Address Register (MAR)
0011 03 H CH1 Count Register
.
.
.

1111 0F H WR all Mask register bits

Page | 17
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
The address 0000 on lines A3 to A0 selects CHO Memory Address Register (MAR) and address
0001 selects the next register, CH0 Count. Similarly, all the remaining registers are selected in
sequential order. The last eight registers are used to write commands or read status as
shown in figure 3.7, the MPU accesses the DMA controller by asserting the signal Y_0 of the
decoder. Therefore, the addresses of these internal registers range from 00 to 0FH as follows:

DMA SIGNALS:
In figure 3.7: signals are divided into two groups
i. The left of the 8237 is used for interfacing with the microprocessor
ii. The right-hand side of the 8237 is for communicating with peripherals.

The signals that are necessary to understand the DMA operations are explained as follows:
CLK: Clock input to 8237. The maximum clock frequency is 5 MHz. In the 8085 system, the
processor clock is inverted and applied to CLK 8237.
CS: Logic low chip select signal. It is an input signal to select 8237 during programming mode.
RESET : Reset input to 8237. Connected to a system reset, when the RESET signal
goes high the command, status, request, and temporary registers are
cleared. It also clears the first-last flip-flop and sets the mask register.
READY : Ready input signal and it is tied to VCC for normal timings. When READY
input is tied low, the 8237 enters a wait state. This is used to get extra time
in DMA machine cycles to transfer data between slow memory and IO
devices.
HRQ : Hold request output signal. It is the hold request signal sent by 8237 to the
processor HOLD pin, to make a request for the bus to perform a DMA
transfer.
HLDA : Hold acknowledge input signal. It is the hold acknowledge signal to be sent
by the processor to inform the acceptance of the hold request.
DREQ3 – : These are the four independent, asynchronous input signals to the DMA
DREQ0 channels from peripherals such as floppy disks and the hard disk. Used by
IO devices to request for DMA to transfer.
DACK3 – : These are output lines to inform the individual peripherals that a DMA is
DACK0 granted. DREQ and DACK are equivalent to handshake signals in I/O
devices.
DB7 – DB0 : Data bus lines. These pins are used for data transfer between the processor
and DMA.
̅̅̅̅̅
𝐈𝐎𝐑 : Bidirectional IO read control signal. It is an input control signal for reading
the DMA controller during programming mode and an output control signal
for reading the IO device during DMA (memory) write cycle.
̅̅̅̅̅̅
𝐈𝐎𝐖 : Bidirectional IO writes control signal. It is an input control signal for writing
the DMA controller during programming mode and an output control signal
for writing the IO device during DMA (memory) read cycle.
EOP : End of process. It is a bidirectional low active signal. It is used either as an
input to terminate a DMA process or as an output to inform the end of the
DMA transfer to the processor. This output can be used as an interrupt to
terminate DMA.
A3 – A0 : Four bidirectional address lines. Used as input address during
programming mode to select internal registers. During DMA mode the low-
order four bits of memory address are output by 8237 on these lines.

Page | 18
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
A7 – A4 : Four unidirectional address lines. Used to output the memory address bits
A7 to A4 during DMA mode.
AEN : Address enable output signal. It is used to enable the address latch
connected to DB7 – DB0 pins of 8237. It is also used to disable any buffers in
the system connected to the processor.
ADSTB : Address strobe output signal. It is used to latch the high-byte memory
address issued through DB7 to DB0 lines by 8237 during DMA mode into an
external latch.
̅̅̅̅̅̅̅̅
𝐌𝐄𝐌𝐑 : Memory read control signal. It is an output control signal issued during a
DMA read operation.
̅̅̅̅̅̅̅̅̅
𝐌𝐄𝐌𝐖 : Memory write control signal. It is an output control signal issued during
DMA write operation.

INTERFACING 8237A DMA CONTROLLER WITH THE 8085:

Figure 3.8: Interfacing 8237A DMA Controller with the 8085

The DMA is used to transfer data bytes between I/O such as floppy disk and the system memory
̅̅̅̅̅, ̅̅̅̅̅̅
or from memory to memory at high speed. In includes 8-data lines, 4-control signals (𝐈𝐎𝐑 𝐈𝐎𝐖,
̅̅̅̅̅̅̅̅̅, 𝐌𝐄𝐌𝐖
𝐌𝐄𝐌𝐑 ̅̅̅̅̅̅̅̅̅̅) and 8-address lines A7-A0. It needs 16 address lines to access 64 KB.
Therefore, an additional 8 lines must be generated as shown in figure 3.7.
When a data transfer begins, DMA places the low-order byte on the address bus and the high-
order byte o the data bus and asserts AEN (address enable) and ADSTB bus i.e. it places the 16-
bit address on the system bus.

Page | 19
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
After the transfer of the first byte, the latch is updated when the lower byte generates a carry or
borrow.
Figure 3.8 has two latches, one latch (373 #1) to latch a high-order address from the data bus by
using the AEN and ADSTB signals, and the second latch (373 #2) to demultiplex the 8085 bus and
generate the low-order address bus by using the ALE (Address Latch Enable from the 8085)
signal. The AEN signal is connected to the ̅̅̅̅
OE signal of the second latch to disable the low-order
address bus from the 8085 when the first latch is enabled to latch the high-order byte of the
address.
PROGRAMMING THE 8237:

To implement the DMA transfer, the 8237 should be initialized by writing into various control
registers discussed earlier in the DMA channels and interfacing section.

To initialize the 8237, the following steps are necessary.

1 Write a control word in the Mode register that selects the channel and specifies the type
of transfer (Read, Write, or Verify) and the DMA mode (block, single-byte, etc.).
2 Write a control word in the Command register that specifies parameters such as priority
among four channels, DREQ and DACK active levels, and timing, and enables the 8237.
3 Write the starting address of the data block to be transferred in the channel Memory
Address Register (MAR).
4 Write the count (the number of the bytes in the data block) in the channel Count register.
5 The starting address of the data block is 4075H and subsequent data bytes have memory
addresses in increasing order.
6 The Command parameters should be: normal timing. fixed priority, late write. DREQ and
DACK are both active low.
7 Set up the demand mode whereby the DMA can complete the data transfer without any
interruption.

MVI A, 00000100B ; Command

OUT 08H ; Send command register
MVI A, 00000111B ; Mode
OUT OBH ; Send to Mode register
MVI A, 75H ; Low-order byte of starting address
OUT 06H ; Output to CH3 memory Address Register
MVI A, 40H ; Higher-order byte of starting address
OUT 06H ; Output to CH3 memory Address Register
MVI A, FFH ; Low-order byte of the count 03FF H
OUT 07H ; Output to CH3 Count register
MVI A, 03H ; High-order byte of the count 03FF H
OUT 07H ; Output to CH3 Count register
MVI A, 10000000B ; Command
OUT 08H ; Send to Command register

DMA OPERATION:
The DMA controller can be classified under two modes:
i. The microprocessor and peripherals such as floppy disks. The DMA plays two roles in
a given system: It is an I/O to the microprocessor (Slave Mode) and
ii. It is a data transfer processor to peripherals such as floppy disks (Master Mode).

Page | 20
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
8255 PROGRAMMABLE PERIPHERAL INTERFACE:
Explain the pin diagram of 8255 along-with the block diagram.
AKTU Question Paper 2020-21, 10 MARKS

Explain the CWR of 8255 Programmable Peripheral Interface and also discuss the BSR
mode. AKTU Question Paper 2022-23, 2 MARKS

With the help of a functional block diagram explain the organization and working of 8255
microprocessor. AKTU Question Paper 2022-23, 2 MARKS

Figure: 8255 interfacing with microprocessor

• PPI 8255 is a general purpose programmable I/O device designed to interface the
microprocessor with its outside world such as ADC, DAC, keyboard etc.

It contains the following blocks

1. Data bus buffer
2. Read/Write control logic
3. Port A and Port B
4. Port C
5. Group A and Group B control

Page | 21
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
1. DATA BUS BUFFER:
• The 8-bit bidirectional data bus buffer is used to interface the 8255 internal data bus with
the system data bus (Microprocessor).
• The direction of the data buffer is decided by read and write control signals.
• When the read is activated, it transmits data to the system data bus.
• When a write is activated, it receives data from the system data bus.

2. READ/WRITE CONTROL LOGIC:

• The control signals are 𝐑𝐃
̅̅̅̅ & 𝐖𝐑
̅̅̅̅̅ and address signals used are A0, A1 and 𝐂𝐒 ̅̅̅̅.
• The signals 𝐑𝐃 & 𝐖𝐑 are connected to 𝐈𝐎𝐑 & 𝐈𝐎𝐖 or 𝐌𝐄𝐌𝐑 & 𝐌𝐄𝐌𝐖
̅̅̅̅ ̅̅̅̅̅ ̅̅̅̅̅ ̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅
• The address lines of A0 & A1 of 8085 are directly connected to address lines A 0 & A1 of
8255.
• The 8255 operation/selection is enabled/disabled by ̅𝐂𝐒 ̅̅̅ signal. The ̅𝐂𝐒̅̅̅ is connected to
address chip select decoder.

3. PORT A AND PORT B

• Port A and port B consist of an 8-bit bidirectional data output latch/buffer and an 8-bit
data input buffer.
• The function of ports A and B is decided by the control bit pattern available in GA and GB
control.
• The functions of ports A and B are also independent of the mode of operation.

4. PORT C
• Port C consists of an 8-bit bidirectional data output latch/buffer and an 8-bit data input
buffer.
• It is divided into 2 sections, Port C upper PCU and Port C lower PCL. These two sections
can be programmed and used separately as a 4-bit I/O port.
• It can be used as
i. Simple I/O
ii. Handshake signals
iii. Status signal inputs.
• Port C is used in combination with port A & Port B for both the status and handshaking
signals.

5. GROUP A AND GROUP B CONTROL:

• The 8255 I/O ports are divided into 2 sections. Group A (GA) and Group B (GB).
• Group A consists of PORT A and PORT C upper.
• Group B consists of PORT B and PORT C lower.
• Each group is programmed through software.
• Group A controls port A with higher order port C bits whereas group B controls port B
with lower order port C bits.
Depending upon the value if ̅𝐂𝐒
̅̅̅, A1 and A0 we can select different ports in different modes as
input-output function or BSR. This is done by writing a suitable word in control register (control
word D0-D7).
̅𝐂𝐒
̅̅̅ A1 A0 OPERATION Address
0 0 0 PORT A 80 H
0 0 1 PORT B 81 H
0 1 0 PORT C 82 H
0 1 1 Control Register 83 H
1 X X No Selection X

8255 OPERATING MODES or Modes of 8255:

8255 has two modes of operation
1. Bit set reset (BSR) mode
2. Input/output (I/O) mode (Mode 0, Mode 1 & Mode 2)

Page | 22
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
BSR (BIT SET RESET MODE):
The content of the control word register will be as follows, when used in the BSR mode

Figure: Control Word Register in BSR mode

• The BSR mode is a port C bit set/reset mode.

• If MSB of Control Word Register (D7) is 0, PPI works in BSR mode. In this mode only, Port
C bits are used for set or reset.
• The individual bit of port C can be set or reset by writing the control word in the control
register.
• At a time, only a single bit of port C can be Set or Reset.
• Is used for control or ON/OFF switch.
• BSR control word doesn’t affect ports A and B functioning.

The D3 D2 D1 bits in Control Word Register in the BSR mode

D3 D2 D1 Particular bit of Port C selected
0 0 0 Bit 0
0 0 1 Bit 1
0 1 0 Bit 2
0 1 1 Bit 3
1 0 0 Bit 4
1 0 1 Bit 5
1 1 0 Bit 6
1 1 1 Bit 7

INPUT/OUTPUT (I/O) MODE:

Figure: Input / Output Mode

If MSB of Control Word Register (D7) is 1, PPI works in input-output mode. This is further divided
into three modes:
1. Mode 0: Input / Output mode
2. Mode 1: Input / Output with handshaking
3. Mode 2: Bidirectional I/O port with handshaking
Page | 23
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
Mode 0:
• This is a basic input/output mode, whose features are:
• All the three ports (Port A, Port B & Port C) can be programmed in either input or output
mode.
• Ports don’t have handshake or interrupt capability

Mode 1:
• In this mode, input or outputting of data is carried out by taking the help of handshaking
signals, also known as strobe signals. The basic features of this mode are:
• Ports A and B can function as 8-bit I/O ports, taking the help of pins of Port C.
• I/Ps and O/Ps are latched.
• Interrupt logic is supported.
• Handshake signals are exchanged between CPU and peripheral prior to data transfer.
• In this mode, Port C is called status port.
• There are two groups in this mode Group A and Group B. They can be configured
separately. Each group consists of an 8-bit port and a 4-bit port. This 4-bit port is used for
handshaking in each group.

Mode 2:

• In this mode, the ports can be utilized for the bidirectional flow of information by
handshaking signals.
• The pins of group A can be programmed to acts as bidirectional data bus and the Port C
upper (PC7 – PC4) are used by the handshaking signal. The rest 4 lower Port C bits are
utilized for I/O operations.
• Port B can be programmed in mode 0 & 1 and in mode 1 the lower bits of Port C of group
B are used for handshaking signals.
• It also has interrupt handling capacity.

PIN DIAGRAM OF 8255:

It consists of 40 pins that operates in +5V regulated power supply out of which 24 pins are for
I/O that are programmable in groups of 12 pins and has three distinct modes of operation.

Figure: Pin diagram of 8255

Page | 24
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

Symbol Name Function

These are 8-bit bi-directional data bus lines, connected to the system
D0-D7 Data Bus
data bus for data transfer between CPU and 8255.

These are input, active HIGH address lines used to distinguish

̅̅̅̅
𝐂𝐒 Chip select different ports of 8255 such as Port A, Port B, Port C, and Control
register.

It is the signal used for read operation. A low signal at this pin shows
̅̅̅̅
𝐑𝐃 Read that CPU is performing read operation at the ports or status word
through data buffer.

It is the signal used for write operation. A low signal at this pin allows
̅̅̅̅̅
𝐖𝐑 Write the CPU to perform write operation over the ports or control register
of 8255 using the data bus buffer.

Address These are basically used to select the desired port among all the
A0-A1
lines ports of the 8255. i.e. Port A, Port B, Port C, and Control register.

This is an active HIGH input signal used to reset 8255. When 8255 is
RESET Reset reset, it clears the control word register and all ports are set to input
mode.

These are 8-bit bidirectional I/O pins used to send data to the
PA0- Port A pins
peripheral or to read data from the peripheral. The contents are
PA7 0 to 7
transferred to/from Port A.

Port B pins
PB0-PB7 These are 8-bit bidirectional I/O pins used the same as PA0-PA7
0 to 7

These are 8-bit bidirectional I/O pins. These lines are divided into 2
Port C pins sections i.e. PC0-PC3 and PC4-PC7. These two sections can be
PC0-PC7
0 to 7 individually used to transfer 4 bits of data from two separate port C
sections.

8253/8254 PROGRAMMABLE INTERVAL TIMER (PIT):

Demonstrate the architecture of 8253/54 Programmable Timer and discuss the control
word register.
AKTU Question Paper 2021-22, 10 MARKS
Name the 06 operating modes of 8254.
AKTU Question Paper 2022-23, 2 MARKS

The Intel 8253 Programmable Interval Timer (PIT) is timing device commonly used in
microprocessor-based systems to generate precise time delays and control events. It provides
a reliable and accurate timing reference for various applications.

The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for microprocessors
to perform timing and counting functions using three 16-bit counters each capable of handling
clock inputs up to 10 MHz. Each counter has 2 input pins, i.e. Clock & Gate, and 1 pin for “OUT”
output. To operate a counter, a 16-bit count is loaded in its register. On command, it begins to
decrement the count until it reaches 0, then it generates a pulse that can be used to interrupt
the CPU.

Page | 25
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

Functional Block Diagram of 8254 Timer

In the above figure, there are three counters, a data bus buffer, Read/Write control logic, and a
control register. Each counter has two input signals - CLOCK & GATE, and one output signal - OUT.

Data Bus Buffer:

It is a tristate, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the system
data bus. It has three basic functions
• Programming the modes of 8253/54.
• Loading the count registers.
• Reading the count values.

Read/Write Logic:
It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1. In the peripheral I/O mode,
the RD and WR signals are connected to IOR and IOW, respectively. In the memory mapped I/O
mode, these are connected to MEMR and MEMW. Address lines A0 & A1 of the CPU are connected
to lines A0 and A1 of the 8253/54, and CS is tied to a decoded address. The control word register
and counters are selected according to the signals on lines A0 & A1.
̅𝐂𝐒
̅̅̅ A1 A0 OPERATION
0 0 0 Counter 0
0 0 1 Counter 1
0 1 0 Counter 2
0 1 1 Control Word Register

COUNTERS:
Each counter consists of a single, 16 bit-down counters, which can be operated in either binary
or BCD. Its input and output are configured by the selection of modes stored in the control word
register. The programmer can read the contents of any of the three counters.

Page | 26
Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
Control Word Register:
This register is accessed when lines A0 & A1 are at logic 1. It is used to write a command word,
which specifies the counter to be used, its mode, and either a read or write operation. Following
table shows the result for various control inputs.

Format of Control Word 0f 8254 Timer

OPERATION OF 8253:
The functions of the 8253/54 can be described by Write and Read operation.

WRITE Operation:
• Write a control word into control register.
• Load the low-order byte of a count in the counter register.
• Load the high-order byte of count in the counter register.

READ OPERATION:
1. Simple Read:
It involves reading a count after inhibiting the counter by controlling the gate input or the
clock input of the selected counter, and two I/O read operations are performed by the
CPU. The first I/O operation reads the low-order byte, and the second I/O operation reads
the high order byte.

2. Counter Latch Command:

In the second method, an appropriate control word is written into the control register to
latch a count in the output latch, and two I/O read operations are performed by the CPU.
The first I/O operation reads the low-order byte, and the second I/O operation reads the
high order byte.

3. Read-Back Command (Available only for 8254):

The third method uses the Read-Back command. This command allows the user to check
the count value, programmed Mode, and current status of the OUT pin and Null count flag
of the selected counter(s).

8254 MODES OF OPERATION:

1. Mode 0 (Interrupt on terminal count)
2. Mode 1 (Programmable Monoshot)
3. Mode 2 (Rate Generator)
4. Mode 3 (Square Wave Generator)
5. Mode4(Software Triggered Strobe)
6. Mode 5 (Hardware Triggered Strobe)

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
The Description and operation of various modes of timer are depicted in the figures below.

MODE 0: INTERRUPT ON TERMINAL COUNT:

• In this mode, OUT is low.
• Once a count is loaded the counter is decremented after every cycle and when count
reaches zero, the OUT goes high.
• This can be used as an interrupt. The OUT remains high until a new count or command
word is loaded.
MODE 0: INTERRUPT ON TERMINAL COUNT
Write control word using counter 1, read load LSB, Mode 0, Binary
Counter
Select Binary
Operation Mode Select
Control Word Counter Counter
0 1 0 1 0 0 0 0
Control Word = 50 H Let Count = 04

This is used for event counting. After writing the control word, OUT is low at first. It will remain
low until the counter reaches 0, it is decremented by 1 after each clock cycle. Then the OUT
goes high, and remains high until a new count is there or a new Mode 0 control word is written
into the counter. The GATE=1 indicates enable counting, and 0 indicates disable counting.

MODE 1: HARDWARE RETRIGGERABLE ONE-SHOT

1. The output will be initially high
2. The output will go low on the CLK pulse following the rising edge at the gate input.
3. The output will go high on the terminal count and remain high until the next rising edge
at the gate input.

MODE 1: HARDWARE RETRIGGERABLE ONE-SHOT

Write control word using counter 0, read load LSB, Mode 1, Binary
Counter
Control Word Select Binary
Operation Mode Select
Counter Counter
0 0 0 1 0 0 1 0
Control Word = 12 H Let Count = 04

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

OUT will be high at first, it will go low on the clock pulse following a trigger to begin the one-
shot pulse. It will remain 0 until the counter reaches 0.

MODE 2: RATE GENERATOR

This mode functions like a divide by-N counter.
1. The output will be initially high.
2. The output will go low for one clock pulse before the terminal count.
3. The output then goes high, the counter reloads the initial count and the process is
repeated.
4. The period from one output pulse to the next equals the number of input counts in the
count register.

MODE 2: RATE GENERATOR

Write control word using counter 1, read load LSB, Mode 2, Binary
Counter

Control Word Select Binary

Operation Mode Select
Counter Counter
0 1 0 1 0 1 0 0
Control Word = 54 H Let Count = 04

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

Initially OUT is low. When the counting is enabled, it goes HIGH. This process repeats
periodically. This mode is used as frequency divided.

MODE 3: SQUARE WAVE GENERATION:

1. Initially output is high.
2. For even count, counter is decremented by 2 on the falling edge of each clock pulse. When
the counter reaches terminal count, the state of the output is changed and the counter is
reloaded with the full count and the whole process is repeated.
3. If the count is odd and the output is high the first clock pulse (after the count is loaded)
decrements the count by 1. Subsequent clock pulses decrement the clock by 2. After
timeout, the output goes low and the full count is reloaded. The first clock pulse
decrements the count by 3 and subsequent clock pulse decrement the count by two. Then
the whole process is repeated. In this way, if the count is odd, the output will be high for
(𝑛 + 1)/2 counts and low for (𝑛 − 1)/2 counts.

MODE 3: SQUARE WAVE GENERATION

Write control word using counter 1, read load MSB, Mode 3, Binary
Counter
Select Binary
Operation Mode Select
Control Word Counter Counter
0 1 1 0 0 1 1 0
Control Word = 66 H Let Count = 04

If the GATE is 1, then the counting is enabled, otherwise it is disabled. This mode is used to
generate the square wave. The time period is equal to count. If the count is even, the on-time of
wave is count/2. Otherwise on-time is (count+1)/2 and off-time is (count-1)/2.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
MODE 4: SOFTWARE TRIGGERED STROBE
1. The output will be initially high
2. The output will go low for one CLK pulse after the terminal count (TC).

MODE 4: SOFTWARE TRIGGERED STROBE

Write control word using counter 0, read load LSB, Mode 4, Binary
Counter
Select Binary
Operation Mode Select
Control Word Counter Counter
0 0 0 1 1 0 0 0
Control Word = 18 H Let Count = 04

If the GATE is 1, then the counting is enabled, otherwise it is disabled. Initially OUT value is
high and go low when count is at the last stage. The count is reloaded again for subsequent
clock pulse.

MODE 5: HARDWARE TRIGGERED STROBE (RETRIGGERABLE)

1. The output will be initially high.
2. The counting is triggered by the rising edge of the Gate.
3. The output will go low for one CLK pulse after the terminal count (TC).
MODE 5: HARDWARE TRIGGERED STROBE (RETRIGGERABLE)
Write control word using counter 0, read load LSB, Mode 5, Binary
Counter
Select Binary
Control Word Operation Mode Select
Counter Counter
0 0 0 1 1 0 1 0
Control Word = 1A H Let Count = 04

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
Initially OUT value is high. The counting is triggered by the rising edge of the Gate (Clock pulse).
When initial count is expired the OUT becomes low for one clock pulse, then high again. After
writing the control word and the initial count, the counter will not be loaded until clock pulse
after one trigger.

PIN DIAGRAM OF 8253/54:

Figure: Pin diagram of 8253/8254

Intel 8253 is a 24 Pin programmable IC. It has three counters which work independently and
whose width is of 16-bits.
VCC and GND These are the Power supply and ground pins which 8253 uses +5V as power
supply

D7-D0 These are 8-bit bidirectional data bus lines, connected to the system data bus
for data transfer between 8085 and 8254.

̅̅̅̅
RD ̅̅̅̅=0, the microprocessor reads the data from the
It is active low pin. When 𝐑𝐃
Selected counter

̅̅̅̅̅
WR It is active low pin. When ̅̅̅̅̅ 𝐖𝐑=0, the microprocessor writes into
counter/control register i.e. writes control information/loading of counters.

A1 & A0 A1 & A0 pins are connected to the address bus. These pins are used for the
selection of counters and control word register.

A1 A0 OPERATION
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register

̅̅̅
CS ̅̅̅= 0 then 8254
This is an active low input signal, used to select the 8254 IC. If CS
will be active and take part in data transfer from/to 8085 otherwise 8254 will
be in the de-active state.

CLK0 Clock input for counter 0

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices

CLK1 Clock input for counter 1

CLK2 Clock input for counter 2

Gate0 Controls function of counter 0 (i.e. gate terminals for triggering purpose)

Gate1 Controls function of counter 1 (i.e. gate terminals for triggering purpose)

Gate2 Controls function of counter 2 (i.e. gate terminals for triggering purpose)

Out0 Out0 is output terminal of counter 0

Out1 Out0 is output terminal of counter 1

Out2 Out0 is output terminal of counter 2

APPLICATIONS OF 8253/8254:
• To generate an accurate time delay
• As an event counter
• Square wave generator
• Rate generator
• Digital one shot

FEATURES OF 8253/54:
The most prominent features of 8253/54 are as follows:
• It has three independent 16-bit down counters.
• It can operate from DC up to 10MHz.
• The three counters can be programmed for either binary or BCD count.
• It is compatible with almost all microprocessors.
• 8254 has a powerful command called READ BACK command, which allows the user to
check the count value, the programmed mode, the current mode, and the status of the
counter.
• Counters can be programmed in six different modes.

DIFFERENCE BETWEEN 8253 AND 8254:

Sl.
8253 8254
No.
1 Its operating frequency is 0 - 2.6 MHz Its operating frequency is 0 - 10 MHz
2 It uses N-MOS technology It uses H-MOS technology
3 Read-Back command is not available Read-Back command is available
Reads and writes of the same counter Reads and writes of the same counter can
cannot be interleaved. be interleaved.
(cannot perform read and write (interleaving reads and writes of the
4
operations on the same counter same counter is a synchronization
simultaneously or in an alternating technique that allows multiple tasks to
fashion) access and manipulate a counter)

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
8259 PROGRAMMABLE INTERRUPT CONTROLLER:
The 8259 is a programmable interrupt controller specially designed to work with Intel
microprocessor 8080, 8085, 8086, 8088. The main features of 8259 programmable interrupt
controller are given below:
1. It can handle eight interrupt inputs. This is equivalent to providing eight interrupt pins
on the processor in place of one INTR (in 8085)/INT (in 8086) pin.
2. The chip can vector an interrupt request anywhere in the memory map from 0000H to
FFFFH in 8085 microprocessor. However, all the eight interrupts are spaced at an interval
of either four or eight locations. This eliminates the major drawback of 8085 interrupts
in which all interrupts are vectored to memory location on page 00H i.e., TRAP, RST7.5,
RST6.5 and RST5.5 are vectored to memory locations 0024H, 003CH, 0034H and 002CH
respectively.
3. It can resolve eight levels of interrupt priorities in a variety of modes. The priorities of
interrupts can be changed under running condition. Some of the desired lower priority
interrupts may be allowed to be acknowledged during the service of higher priority
interrupts.
4. Each of the interrupt requests can be masked individually similar to RST7.5, RST6.5 and
RST5.5 interrupts of 8085.
5. The status of pending interrupts, in service interrupts, and masked interrupts can be read
at any time similar to RST interrupts of 8085.
6. The chip can be programmed to accept interrupt requests either as level triggered or edge
triggered interrupt request unlike your RST interrupts where some are edge triggered
and some are level triggered. However, all interrupts must be either level triggered or
edge triggered.
7. If required, nine 8259 can be cascaded in a master-slave configuration mode to handle 64
interrupt inputs. In this case, the interrupting devices send their interrupt requests either
to slave 8259 or to master 8259 directly. The slave 8259 send their interrupt to master
interrupt request inputs and the master will send a single interrupt to microprocessor
interrupt pin INTR/INT.

Figure: Block Diagram of 8259

INTERRUPT REQUEST REGISTER (IRR): The interrupts at IRQ input lines are handled by
Interrupt Request Register internally. IRR stores all the interrupt requests in it in order to serve
them one by one on the priority basis.
IN-SERVICE REGISTER (ISR): This register stores all the interrupt requests those are being
served, i.e. ISR keeps a track of the requests being served.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
PRIORITY RESOLVER: This unit determines the priorities of the interrupt requests appearing
simultaneously. The highest priority is selected and stored into the corresponding bit of ISR
during INTA pulse. The IR0 has the highest priority while the IR7 has the lowest one, normally in
fixed priority mode. The priorities however may be altered by programming the 8259 in rotating
priority mode.

INTERRUPT MASK REGISTER (IMR): This register stores the bits required to mask the interrupt
puts. IMR operates on IRR at the direction of the Priority Resolver.

INTERRUPT CONTROL LOGIC: This block manages the interrupt and interrupt acknowledge
signals to be sent to the CPU for serving one of the eight interrupt requests. This also accepts
interrupt acknowledge (INTA) signal from CPU that causes the 8259 to release vector address on
to the data bus.

DATA BUS BUFFER: This tristate bidirectional buffer interfaces internal 8259 bus to the
microprocessor system data bus. Control words, status and vector information pass through
buffer during read or write operations.

READ WRITE CONTROL LOGIC: This circuit accepts and decodes commands from the CPU. This
also allows the status of the 8259 to be transferred on to the data bus.

CASCADE BUFFER/COMPARATOR: This block stores and compares the ID's of all the 8259 used
in the system. The three I/O pins CAS0-2 are outputs, when the 8259 is used as a master. The
same pins act as inputs when the 8259 is in slave mode. The 8259 in master mode sends the ID
of the interrupting slave device on these lines. The slave thus selected, will send its pre-
programmed vector address on the data bus during the next INTA pulse.

INTERRUPT SEQUENCE:
The powerful features of the 8259 in a microcomputer system are its programmability and the
interrupt routine addressing capability. The latter allows direct or indirect jumping to the specific
interrupt routine requested without any polling of the interrupting devices. The normal sequence
of events during an interrupt depends on the type of CPU being used. The events occur as follows
in an 8085 system:
1. One or more of the INTERRUPT REQUEST lines (IR7-0) are raised high, setting the
corresponding IRR bit(s).
2. The 8259 evaluates these requests, and sends an INT to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds with an INTA pulse.
4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set, and the
corresponding IRR bit is reset. The 8259 will also release a CALL instruction code
(11001101) onto the 8-bit Data Bus through its D7-0 pins.
5. This CALL instruction will initiate two more INTA pulses to be sent to the 8259A from the
CPU group.
6. These two INTA pulses allow the 8259 to release its preprogrammed subroutine address
onto the Data Bus. The lower 8-bit address is released at the first INTA pulse and the
higher 8-bit address is released at the second INTA pulse. 7. This completes the 3-byte
CALL instruction released by the 8259. In the AEOI mode the ISR bit is reset at the end of
the third INTA pulse.
7. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end
of the interrupt sequence.
When the 8259 PIC receives an interrupt, INT becomes active and an interrupt acknowledge cycle
is started. If a higher priority interrupt occurs between the two INTA pulses, the INT line goes
inactive immediately after the second INTA pulse. After an unspecified amount of time the INT
line is activated again to signify the higher priority interrupt waiting for service. This inactive
time is not specified and can vary between parts.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
PIN DIAGRAM OF 8259:

Figure: Pin Diagram of 8259

Bi-directional, tristate, buffered data lines. Connected to data bus directly or

D0-D7
through buffers
̅̅̅̅
RD Active low read control
̅̅̅̅̅
WR Active low write control
A0 Address input line, used to select control register
̅̅̅
CS Active low chip select
CAS0-2 Bi-directional,3-bit cascade lines. In master mode, PIC places slave ID no. on
these lines. In slave mode, the PIC reads slave ID no. from master on these lines.
It may be regarded as slave- select.
̅̅̅/EN
SP ̅̅̅̅ Slave program / enable. In non-buffered mode, it is SP-bar input, used to
distinguish master/slave PIC. In buffered mode, it is output line used to enable
buffers.
INT Interrupt line, connected to INTR of microprocessor
̅̅̅̅̅̅̅
INTA Interrupt ack, received active low from microprocessor
IR 0-7 Asynchronous IRQ input lines, generated by peripherals.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
8251 USART & RS 232C:

USART stands for Universal Synchronous and Asynchronous Receiver Transmitter

Figure: Architecture of 8251 USART

Data Bus Buffer: It basically interfaces the 8251 with the internal system buses of the processor.
The data bus buffer has 8-bit bidirectional data bus that allows the transfer of data bytes, status
or command word between the processor and external devices.

Read/Write Control Logic: This functional unit generates a control signal for the operation of
8251 according to the signal present in the control bus of the processor. Basically, it performs
decoding operation of the control signal produced by the processor, so that respective operation
can be performed by the USART.

The control formats for system operation is stored in control and command word registers
present in the read/write logic unit.

The signals handled by the read/write control logic unit are discussed below:
• CS: It is chip select. A low signal at this pin shows that processor has selected 8251 in order
to communicate with the peripheral devices.
• C/D: As the system has control, status and data register. So, when a high signal is present at
this pin then control or status register is addressed. While in case of low signal data register
is addressed.
• RD and WR: Both read and write are active low signal pins. A low signal at RD shows that the
processor is reading the control, status or data bytes from the 8251. While at WR indicates
the write operation over the data bus of 8251.
• CLK and RESET: CLK stands for clock and it produces the internal timing for the device. While
an active high signal at the RESET pin puts the 8251 in the idle mode.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
3. Transmit Buffer: This unit is used to change the parallel data received from the CPU into serial
data by inserting the necessary framing information. Once the data is transformed into serial
form, then in order to transmit it to the external devices, it is provided to the TxD pin of the 8251.
This unit consists of 2 registers. These are as follows:
• Buffer register: Basically, the data provided by the processor is stored in the buffer register.
As we know that initially, the CPU provides parallel data to 8251. So, the processor loads the
parallel data to the buffer register. Further, this data is fed to the output register.
• Output register: The parallel data from the buffer register is fed to the empty output register.
This register changes the 8-bit parallel data into a stream of serial bits. Then further the serial
data is provided at the TxD pin so as to have its transfer to the peripheral device.
It performs both synchronous and asynchronous transmission and reception. Thus, in case of
asynchronous transmission, start and stop bit is added by the transmitter in order to notify the
external devices about the data transmission.
But in case of synchronous transmission, the clock signal is used thus there exists no need of
adding additional bits expect the parity bit (if required).

4. Transmit Control: As the name of the unit is itself indicating that it is controlling the
transmission action. And it does so by accepting and sending signals both externally and
internally.
The various control signal generated by this unit are as given below:
• TxRDY: It implies transmit ready. This signal is used to notify the processor that the buffer
register of the 8251 is empty and ready to accept the data.
• The status read operation is utilized by the processor in order to check the presence of the
signal.
• TxE: This stands for transmitter empty. It is an active high signal that indicates that the output
buffer is empty and thus data received from the processor can be loaded to it for conversion.
• TxC: It stands for transmitter clock and is an active low pin. It controls the rate of character
transmission by the USART.
• However, 8251 offers programmable clock rate. As by writing appropriate mode word in the
mode set register the clock division can be programmed.

5. Receive Buffer:
• This unit takes the serial data from the external devices, changes the serial data into the
parallel form so that it can be accepted by the processor. It consists of 2 registers: receiver
input register and buffer register.
• When the external device is ready to send the data to the 8251 then it sends a low signal
to the RxD line of the 8251. In asynchronous mode, once 8251 receives a low signal it
considers that signal as start bit of the data.
• So, once the start bit is successfully accepted by 8251, then it also receives the whole data
bits in serial form along with parity and stop bits.
• Once the data is received by the receiver input register then it converts the data bits in
parallel form and sends it to the receiver buffer register.
• In case of the synchronous mode of operation, according to the clock input, the external
device loads the serial data bits in the receiver input register. And on converting the serial
data to parallel format the receiver input register sends the data to the buffer register.

6. Receiver Control
This unit controls the operation of the receiver buffer. It manages the data reception, along with
that it also detects the presence of false start bit, error in parity bit, framing errors etc.
• RxRDY: It stands for receiver ready. When this signal goes high then it indicates that the
receiver buffer register is holding the data and is ready to transfer it to the processor. Once
the CPU reads the data sent by the 8251 then this pin is reset.
• RxC: It stands for receiver clock. This clock signaling controls the rate at which the 8251
receives the data in the synchronous mode of operation. It is provided by the modem and is
equal to the baud rate. While asynchronous mode offers the clock rate as 1, 16 or 64 times of
the baud rate as it is programmable.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
7. Modem Control: This unit of 8251 holds input and output control signals that simplify the
operation of the whole system. The control circuitry for handing various signals is provided by
the modem control unit. It includes DTS, RTS, DTR and CTS.
These are all active low signals.
• DSR: Stands for data set ready and the signal is used to check whether the data set is ready or
not when the processor is in the urge of communication.
• DTR: Implies data terminal ready. An active-low signal at this pin shows that the 8251 is now
ready to accept the data from the processor.
• RTS: It stands for the request to send. A low signal shows an assertion for data transmission.
• CTS: Clear to send. When 8251 receives a low signal at this pin then it clears all the data
present in the modem in order to allow further communication.

RS232C

Figure: DB-9 Male and Female Connector

Pin Description
1 Data carrier detect (DCD)
2 Received data (RxD)
3 Transmitted data (TxD)
4 Data terminal ready (DTR)
5 Signal ground (GND)
6 Data set ready (DSR)
7 Request to send (RTS)
8 Clear to send (CTS)
9 Ring indicator (Rl)

RS232 is an Interface and the protocol between DTE (data terminal equipment) and DCE (data
communication equipment) using serial binary data exchange. Here C is used for the current
version. Universal Asynchronous Data Receiver & Transmitter (UART), attached in a
motherboard, used in connection with RS232 for transmitting data to any serial device like
modem or printer from its DTE interface.

Figure: RS 232C
ELECTRICAL SPECIFICATIONS:
1. Voltages:
There can be two states in the signal level of RS232C pins.
• Mark state – It is the high bit which is represented by binary 1 and have negative
voltages. Its voltage limits for transmitting signal ranges from -5 to -15V. Its voltage
limits for receiving signals ranges from -3 to -25V.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
• Space state – It is the low bit which is represented by binary 0 and have positive
voltages. Its voltage limits for transmitting signal ranges from +5 to +15V. Its voltage
limits for receiving signals ranges from +3 to +25V.

2. Cables and Wires:

The maximum cable length for RS232C is equals to 15.24 meters or equal to the capacitance of
2500pF. Limits for the impedance of wires ranges from 3 ohms to 7 ohms.

3. Data and Slew rates:

Rate of data transmission through RS232C is up to 20Kbps. The rate of change in signal levels
i.e. slew rate is up to 30V/microsecond.

4. Current:
Maximum current rating is 3Amps at the maximum operating voltage of 250V AC.

WORKING OF RS 232C:

Figure: RS 232C Connection and Signals

RS232C requires 25 pins connector for connecting DTE and DCE. Here is the list of pins and
signals of RS232C and the connection between DTE and DCE using drivers and receivers.

An RS232 pinout 9 pin cable features nine pins:

1. Data Carrier Detect: After a data terminal is detected, a signal is sent to the data set that is
going to be transmitted to the terminal.
2. Received Data: The data set receives the initial signal via the receive data line (RxD).
3. Transmitted Data: The data terminal gets a signal from the data set, a confirmation that
there is a connection between the data terminal and the data set.
4. Data Terminal Ready: A positive voltage is applied to the data terminal ready (DTR) line, a
sign that the data terminal is prepared for the transmission of data.
5. Signal Ground: A return for all the signals on a single interface, the signal ground (SG) offers
a return path for serial communications. Without SG, serial data cannot be transmitted
between devices.
6. Data Set Ready: A positive voltage is applied to the data set ready (DSR) line, which ensures
the serial communications between a data terminal and a data set can be completed.

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Microprocessor & Microcontroller Unit-3: 16-bit Microprocessor and Peripheral devices
7. Request to Send: A positive voltage indicates the request to send (RTS) can be performed,
which means the data set is able to send information to the data terminal without
interference.
8. Clear to Send: After a connection has been established between a data terminal and a distant
modem, a clear to send (CS) signal ensures the data terminal recognizes that communications
can be performed.
9. Ring Indicator: The ring indicator (RI) signal will be activated if a modem that operates as
a data set detects low frequency. When this occurs, the data terminal is alerted, but the RI
will not stop the flow of serial data between devices.

HANDSHAKING:
Before the actual data transfer, signals are transmitted from DTE to DCE in order to make
connections by a process known as handshaking. Following is the sequence of signal
handshaking:
• Initially, the computer activates RTS signal to modem when a data is transferred from
computer to modem.
• Modem in turn activates the DCD and then the CTS gets activated.
• Computer then sends data on TXD. After the data transmission is completed, the computer
deactivates the RTS which causes the modem to deactivate CTS.

APPLICATIONS:
It is used in establishing communication between the computer and embedded systems.
1. Due to its lower costs, it plays a vital role in CNC machines and servo controllers
2. Some microcontroller boards and PLC machines uses RS232C.
3. RS232C ports are used to communicate in headless systems in the absence of any network
connection.
4. Many Computerized Numerical Control Systems are containing RS232C port.

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