Digital Design Using Verilog

always @(posedge clk) begin

Rc
: <2
5:2
1>

2S
EL
assign pcinc = pc + 4;
RA
on 1>

XA
ILLP JT
dOr
2
1
0
A M
tru
cti
Ins emory
6>
Rb
: <1
5:1 0 1

RA
2 WD WERF for (i=0; i < 31; i = i+1) begin
D 0:1 ter WE
3 00 : <2 gis
L4 Ra Re ile RD
2
SE PC SE
L 1 F
PC RA
WA A
WWA
1
1 RD
X5P:21> 0 JT EL
+4 BS
+ : <2
Rc >) 1
0
Z 15:0 Wr
XT(<
S
C: R/W
)
0 WD
1
XT
(C ory
EL em
4*S AS ta M
+4+ Z
B Da
PC RD
IRQ U Ad
r
gic AL
Lo A
ol
ntr
Co L
SE UF
N
PC SEL AL
2
RA L
E
AS
EL
BS SEL
WD FN EL
+4 WDS
AL
U PC 2
Wr 01
RF
WE EL
S
WA

,…
t,irq
se Inpu
lk,re t [3 1
c ( :0] m
beta em_
e l data
odu ;
m

If (done) $finish; e
dul
o
ndm
e

6.884 – Spring 2005 02/04/05 L02 – Verilog 1

 Hardware Description Languages

In the beginning designs involved just a few

gates, and thus it was possible to verify these
circuits on paper or with breadboards

6.884 – Spring 2005 02/04/05 L02 – Verilog 2

 Hardware Description Languages

As designs grew larger and more complex, designers

began using gate-level models described in a
Hardware Description Language to help with
verification before fabrication

6.884 – Spring 2005 02/04/05 L02 – Verilog 3

 Hardware Description Languages
When designers began working
on 100,000 gate designs, these
gate-level models were too low-
level for the initial functional
specification and early high-
level design exploration

6.884 – Spring 2005 02/04/05 L02 – Verilog 4

 Hardware Description Languages
Designers again turned to HDLs
for help – abstract behavioral
models written in an HDL
provided both a precise
specification and a framework
for design exploration

6.884 – Spring 2005 02/04/05 L02 – Verilog 5

 Advantages of HDLs
Allows designers to talk about what the hardware
should do without actually designing the hardware
itself, or in other words HDLs allow designers to
separate behavior from implementation at various
levels of abstraction

HDLs do this with

modules and interfaces

6.884 – Spring 2005 02/04/05 L02 – Verilog 6

 Advantages of HDLs
Allows designers to talk about what the hardware
should do without actually designing the hardware
itself, or in other words HDLs allow designers to
separate behavior from implementation at various
levels of abstraction

6.884 – Spring 2005 02/04/05 L02 – Verilog 7

 Advantages of HDLs
Allows designers to talk about what the hardware
should do without actually designing the hardware
itself, or in other words HDLs allow designers to
separate behavior from implementation at various
levels of abstraction

6.884 – Spring 2005 02/04/05 L02 – Verilog 8

 Advantages of HDLs
Allows designers to talk about what the hardware
should do without actually designing the hardware
itself, or in other words HDLs allow designers to
separate behavior from implementation at various
levels of abstraction

Processor Processor Processor

A B C

Network

Memory Memory
Bank Bank
A B

6.884 – Spring 2005 02/04/05 L02 – Verilog 9

 Advantages of HDLs
Allows designers to talk about what the hardware
should do without actually designing the hardware
itself, or in other words HDLs allow designers to
separate behavior from implementation at various
levels of abstraction
– Designers can develop an executable functional specification
that documents the exact behavior of all the components and
their interfaces

– Designers can make decisions about cost, performance,

power, and area earlier in the design process

– Designers can create tools which automatically manipulate

the design for verification, synthesis, optimization, etc.

6.884 – Spring 2005 02/04/05 L02 – Verilog 10

 A Tale of Two HDLs
VHDL Verilog
ADA-like verbose syntax, lots C-like concise syntax
of redundancy
Extensible types and Built-in types and logic
simulation engine representations
Design is composed of entities Design is composed of modules
each of which can have which have just one
multiple architectures implementation
Gate-level, dataflow, and Gate-level, dataflow, and
behavioral modeling. behavioral modeling.
Synthesizable subset. Synthesizable subset.
Harder to learn and use, DoD Easy to learn and use, fast
mandate simulation

6.884 – Spring 2005 02/04/05 L02 – Verilog 11

 We will use Verilog …
Advantages
– Choice of many US design teams
– Most of us are familiar with C-like syntax
– Simple module/port syntax is familiar way to organize
hierarchical building blocks and manage complexity
– With care it is well-suited for both verification
and synthesis

Disadvantages
– Some comma gotchas which catch beginners everytime
– C syntax can cause beginners to assume C semantics
– Easy to create very ugly code, good and consistent
coding style is essential

6.884 – Spring 2005 02/04/05 L02 – Verilog 12

 An HDL is NOT a
Software Programming Language
Software Programming Language
– Language which can be translated into machine instructions
and then executed on a computer

Hardware Description Language

– Language with syntactic and semantic support for modeling the
temporal behavior and spatial structure of hardware

module foo(clk,xi,yi,done);
input [15:0] xi,yi;
output done;

always @(posedge clk)

begin:
if (!done) begin
if (x == y) cd <= x;
else (x > y) x <= x - y;
end
end
endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 13

 Hierarchical Modeling with Verilog
A Verilog module includes a module name and an
interface in the form of a port list
– Must specify direction and bitwidth for each port

module adder( A, B, cout, sum );

A B input [3:0] A, B;
output cout;
output [3:0] sum;

adder // HDL modeling of

// adder functionality
cout sum
endmodule Don’t forget
the semicolon!

6.884 – Spring 2005 02/04/05 L02 – Verilog 14

 Hierarchical Modeling with Verilog
A Verilog module includes a module name and an
interface in the form of a port list
– Must specify direction and bitwidth for each port
– Verilog-2001 introduced a succinct ANSI C style portlist

module adder( input [3:0] A, B,

A B output cout,
output [3:0] sum );

// HDL modeling of 4 bit

adder // adder functionality

cout sum endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 15

 Hierarchical Modeling with Verilog
A module can contain other modules through
module instantiation creating a module hierarchy
– Modules are connected together with nets
– Ports are attached to nets either by position or by name

a b module FA( input a, b, cin

output cout, sum );
cin
// HDL modeling of 1 bit
cout FA // adder functionality

endmodule
c

6.884 – Spring 2005 02/04/05 L02 – Verilog 16

 Hierarchical Modeling with Verilog
A module can contain other modules through
module instantiation creating a module hierarchy
– Modules are connected together with nets
– Ports are attached to nets either by position or by name

A B
module adder( input [3:0] A, B,
output cout,
adder output [3:0] S );
cout S
FA fa0( ... );
FA fa1( ... );
FA fa2( ... );
FA fa3( ... );

FA FA FA FA endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 17

 Hierarchical Modeling with Verilog
A module can contain other modules through
module instantiation creating a module hierarchy
– Modules are connected together with nets
– Ports are attached to nets either by position

A B
module adder( input [3:0] A, B,
output cout,
adder output [3:0] S );
cout S
wire c0, c1, c2;
FA fa0( A[0], B[0], 0, c0, S[0] );
FA fa1( A[1], B[1], c0, c1, S[1] );
FA fa2( A[2], B[2], c1, c2, S[2] );
FA fa3( A[3], B[3], c2, cout, S[3] );
FA FA FA FA
endmodule
Carry Chain

6.884 – Spring 2005 02/04/05 L02 – Verilog 18

 Hierarchical Modeling with Verilog
A module can contain other modules through
module instantiation creating a module hierarchy
– Modules are connected together with nets
– Ports are attached to nets either by position or by name

A B
module adder( input [3:0] A, B,
output cout,
adder output [3:0] S );
cout S
wire c0, c1, c2;
FA fa0( .a(A[0]), .b(B[0]),
.cin(0), .cout(c0),
.sum(S[0] );

FA FA FA FA FA fa1( .a(A[1]), .b(B[1]),

...

endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 19

 Verilog Basics
Data Values Numeric Literals

4’b10_11
0 1 Underscores
X Z are ignored

Base format
(d,b,o,h)

Decimal number
representing size in bits

32’h8XXX_XXA3
6.884 – Spring 2005 02/04/05 L02 – Verilog 20
 3 Common Abstraction Levels

Module’s high-level algorithm is

Behavioral implemented with little concern
for the actual hardware

Module is implemented by
Dataflow specifying how data flows
between registers

Module is implemented in terms

Gate-Level of concrete logic gates (AND,
OR, NOT) and their
interconnections

6.884 – Spring 2005 02/04/05 L02 – Verilog 21

 3 Common Abstraction Levels

Designers can create

Behavioral lower-level models from
the higher-level models
either manually or
automatically

Dataflow The process of

automatically generating a
gate-level model from
either a dataflow or a
behavioral model is called
Gate-Level Logic Synthesis

6.884 – Spring 2005 02/04/05 L02 – Verilog 22

 Gate-Level : 4-input Multiplexer
module mux4( input a, b, c, d
input [1:0] sel,
output out );
Basic logic gates are built-in
wire [1:0] sel_b; primitives meaning there is no
not not0( sel_b[0], sel[0] ); need to define a module for
these gates
not not1( sel_b[1], sel[1] );

wire n0, n1, n2, n3;

and and0( n0, c, sel[1] );
and and1( n1, a, sel_b[1] ); sel[0]
and and2( n2, d, sel[1] );
and and3( n3, b, sel_b[1] );
sel[1]
wire x0, x1;
nor nor0( x0, n0, n1 ); c
nor nor1( x1, n2, n3 );
a
out
wire y0, y1; d
or or0( y0, x0, sel[0] );
or or1( y1, x1, sel_b[0] ); b

nand nand0( out, y0, y1 );

endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 23

 Dataflow : 4-input Multiplexer

module mux4( input a, b, c, d

input [1:0] sel,
output out );

wire out, t0, t1;

assign t0 = ~( (sel[1] & c) | (~sel[1] & a) );
assign t1 = ~( (sel[1] & d) | (~sel[1] & b) );
assign out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );

endmodule

This is called a continuous assignment

since the RHS is always being evaluated
and the result is continuously being
driven onto the net on the LHS

6.884 – Spring 2005 02/04/05 L02 – Verilog 24

 Dataflow : 4-input Multiplexer

module mux4( input a, b, c, d

input [1:0] sel,
output out );

wire t0 = ~( (sel[1] & c) | (~sel[1] & a) );

wire t1 = ~( (sel[1] & d) | (~sel[1] & b) );
wire out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );

endmodule
An implicit continuous assignment combines
the net declaration with an assign statement
and thus is more succinct

6.884 – Spring 2005 02/04/05 L02 – Verilog 25

 Dataflow : 4-input Mux and Adder
// Four input muxltiplexor
module mux4( input a, b, c, d
input [1:0] sel, Dataflow style Verilog
output out ); enables descriptions
which are more
assign out = ( sel == 0 ) ? a : abstract than gate-
level Verilog
( sel == 1 ) ? b :
( sel == 2 ) ? c :
( sel == 3 ) ? d : 1’bx;

endmodule

// Simple four bit adder

module adder( input [3:0] op1, op2,
output [3:0] sum );

assign sum = op1 + op2;

endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 26

 Dataflow : Key Points
Dataflow modeling enables the designer to focus
on where the state is in the design and how the
data flows between these state elements without
becoming bogged down in gate-level details
– Continuous assignments are used to connect
combinational logic to nets and ports

– A wide variety of operators are available including:

Arithmetic: + - * / % **
Logical: ! && || Avoid these
Relational: > < >= <= operators since
Equality: == != === !=== they usually
Bitwise: ~ & | ^ ^~ synthesize poorly
Reduction: & ~& | ~| ^ ^~
Shift: >> << >>> <<<
Concatenation: { }
Conditional: ?:

6.884 – Spring 2005 02/04/05 L02 – Verilog 27

 Dataflow : Key Points
Dataflow modeling enables the designer to focus
on where the state is in the design and how the
data flows between these state elements without
becoming bogged down in gate-level details
– Continuous assignments are used to connect
combinational logic to nets and ports

– A wide variety of operators are available including:

Arithmetic: + - * / % **
Logical: ! && ||
assign signal[3:0]
Relational: > < >= <=
= { a, b, 2’b00 }
Equality: == != === !===
Bitwise: ~ & | ^ ^~
Reduction: & ~& | ~| ^ ^~
Shift: >> << >>> <<<
Concatenation: { }
Conditional: ?:

6.884 – Spring 2005 02/04/05 L02 – Verilog 28

 Behavioral : 4-input Multiplexer
module mux4( input a, b, c, d
input [1:0] sel,
output out );

reg out;

always @( a or b or c or d or sel )
begin
if ( sel == 0 ) An always block is a behavioral
out = a;
block which contains a list of
else if ( sel == 1 )
out = b expressions which are (usually)
else if ( sel == 2 ) evaluated sequentially
out = c
else if ( sel == 3 ) The code in an always block can
out = d be very abstract (similar to C
end code) – here we implement a mux
with an if/else statement
endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 29

 Behavioral : 4-input Multiplexer
module mux4( input a, b, c, d
input [1:0] sel,
output out );

reg out;

always @( a or b or c or d or sel )
begin
if ( sel == 0 )
out = a;
An always block can include a
else if ( sel == 1 )
out = b
else if ( sel == 2 ) sensitivity list – if any of these
out = c signals change then the always
else if ( sel == 3 ) block is executed
out = d
end

endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 30

 Behavioral : 4-input Multiplexer
module mux4( input a, b, c, d
input [1:0] sel,
output out );

reg out;

always @( a, b, c, d, sel )
begin
if ( sel == 0 )
out = a;
else if ( sel == 1 )
out = b In Verilog-2001 we can use a
else if ( sel == 2 ) comma instead of the or
out = c
else if ( sel == 3 )
out = d
end

endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 31

 Behavioral : 4-input Multiplexer
module mux4( input a, b, c, d
input [1:0] sel,
output out );

reg out; What happens if we accidentally

leave off a signal on the
always @( a, b, c, d, sel ) sensitivity list?
begin
The always block will not
if ( sel == 0 )
out = a;
else if ( sel == 1 ) execute if just d changes – so if
out = b sel == 3 and d changes then
else if ( sel == 2 ) out will not be updated
out = c
else if ( sel == 3 )
out = d This will cause discrepancies
end between simulated and
synthesized hardware – there
endmodule are no sensitivity lists in real
hardware so it would work fine!

6.884 – Spring 2005 02/04/05 L02 – Verilog 32

 Behavioral : 4-input Multiplexer
module mux4( input a, b, c, d
input [1:0] sel,
output out );

reg out;

always @( * )
begin
if ( sel == 0 )
out = a;
else if ( sel == 1 )
out = b In Verilog-2001 we can use the
else if ( sel == 2 ) @(*) construct which creates a
out = c sensitivity list for all signals
else if ( sel == 3 )
read in the always block
out = d
end

endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 33

 Behavioral : 4-input Multiplexer
module mux4( input a, b, c, d
input [1:0] sel,
output out );

reg out;

always @( * )
begin
case ( sel )
0 : out = a; Always blocks can contain case
1 : out = b; statements, for loops, while loops,
2 : out = c; even functions – they enable
3 : out = d; high-level behavioral modeling
endcase
end

endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 34

 Behavioral : 4-input Multiplexer
module mux4( input a, b, c, d
input [1:0] sel,
output out );

reg out;
What about this funny No! and whoever
always @( * ) reg statement? decided on the reg
begin Is this how you create syntax really
case ( sel ) a register in Verilog? messed things up!
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
endcase
end

endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 35

 Behavioral : 4-input Multiplexer
module mux4( input a, b, c, d
input [1:0] sel,
output out );

reg out;
In Verilog a reg is just a variable –
always @( * ) when you see reg think variable not
begin hardware register!
case ( sel )
0 : out = a; Any assignments in an always block
1 : out = b; must assign to a reg variable – the
reg variable may or may not actually
2 : out = c;
3 : out = d;
endcase represent a hardware register
end
If the always block assigns a value to
endmodule the reg variable for all possible
executions then the reg variable is
not actually a hardware register

6.884 – Spring 2005 02/04/05 L02 – Verilog 36

 Behavioral : 4-input Multiplexer
module mux4( input a, b, c, d
input [1:0] sel,
output out );
What about in this
reg out;
situation? Will the
always @( * )
generated hardware
begin include a latch for out?
case ( sel )
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
endcase
end

endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 37

 Behavioral : 4-input Multiplexer
module mux4( input a, b, c, d
input [1:0] sel,
output out );
Maybe! What if sel == xx?
reg out;
Then out is unassigned and
always @( * )
the hardware must maintain
begin the previous value of out!
case ( sel )
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
endcase
end

endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 38

 Behavioral : 4-input Multiplexer
module mux4( input a, b, c, d
input [1:0] sel,
output out );
Fix it with a default clause
reg out;
in the case statement –
always @( * )
then no hardware latch is
begin inferred
case ( sel )
default : out = 1’bx;
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
endcase
end

endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 39

 Behavioral Non-Blocking Assignments
always @( posedge clk ) always @( posedge clk )
begin begin
x = next_x; x <= next_x;
end end

next_x D Q X next_x D Q X
clk clk

always @( posedge clk ) always @( posedge clk )

begin begin
x = next_x; x <= next_x;
y = x; y <= x;
end end

X X
next_x D Q Y next_x D Q D Q Y
clk clk clk

6.884 – Spring 2005 02/04/05 L02 – Verilog 40

 Behavioral Non-Blocking Assignments

always @( posedge clk ) always @( posedge clk )

begin begin
y = x; y <= x;
x = y; x <= y;
end end

X Y
D Q X

clk

Take Away Point - always ask

yourself “Do I need blocking or
non-blocking assignments for this D Q Y

always block?” clk

Never mix and match!

6.884 – Spring 2005 02/04/05 L02 – Verilog 41

 Which abstraction is the right one?
Designers usually use a mix of all three! Early on in
the design process they might use mostly behavioral
models. As the design is refined, the behavioral
models begin to be replaced by dataflow models.
Finally, the designers use automatic tools to
synthesize a low-level gate-level model.

Behaviora
l

Gat Dataflow
e-L
eve
l

6.884 – Spring 2005 02/04/05 L02 – Verilog 42

 Revisiting Logic Synthesis

Modern tools are able to

Behavioral synthesize more and more
behavioral Verilog code
directly to the gate-level

Dataflow The problem though, is

that it is very hard to
predict what the generated
hardware will look like
This makes it difficult to
Gate-Level perform rational design
space exploration

6.884 – Spring 2005 02/04/05 L02 – Verilog 43

 Revisiting Logic Synthesis

In this course we will

Behavioral mostly stick to very
predictable dataflow to
gate-level synthesis – we
want to have a good idea
what kind of hardware we
Dataflow are generating!

Gate-Level

6.884 – Spring 2005 02/04/05 L02 – Verilog 44

 Writing Parameterized Models
module mux4 #( parameter width )
( input [width-1:0] a, b, c, d
input [1:0] sel,
output [width-1:0] out );
...
endmodule

// Specify parameters at instantiation time

mux4 #( .width(32) )
alu_mux( .a(op1), .b(bypass), .c(32’b0), .d(32’b1),
.sel(alu_mux_sel), .out(alu_mux_out) );

Parameters enable static configuration of modules at

instantiation time and can greatly increase the
usefulness of your modules

6.884 – Spring 2005 02/04/05 L02 – Verilog 45

 Writing Parameterized Models
module adder #( parameter width )
( input [width-1:0] op1,op2,
output cout,
output [width-1:0] sum );

wire [width-1:0] carry;

assign carry[0] = 0;
assign cout = carry[width]

genvar i; Generate blocks can

use parameters to
generate
for ( i = 0; i < width; i = i+1 )
begin : ripple instantiate a variable
FA fa( op1[i], op2[i], number of sub-modules
carry[i], carry[i+1] ); or to create a variable
end number of nets
endgenerate

endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 46

 Static Elaboration

Model

Static Elaboration

Elaborated Model
Synthesis

Gate-Level

6.884 – Spring 2005 02/04/05 L02 – Verilog 47

 Larger Examples
Let’s briefly examine two larger digital designs
and consider the best way to model
these designs in Verilog

GCD Beta

6.884 – Spring 2005 02/04/05 L02 – Verilog 48

 GCD Behavioral Example
module gcd_behavioral #( parameter width = 16 )
( input [width-1:0] A_in, B_in,
output [width-1:0] Y );

reg [width-1:0] A, B, Y, swap;

integer done;

always @( A_in or B_in )

begin
done = 0;
A = A_in; B = B_in;

while ( !done )
begin
if ( A < B )
begin
swap = A;
We write the general
A = B; algorithm in an always block
using a very C-like syntax
B = swap;
end
else if ( B != 0 )
A = A - B;
else
done = 1;
end

Y = A;
end

endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 49

 GCD Behavioral
module gcd_test;
parameter width = 16;

Test Harness
reg [width-1:0] A_in, B_in;
wire [width-1:0] Y;

gcd_behavioral #( .width(width) )
gcd_unit( .A_in(A_in), .B_in(B_in), .Y(Y) );

initial
begin

// Default inputs if cmdline args We use a test harness to drive

// are not provided the GCD module. The test
harness includes an initial block,
A_in = 27;
B_in = 15;

// Read in cmdline args which is similar to always block

$value$plusargs("a-in=%d",A_in);
$value$plusargs("b-in=%d",B_in);
except it executes only once at
time = 0.
// Let the simulation run
#10;
Special directives which begin
// Output the results with $ enable the test harness
to read command line arguments,
$display(" a-in = %d", A_in );
$display(" b-in = %d", B_in );
$display(" gcd-out = %d", Y
$finish;
);
use file IO, print to the screen,
end
and stop the simulation
endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 50

 GCD RTL Example
go done
Control Unit

zero? lt out

A_in
A
sub

B_in
B
Design
Design Strategy
Strategy
Partition
Partition into
into control
control and
and datapath
datapath
Keep
Keep all
all functional
functional code
code in
in the
the leaf
leaf modules
modules

6.884 – Spring 2005 02/04/05 L02 – Verilog 51

 GCD RTL Datapath
module gcd_dpath #( parameter width = 16 )
( input clock,
input A_en, B_en, A_mux_sel, B_mux_sel, out_mux_sel,
input [width-1:0] A_in, B_in,
output B_zero, A_lt_B,
output [width-1:0] Y );

reg [width-1:0] A, B;
assign Y = A;

// Datapath logic
wire [width-1:0] out = ( out_mux_sel ) ? B : A - B;
wire [width-1:0] A_next = ( A_mux_sel ) ? out : A_in;
wire [width-1:0] B_next = ( B_mux_sel ) ? A : B_in;

// Generate output control signals

wire B_zero = ( B == 0 );
wire A_lt_B = ( A < B );
A mix of dataflow
and behavioral
// Edge-triggered flip-flops Edge-triggered
always @( posedge clock )
begin
flip-flops with
if ( A_en ) enables
A <= A_next;
if ( B_en )
B <= B_next;
end

endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 52

 GCD RTL Control Unit
module gcd_ctrl ( input clock, reset, go,
input B_zero, A_lt_B,
output A_en, B_en, A_mux_sel, B_mux_sel, out_mux_sel,
output done );

// The running bit is one after go goes high and until done goes high

reg running = 0;
always @( posedge clock )
begin
if ( go ) running <= 1;
else if ( done ) running <= 0;
end

// Combinational control logic - we group all the control signals

// onto one bus to make the Verilog more concise

reg [5:0] ctrl_sig;

assign { A_en, B_en, A_mux_sel, B_mux_sel, out_mux_sel, done } = ctrl_sig;

always @(*)
begin
if ( !running ) ctrl_sig = 6'b11_00x_0; // Latch in A and B values
else if ( A_lt_B ) ctrl_sig = 6'b11_111_0; // A <= B and B <= A
else if ( !B_zero ) ctrl_sig = 6'b10_1x0_0; // A <= A - B and B <= B
else ctrl_sig = 6'b00_xxx_1; // Done
end

endmodule

6.884 – Spring 2005 02/04/05 L02 – Verilog 53

 GCD Testing
We use the same test inputs to test both the
behavioral and the RTL models. If both models
have the exact same observable behavior then the
RTL model has met the functional specification.

Test Inputs

Behavioral RTL
Model Model

Identical
Outputs?

6.884 – Spring 2005 02/04/05 L02 – Verilog 54

 Beta Redux I thought I already did
6.004
ILL
XAdr OP JT

PCSEL 4 3 2 1 0

PC 00

A Instruction
Memory
+4 D

Ra: <20:16> Rb: <15:11> Rc: <25:21>

0 1 RA2SEL
+ WASEL

XP
RA1 Register RA2
1
WD
Rc: <25:21> WA
WA
File
0
RD1 RD2 WE WERF
Z
JT
C: SXT(<15:0>)
PC+4+4*SXT(C)
IRQ Z
ASEL 1 0 1 0 BSEL

Control Logic

PCSEL
RA2SEL A B
ASEL ALU WD R/W Wr
ALUFN
BSEL
WDSEL Data Memory
ALUFN Adr RD
Wr
WERF
WASEL
PC+4

0 1 2 WDSEL

6.884 – Spring 2005 02/04/05 L02 – Verilog 55

 Goals for the Beta Verilog Description
Readable, correct code that clearly
captures the architecture diagram – “correct by inspection”

Partition the design into regions appropriate for different

implementation strategies. Big issue: wires are “bad” since they
take up area and have capacitance (impacting speed and power).
– Memories: very dense layouts, structured wires pretty much route
themselves, just a few base cells to design & verify.
– Datapaths: each cell contains necessary wiring, so replicating cells (for N
bits of datapath) also replicates wiring. Data flows between columnar
functional units on horizontal busses and control flows vertically.
– Random Logic: interconnect is “random” but library of cells can be
designed ahead of time and characterized.
– Think about physical partition since wires that cross boundaries can take
lots of area and blocks have to fit into the floorplan without wasteful
gaps.

6.884 – Spring 2005 02/04/05 L02 – Verilog 56

 Hey! What happened to abstraction?
Because life is short! If you
have the luxury of writing two
Wasn’t the plan to models (the first to experiment
abstract-away the physical with function, the second to
details so we could describe the actual partition you
concentrate on getting the want to have), by all means! But
functionality right? Why with a little experience you can
are we worrying about wires tackle both problems at once.
and floorplans at this stage?

6.884 – Spring 2005 02/04/05 L02 – Verilog 57

 Divide and Conquer
ILL
XAdr OP JT

PCSEL 4 3 2 1 0 Step 1: identify memories

PC 00
1 Step 2: identify datapaths
A Instruction
Memory
What’s left is random logic …
D
+4

Ra: <20:16> Rb: <15:11> Rc: <25:21>

0 1 RA2SEL

2 + WASEL

XP 1
RA1 Register RA2
WD
1
PC
Rc: <25:21> WA
WA
File
0
RD1 RD2 WE WERF
Z
JT
C: SXT(<15:0>)
PC+4+4*SXT(C)
IRQ Z
ASEL 1 0 1 0 BSEL

Control Logic

PCSEL
RA2SEL A B
ASEL ALU WD R/W Wr
ALUFN
BSEL
WDSEL Data Memory
ALUFN Adr RD
Wr
WERF
WASEL
PC+4 1
0 1 2 WDSEL
2
Main Datapath
6.884 – Spring 2005 02/04/05 L02 – Verilog 58
 Take Away Points
Hardware description languages are an essential
part of modern digital design
– HDLs can provide an executable functional specification
– HDLs enable design space exploration early in design process
– HDLs encourage the development of automated tools
– HDLs help manage complexity inherent in modern designs

Verilog is not a software programming language so

always be aware of how your Verilog code will map
into real hardware

Carefully plan your module hierarchy since this will

influence many other parts of your design

6.884 – Spring 2005 02/04/05 L02 – Verilog 59

 Laboratory 1
You will be building an RTL model of a
two-stage MIPS processor
1. Read through the lab and the SMIPS processor
spec which is posted on the website
2. Look over the Beta Verilog posted on the website
3. Try out the GCD Verilog example in 38-301
(or on any Athena/Linux machine)
% setup 6.884
% cp –r /mit/6.884/examples/gcd .
% cat gcd/README

4. Next week’s tutorial will review the Beta

implementation and describe how to use Lab 1
toolchain (vcs, virsim, smips-gcc)

6.884 – Spring 2005 02/04/05 L02 – Verilog 60