Design Rules for Layout

1. DRC should be “ON” all the time during the layout.

2. Till the designer’s checklist is complete design is not complete.

3. Use following rules for the net name selection:

a. Test Board design:

i. Always use channel numbers as net names.
ii. Use Power supply numbers as net names (PS1, PS2…)
b. Speed Board (Bench Test) design:
i. Use DUT pin name as net name.
ii. Use Power supply numbers as net names (PS1, PS2…)

4. Power supply sense line connection:

a. Sense line for each power supply must be connected other wise the power
supply will not work.
b. Always connect sense trace at the corresponding DUT power pin.
c. Always use copper tie between sense pin and the Power supply pin.
d. Make sure to assign tie net names from both sides of the copper tie.
e. All the sense lines should be mitered also.

5. Ground sense line connection:

a. Always connect sense trace at the corresponding DUT GND pin.
b. Always use copper tie between sense pin and the GND pin.
c. All the sense lines should be mitered also.
d. Use 20 to 25-mil trace for GND sense.
e. Keep the trace length as short as possible.

6. Minimum Air gap between traces (Edge to Edge) should be as follows unless
specified:

a. Traces on outer layer: 5 X Trace Width (or more, if required by customer)

b. Traces on inner layer: 3 X Trace Width (or more, if required by customer)

Y x Trace width (Edge to Edge)

c. Minimum possible spacing is 4-mil (Special case, permission required

from Fab house)
7. For 100 Ω Differential Routing following example will apply unless otherwise
specified, actual numbers depend upon the layer stackup for that particular job:
a. Trace Width: 10 Mils
b. Space with in the pair edge to edge: 15 Mils ±0.5Mils
c. Space between two pairs will be same as rule # 6
15 Mils

Y x Trace
Width
d. Difference in length between two traces should not be more then ±5 Mils
e. Use Channel side for matching length
f. Use equal distance between point of separation of two traces and the
channel pin.

Channel
DUT Side

8. Bend Corners:
a. 90° turn vs round corners:

Preferred
Wrong Not Preferred

b. Small curves vs big curves:

Preferred
Not Preferred

9. Bends in a trace must not be too sharp to be close to 90’, see below:

10. Trace to Via pad gap (Edge to Edge) should be:

 a. As much as available (Preferred)
b. 5-mil (Minimum possible, worst case)
c. 4-mil (Special case, permission required from Fab house)

Max (Edge to Edge) 5 mils 4-mil

Preferred Minimum Special case

11. Via Pad to Via Pad gap (Edge to Edge) should be:

a. Maximum available (Preferred)

b. 5-mils (Minimum possible, worst case)

5 mils (Edge to Edge)

12. Running trace between two pads:

a. Route the trace at the center of two pads
b. Use equal distance on both sides

Wrong Correct

13. Annular ring for Plated holes:

a. 15-mil annular ring is standard, i.e. 7.5-mil pad thickness per side.
b. 5-mil annular ring in worst-case scenario i.e. 2.5-mil per side.
c. Lower than 5-mil require permission from fab house.

Note: When using minimum numbers it needs

1. Teardrop is allowed. 2. Locations are in the center of the board.

7.5-mil 2.5-mil

14. Annular ring for Non-Plated holes:

a. 10-mil annular ring is standard, i.e. 5-mil pad thickness per side.
Drill
Drill b. 5-mil annular ring in worst-case scenario i.e. 2.5-mil per side.
Standard Minimum
 c. Lower than 5-mil require permission from fab house.

5-mil 2.5-mil

Drill Drill
Minimum
Standard

15. For SMT Socket area, via should be placed exactly at the center of the grid area b/w
surface pads, as shown below. In case, the pitch is too small and via size can not be
made small enough to fit, use one of the following two options:

a. Place via next to the Pad as long as the edge of the Via Pad and the edge
of the other SMT pad is 5-mil apart.
b. If option “a” does not work then use an oval via. In this case, via drill must
not touch the surface pad.

Pad size; Min edge of pad to edge of pad is 5-mil

Follow rule#12 on either side of Drill

OPTION “A”

Pad size; Min edge of pad to edge of pad is 5-mil

Follow rule#12 on either side of Drill

OPTION “B”
16. A Trace must enter the pad/via perpendicular to the pad circumference, see below for
example:
 Correct Wrong

17. Distance b/w the segments of the same trace should also be maintained as specified in
point#6

18. Distance b/w the trace and pad of same net should be maintained as in point#9 and 11
until it connects to the pad, see below:

19. Signal trace must not overlap a gap boundary. Avoid crossing of trace over the gap
boundaries as much as possible. However, if it has to cross, it should cross
perpendicularly.
20. If a signal layer is next to an outer layer with copper pour, its traces should not lie
inside, overlap or cross the area with clearance in copper pour. This acts like a gap
boundary in plane layer.
21. If copper pour is connected to the surface pads of SMT components that need to be
soldered on the board, its connections must be defined as thermal. If it connects to
 thru-holes or surface pads where nothing is going to be soldered then make it Direct
connect.

22. In case of copper pour, use bigger line width and high backoff smoothness to keep
file size smaller

23. When there is a special swell in plane layers, make same cutouts in all Copper pours
also.

24. Copper pour should not flow under the SMP/SMA body where the footprint does not
have any copper.

25. When the vias in DUT area, pogo area or any other area are required to be filled with
Solder mask, those should not have any clearance in the respective mask layer (Top
or bottom) i.e. their properties in the respective mask layer should be zero (0).

26. Distance b/w the pads/vias of different supplies should be atleast 25-mil.
27. Distance b/w the pads/vias of a supply and GND should be atleast 30-mil.
28. Distance b/w GND pads/vias from GND pads/vias should be atleast 10-mil.

29. Distance b/w the traces of different supplies should be atleast 25-mil.
30. Distance b/w the traces of a supply and GND should be atleast 25-mil.

31. Connections must be evenly distributed among layers.

32. Standard Global swell is 10 mils (on each side) and it is off the drill size not the Pad
size. In any application if you need to add the clearance around the Drill the Pad size
will be enough to show the clearance on the signal layers, but for the Plane layers you
need to use proper swell to achieve the correct clearance and the Global swell can not
be used. This is extremely important specially, in case of Counter bore or counter
sink holes.

Plane

Swell
Drill

Board Thickness Standard Advanced R&D

Technology Technology
0.125” Thick Board 0.010” 0.008” 0.006”
0.185” Thick Board 0.011” 0.0096” 0.0075”
0.250” Thick Board 0.0125” 0.0105” 0.0085”

33. Line width depends upon the layer stackup. However, minimum line width that can
be used is mentioned below:

Copper Weight Minimum Width Special Case

(Worst case) (Require Permission from
fab)
½ OZ Copper 0.004” 0.003”
1 OZ Copper 0.004” 0.003”
2 OZ Copper 0.006” 0.006” (DUT area only)

34. Minimum Drill size for Unplugged or Plugged with epoxy solder mask plated holes
(Vias) with respect to the thickness of the board.

Board Thickness Standard Worst case Special case; R&D

Technology (Advanced (Permission
Technology) required from fab)
0.125” Thick or less 0.010” 0.008” 0.006”
0.187” Thick or less 0.014” 0.010” 0.006”
0.250” Thick or less 0.016” 0.013” 0.010”
Above 0.250” Check with Fab house

35. Minimum Drill size for the Conductive Filled plated holes (Vias) with respect to the
thickness of the board. (e.g. filled with silver)
 Board Thickness Standard Worst case Special case; R&D
Technology (Advanced (Permission
Technology) required from fab)
0.125” Thick or less 0.012” 0.008” 0.006”
0.187” Thick or less 0.014” 0.010” 0.008”
0.250” Thick or less 0.016” 0.014” 0.012”
Above 0.250” Check with Fab house

36. Board routing (Cutting) is done at the center of the outline provided in Board layer.
Minimum Tolerance in board outline route is +/- 5 mils. This requirement is
important when we have special cutouts or special routing on the board. Special
cutouts matter specially when there is some copper near the edge of the cutout and the
corners need to be sharp (not curve). Minimum arc diameter for board route is 31-mil
for a board as thick as 0.200”. Tolerance in the board routing outline is tabulated
below:
Board Thickness Standard Worst case Special case; R&D
Technology (Advanced (Permission
Technology) required from fab)
0.125” Thick or less 0.007” 0.006” 0.005”
0.185” Thick or less 0.010” 0.008” 0.007”
0.250” Thick or less 0.012” 0.010” 0.008”
Above 0.250” Check with Fab house

37. Minimum text size is 6 mils.

Standard Minimum
(Preferred) (Worst case)

38. Minimum spacing between any features (Not specified above): 5 mils.

39. Minimum thermal ties and sizes:

40. Before starting a design, first purge all vias and pads and modify the Plane definition
of the remaining according to point#22 such that outer diameter is atleast 7-mil
bigger than the inner diameter in plane layer and spoke width is 10-mil.

41. PCB PANEL SIZES Vs WORKING AREA

PANEL SIZE EDGE MIN. GAP WORKING COMMENTS

MARGIN B/W BOARDS AREA
REQUIRED REQUIRED
12” x 18” 1¼” 1¼” 10” x 16” SMALLEST
PANEL
15” x 18” 1¼” 1¼” 13” x 16”
18” x 18” 1¼” 1¼” 16” x 16”
21” x 26” 1¼” 1¼” 19” x 24”
26” x 35” 1¼” 1¼” 24” x 33” BIGGEST
PANEL, Need
Special Order

42. Always purge all unused via styles, pad styles and text styles at the end of design.
With that, when you open the PCB file in ASCII format, there should be no
error/warning messages shown, as they normally appear when the file is opened. This
reduces the file size by a huge proportion and makes a huge difference in the time to
open the file.

43. Unnecessary attributes should always be turned-off in PCB. Unnecessary attributes

include all those are not required in assembly drawing including part#, value, type,
manufacturer name etc.
44. Gaps (and polygons also) should not have unnecessary vertices because it makes
them complicated to modify and increase modification time specially when more than
one designers work on the same file. See the example below:

FAB INFO:

45. Restrictions with using two different Prepregs (dielectrics) in the layer stack-up of the
same board. Note that Cores of these materials can be in the same board but Prepregs
are restricted.

No mix of GTEK and FR4.

No mix of ARLON 25N and FR4.

TOP
CORE
GND
PRE PREG
INR1
CORE
GND
PRE PREG
PWR1
CORE
PWR2
PRE PREG
GND
CORE
INR2
PRE PREG
GND
CORE
BOTTOM

STANDARD FAB NOTES:

46. VIA PLUG

ALL THE VIA IN THIS AREA

NEED TO BE PLUGGED FROM
TOP/BOTTOM SIDE.

47. COUNTER SINK

Special Notes: Counter Sink 0.182” from Top/Bottom Side @82’.

48. PEM NUT

Special Notes: Install #8-32 from Bottom Side – Counter Bore: 0.349”, -Depth: 0.101”,
to be flushed to the bottom of the board.

49. Spacing and Trace width with Fine pitch sockets

For spacing and trace width when designing with a fine pitch socket, please refer to
the excel file “Spacing and Traces with Fine pitch sockets.xls”.