Linkedin_orsuvenkatakrishnaiah

Linkedin_orsuvenkatakrishnaiah
1.what logic is inferred when there are multiple assign statements targeting the same wire?
It’s not possible to specify multiple assign statements to the same wire in a Synthesizable code that will
become an output port of the module. The Synthesis tools give a syntax error that a net is being driven by
more than One source.
For an example:-
module multi_wire(input in1,in2,output temp);

assign temp=in1&in2;
assign temp=in1|in2;
endmodule

Note:-Only one type of output assignment is legal for synthesis

2.what do conditional assignments get inferred into?

• conditionals in a continuous assignment are specified through the “?:” operator. conditionals get inferred
into a multiplexor.

• for an example
module example2(input sel,a,b,output wire wire1);

assign wire1=(sel)?a:b;

endmodule
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3.what is the logic that gets synthesized when conditional operators in a single continuous assignment are
nested?

• The logic gets elaborated into a tree of multiplexors.

assign out1=(sel1)?a:sel2?b:sel3?c:d;

endmodule
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4. what value is inferred when multiple procedural assignments made to the same reg variable in an always
block?
• when there are multiple nonblocking assignments made to the same reg variable in a sequential always block, then the last assignment is picked up
for logic synthesis.
• for an example
module example4(input clk,a,b,output out2);
reg temp;
always@(posedge clk)begin
temp<=a^b;
temp<=a|b;
temp<=a&b;
end
assign out2=temp;
endmodule
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5.why should a nonblocking assignment be used for sequential logic, and what would happen if a blocking
assignment were used?
• In Verilog, nonblocking assignments (<=) should be used for sequential logic because they allow for
concurrent execution of multiple assignments within the same always block, which is necessary for correct
behavior of sequential circuits.
• If a blocking assignment (=) were used instead of a nonblocking assignment in a sequential always block, it
would cause a race condition where the order of execution of the assignments would be determined by the
order of the statements in the always block. This can lead to unpredictable behavior and incorrect results in
the circuit.
• In a sequential always block, the output signals are usually dependent on the current state of the circuit
and the inputs. Nonblocking assignments allow for the output signals to be updated independently of the
order of the statements in the always block and ensure that the output signals are updated consistently
with the current state of the circuit.
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6.Compare above question with the same code in a combinatorial block.

• In a combinatorial block, blocking assignments (=) are typically used to assign values to the output signals because
the outputs are updated directly from the inputs without any clock or state dependencies.
• In a combinatorial block, the order of execution of the statements is not important, as all the statements are
evaluated simultaneously. Therefore, there is no risk of race conditions that can occur with blocking assignments
in a sequential block.
• If a nonblocking assignment (<=) were used in a combinatorial block, it would not necessarily cause any issues or
errors, but it would be unnecessary and could potentially confuse other designers who are reviewing or modifying
the code.
• Overall, the use of blocking assignments in a combinatorial block is appropriate and preferred because it reflects
the nature of the combinatorial logic and avoids any confusion or unnecessary complexity. In contrast,
nonblocking assignments are typically used in sequential blocks to ensure correct behavior and avoid race
conditions.
 7. what are the differences between continuous and procedural assignments?
• Continous Assignments
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• Assigns values primarily to nets
• Variables and nets Continuosly drive values onto ports
• Used to infer Combinational logic
• Assignment occurs whenever the value on the RHS of the expression changes as a continuous
process
• Occurs in assignments to wire,port and net type.
• For an example
module example5(input in1,in2,output out1);
assign out1=in1&in2;
endmodule
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• Procedural Assignments
• Assigns values primarily to Reg variables
• Variables and nets can stores into variables
• Used to infer both storage elements like Sequential logic circuits and Combinational logic
• The value of the previous assignment is held until another assignment is made to the variable.
• Occurs in constructs like always,initial,task and function
• For an example
module example51(input clk,in1,output reg reg1);
always @(posedge clk)
reg1<=in1;
endmodule
8.What are the differences between assignments in initial and always constructs?
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• In Verilog, `initial` and `always` constructs are used to specify the behavior of the circuit.
• The main differences between assignments in `initial` and `always` constructs are:
• 1. Timing:
• - The `initial` block is executed only once at the beginning of simulation time, while the `always` block is executed continuously based on the
sensitivity list or trigger event.
• - The `initial` block is used to initialize the circuit's variables and registers with specific values at the start of simulation, while the `always` block is
used to describe the behavior of the circuit during its operation.
• 2. Sensitivity list or trigger event:
• - The `always` block may have a sensitivity list or a trigger event that specifies when the block should be executed. The sensitivity list or trigger event
indicates the changes in input signals that should cause the block to be executed.
• - In contrast, the `initial` block does not have a sensitivity list or trigger event as it is executed only once at the beginning of simulation time.
• 3. Blocking and Nonblocking assignments:
• - Nonblocking assignments (`<=`) are typically used in `always` blocks to ensure correct behavior of sequential logic and avoid race conditions.
• - In `initial` blocks, blocking assignments (`=`) are usually used to initialize variables and registers with specific values at the start of simulation.
9.What are the differences between blocking and nonblocking assignments?
• In Verilog, there are two types of assignments: blocking (`=`) and nonblocking (`<=`) assignments. The main differences between them are:
• 1. Order of execution:
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• - Blocking assignments are executed in the order they appear in the code. Once a blocking assignment is executed, the next assignment
can be executed.
• - Nonblocking assignments, on the other hand, are executed concurrently, regardless of their order in the code. All nonblocking
assignments in an always block are executed simultaneously, and the order in which they appear in the code does not matter.
• 2. Timing control:
• - In a combinational logic block, blocking assignments are used to assign values to the output signals as the output values are updated
immediately based on the input signals.
• - In a sequential logic block, nonblocking assignments are used to update the state of the circuit's registers, as the output values depend
on the current state of the circuit and the input signals. Nonblocking assignments ensure that the state of the circuit is updated
consistently with the current state.
• 3. Behavior in simulation:
• - In a simulation, blocking assignments cause a delay in the execution of the next statement, which can cause a time-consuming
simulation.
• - Nonblocking assignments do not cause delays in the execution of subsequent statements, and therefore, they are more efficient in
simulation.
10.How can I model a bi-directional net with assignments influencing both source and destination?

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• The assign statement constitutes a continuous assignment. The changes On the RHS of the
statement immediately reflect on the LHS net. However,Any changes on the LHS don't get
reflected on the RHS.

• For example, changes to the rhs net will update the lhs net, but not Vice versa.
wire lhs,rhs;

assign lhs=rhs;