Microprocessors

GATE & ESE

Disclaimer: The content provided herein is created and owned by a third-party service
provider and licensed to the Company. The Company disclaims all rights and liabilities
in relation to the content. The author of the content shall be solely responsible towards,
without limitation, any liabilities, damages, or suits which may arise with respect to the
same. The content contained herein is copyright protected and any unauthorised use or
distribution is not allowed.

2
Contents
Chapter 1 Introduction to Microprocessors & Microcontroller 05 - 16
Chapter 2 The 8085 Microprocessors 17 - 28
Chapter 3 8085 Interrupts 29 - 37
Chapter 4 Instruction Set of Microprocessors 8085 39 - 76
Chapter 5 8085-Timing Diagrams 77 - 101
Chapter 6 Memory and I/O Interfacing 103 - 110
Chapter 7 DMA (Direct Memory Access 111 - 122
Chapter 8 8086 Microprocessor 123 - 136

3
4
 Introduction to Microprocessors & Microcontroller

Chapter 1
Introduction to Microprocessors
& Microcontroller
Objective
Upon completion of this chapter, you will be able to:
• Understand the basics of Microprocessors & Microcontrollers
• Understand Microprocessors and their architecture and operation
• Types of Microcontrollers
• Operations Performed by Microprocessors

Introduction
Microprocessor is regarded as one of the most important devices in our everyday
machines called computers. It is an electronic circuit that functions as the central
processing unit (CPU) of a computer, providing computational control. It is also used in
other advanced electronic systems, such as computer systems, printers.
A Microprocessor incorporates arithmetic and logic functional units as well as the
associate control logic, instruction processing circuitry and a portion of the memory
hierarchy. It is a semiconductor component designed by using VLSI technology and
includes ALU, CU (control unit), and the resistor of the CPU in a single package.

Computer

CPU (MP)

ALU
I/P O/P
CU
Devices Devices
Resgister

Memory

5
 Introduction to Microprocessors & Microcontroller

A microprocessor is a multi-purpose, programmable clock driven register and ALU

(arithmetic and logic unit) based electronic device. It reads binary instructions from a
storage device called memory, accepts binary data as an Input, processes data according
to the instructions read, and provides results as an output. It is just like the human
brain. The brain get input from the ears and eyes and sends processed information to
output devices such as the hands, legs or the face with specific expressions.
• Memory is outside the CPU i.e., memory is not a part of the CPU
• Resistor present inside the CPU is not used as memory

Note:
• For a microprocessor, memory is connected externally
• Busicom (Japan) is the first company to design a calculator by using discrete ALU,
CU and memory
• After Busicom, Intel designed a microprocessor in a single package
• 1st microprocessor, 1971 → Intel 4004 → 4-bit
• Bit → Binary digit (0 or 1)
• Nibble → 4-bit
• Byte → 8-bits
• Word length → Depends on type of processor

Microcontroller
A microcontroller is an integrated chip that is often part of an embedded system.
The microcontroller includes a CPU, ROM, RAM, I/O ports, and a Timer like a standard
computer but because these are designed to execute only a single specific task to
control a single system, they are much smaller and simplified so that they can include all
the functions required on a single chip. Microcontrollers are sometimes called embedded
microcontrollers, which just means that they are part of an embedded system that is one
part of a larger device or system. Microcontrollers have become common in various areas
and are found in home appliances, computer equipment and instrumentations. These are
most used in automobiles and have become a central part of industrial Robotics.

Micro-Controller

ALU
Timer/
CU Memory
Counter
Resgister

Interfacing
Circuits

6
 Introduction to Microprocessors & Microcontroller

Different Types of Microcontrollers

Microcontrollers can be classified on the basis of internal bus width, architecture,
memory and instruction set.

Microcontrollers

Bits Memory/devices Instruction set Memory architecture

4 8 16 32 Embedded External CISC RISC Princeton Harvard

Family

8051 Motorola PIC Texas National ARM Others

Intel Atmel Dallas Phillips Siemens

Types of microcontrollers

(1) Microcontroller Based on Bit Size

Microcontrollers are available in bit sizes like 8 bit, 16 bit, and 32 bit. 8 bit
microcontrollers are Intel 8051, Atmel AT89C2051, PIC microcontroller are available in
both 8, 16 and 32 bit. 32 bit Tricor microcontrollers from Infineon.

4 bit 6 bit 16 bit 32 bit

Hitachi HMCS40 Intel 8051 Intel 8096 ARM9TM

Toshiba TLCS47 National COP820 National: HPC16164 IBM PowerPC 750TM
PID
National COP 420 Rockwell 6500/1 Hitachi: H8/532 MCORE MMC2001

OKI: MSM6411 Zilog Z8 M683XX family

TMS1000 Motorola 68HC11

Signetics: 87c552

(2) Microcontroller Based on Memory/Device

Based on memory/devices, microcontrollers are available in two formats, embedded
microcontroller and external memory microcontroller. When the entire hardware
is embedded into a microcontroller to run the desired application, then it is called
an embedded microcontroller. Such a microcontroller which can address external
memory is called an external memory microcontroller.

7
 Introduction to Microprocessors & Microcontroller

(3) Microcontroller Based on Instruction Set

According to the instruction set, two types of microcontrollers have been
reported with RISC architecture and CISC architecture. For example, CISC based
microcontrollers are Motorola 68HCXX, Intel 80x86 and RISC based microcontrollers
are SPARC from Sun, IBM Power PC 601, 604 and Motorola MPC 620.

(4) Microcontroller Based on Memory Architecture

Princeton response was a computer that had common memory for storing the
control program as well as variable and other data structures. It was best known
by the chief scientist’s name, “Von Neumann”. In contrast, Harvard’s response was a
design that used separate memory banks for program storage, the processor stack,
and variable RAM. PIC microcontrollers from Microchip are examples of Harvard
architecture.

ALU
Control Unit

ALU
Input Output Instruction Control Data Memory
CPU Memory Unit

Memory Unit
I/O

Von Neumann Model Harvard Model

(5) Microcontroller Based on Family/Manufacturer

Different vendors are available in the market with different architecture and
instruction sets like Intel, Atmel, Dallas, Philips, Siemens, Motorola.
Some other popular microcontrollers are:
Hitachi H8x family
Samsung SAM8
Mitsubishi 740
National Semiconductor COP8 and CR16.

Applications of Microcontrollers
Microcontrollers can be used to complete any task by interfacing sensors, actuators,
motors & appliances, etc. They are used in embedded systems-based applications
to control a specific task automatically. Following are some of the applications of
microcontrollers;
• Smart phones & handheld mobile devices
• Automobiles

8
 Introduction to Microprocessors & Microcontroller

• Cameras
• Appliances
• Fire detection, security alarms & safety devices (including temperature & smoke
sensing)
• Electronic Measurements Instruments
• Domestic appliances such as microwave oven, alarm clock, washing machines, air
conditioners
• Industrial automation (conveyor belts, sorting, pick & place bots, etc.)
• Industrial Instrumentation & measurement devices such as volt & current meter,
object detection, inspection & sorting devices
• Communication devices

Embedded System
“Embedded Systems are devices which are used to control, monitor or assist the
operation of an equipment, machinery or plant”. The term “control” defines the main
function of an Embedded System because its purpose is to control an aspect of a
physical system such as pressure, temperature and so on. Also, the term “monitor”
defines the progress of activities. Where do we use Embedded Systems? Due to the
several examples listed earlier, these systems are extremely common in the home,
vehicles and in the workplace.
At Home: Washing machines, dishwashers, ovens, central heating system, burglar alarms,
etc.
In Motor Vehicles: Engine management, security (locking or anti-theft devices), air
conditioning, brakes, radio, etc.
In Industry and Commerce: Machine control, factory automation, robotics, electronic
commerce office equipment.

Embedded system

Software

Application Embedded OS

Input Output

Hardware

Embedded Peripheral
microprocessor device

9
 Introduction to Microprocessors & Microcontroller

Comparison Between Microprocessor & Microcontroller

Microprocessor Microcontroller

• It contains ALU, CU and Resistors • It contains ALU, CU and Resistors

• No internal memory • Contains internal memory

• Contains interfacing circuits, Timer /
• No interfacing circuits, Timer/Counter
Counters
• Used for general purpose • Used for specific purpose

Application Application

E.g.: Intel 8085, 8086, M6800, Z80, i3, i7 E.g.: Intel 8051, 8031, PIC-8 bit/ 16 bit

Microprocessor Architecture and its Operations

Microprocessor Architecture
Figure (1) and Figure (2) show the block diagram and programmers model of a
microprocessor. The microprocessor’s block diagram and the microprocessor
programming model show you how a specific microprocessor is constructed. The block
diagram shows the microprocessor’s functions for data processing and data handling. It
also shows how each of these logic functions are connected together. The programming
model assists you in the programming process. The difference is that the programming
model shows only those parts of the microprocessor which the programmer can change.
So we can say that the block diagram makes it easier to understand the architecture
of the microprocessor and the programming model makes it easier to understand the
working of the microprocessor in a programming environment.

Block Diagram of Microprocessor

8-bit
internal
data bus
Status Instruction
Temp
register register

Register
IN
A OUT file
L
U SP
IN Instruction
detector PC
Memory
Control Logic address
register

16-bit
Address
External input and output control lines Bus

Block diagram of microprocessors

10
 Introduction to Microprocessors & Microcontroller

B7 B0 B7 B0

Accumulator (A) Status Reg.

Reg B. Reg C.

Reg D. Reg E.

Reg H. Reg L.

Stack Pointer(SP)

Program Counter(PC)
B15 B0
Programmer's model / Register file

The block diagram shown in Fig. 1 includes three major logic devices.
• ALU
• Several registers / register file
• Control unit
The internal data bus is used to transmit data between these logic devices.

ALU
ALU (Arithmetic and Logic Unit) performs arithmetic and logic operations such as ADD,
SUBTRACT, AND, OR, NOT, etc.

Registers
Registers are a prominent part of the block diagram and the programming model of
any microprocessor. Basic registers found in most of the microprocessors are the
accumulator, the program counter, the stack pointer, the status register, the general
purpose registers, the memory address register, the instruction register and the
temporary data registers.

The Accumulator
The accumulator is the major working register of a microprocessor. Most of the time it
is used to hold the data for manipulation. Whenever the operation processes two words,
whether arithmetically or logically, the accumulator contains one of the words. The other
word may be present in another register or in a memory location. Most of the times the
result of an arithmetic or logical operation is placed in the accumulator. In such cases,
after execution of the instruction, the original contents of the accumulator are lost
because they are overwritten.
The accumulator is also used for data transfer between an I/O port and a memory
location, or between one memory location and another.

11
 Introduction to Microprocessors & Microcontroller

The Program Counter

The program counter is one of the most important registers in the microprocessor. As
mentioned earlier, a program is a series of instructions stored in the memory. These
instructions tell the microprocessor exactly how to solve a problem. It is important that
these instructions must be executed in the proper order to get the correct result. This
sequence of instruction execution is monitored by the program counter. It keeps track of
which instruction is being used and what the next instruction will be.
The program counter gives the address of the memory location from where the next
instruction is to be fetched. Due to this, the length of the program counter decides
the maximum program length in bytes. For example, a microprocessor that has a 16 bit
program counter, can address 210 bytes (64K) of memory.
Before the microprocessor can start executing a program, the program counter has to be
loaded with a valid memory address. This memory location must contain the opcode of
the first instruction in the program. In most of the microprocessors this location is fixed.
For example, memory address (0000H) for a 16 bit program counter. The fixed address 5
is loaded into the program counter by resetting the microprocessor.
The instructions must be executed in a proper order to get the correct result. This does
not mean that every instruction must follow the last instruction in the memory. But It
must follow the logical sequence of the instructions. In some situations, it is better to
execute part of a program that is not in sequence (don’t confuse with logical sequence)
with the main program. For example, there may be a part of a program that must be
repeated many times during the execution of the entire program. Rather than writing the
repeated part of the program again and again., the programmer can write that part only
once. This part is written separately. The part of the program which is written separately
is called subroutine.
This figure shows how the main and subroutine programs are executed.

Main program Subroutine program

Part of the
Subroutine call program to
be repeated

Return to instruction after

subroutine call
Subroutine call

Excution of subroutine programs

The program counter does the most in subroutine execution as it can be loaded with
the required memory address. With the help of instructions, it is possible to load any
memory address in the program counter. When the subroutine is to be executed, the
program counter is loaded with the memory address of the first instruction in the
subroutine. After execution of the subroutine, the program counter is loaded with the
memory address of the next instruction from where the program control was transferred
to the subroutine program.

12
 Introduction to Microprocessors & Microcontroller

The Status Register

The status register is used to store the results of certain conditions when certain
operations are performed during execution of the program. The status register is also
referred to as the flag register. ALU operations and certain register operations may
set or reset one or more bits in the status register. Status bits lead to a new set of
microprocessor instructions. These instructions permit the execution of a program to
change flow on the basis of the condition of bits in the status register. So, the condition
bits in the status register can be used to take logical decisions within the program.

The Stack Pointer

This is an important register which programmers use frequently. In the earlier sections
we have seen how subroutines are executed by changing the program counter contents.
But one question you may have in your mind is how the program counter is loaded with
the address of the next instruction (return address) from where the program control was
transferred to the subroutine. This return address is kept in a special memory area called
the stack. Before transferring the program control to the subroutine the return address
is pushed onto the stack. After the execution of subroutine the return address is popped
off from the stack and loaded into the program counter.
The memory address of the stack area is given by a special register called the stack
pointer. Like the program counter, the stack pointer automatically points to available
location in the memory. In most microprocessors, the stack pointer decrements (points
to the next lower memory address) when data is pushed on the stack. This allows the
programmer to build the stack down in memory as shown in the Fig. 1.2.3. Usually stack
operations are 2 byte operations. This means that the stack pointer decrements by two
memory address locations each time when 2 byte data is pushed on the stack. When
the data is popped off from the stack, the stack pointer is incremented by two memory
address locations.

27FB E SP

27FC D

27FD C

27FE B

27FF A

Stack operation

It is important to note that as you go on storing (pushing) data on the stack, the stack
pointer always points the last data placed on the stack and when you try to remove
(pop) data you always get the last data placed on the stack. This kind of stack operation
is called LIFO (Last In First Out) operation.

13
 Introduction to Microprocessors & Microcontroller

General Purpose Registers

In addition to basic registers, most microprocessors have other registers called general
purpose registers. The general purpose registers are used as simple storage area, mainly
these are used to store intermediate results of the operation. Getting the operand from
the general purpose registers is faster than getting it from memory, so it is better to have
a sufficient number of general purpose registers in the microprocessor.

Memory Address Register

The memory address register gives the address of the memory location that the
processor wants to use. If memory address register holds 16-bit binary number, the
output of the memory address register drives the 16-bit address bus. This output is used
to select a memory location out of 216 (65536) memory locations.

The Instruction Register

The instruction register holds the operation code (opcode) of the instruction that the
microprocessor is currently executing. The instruction register is loaded during the
opcode fetch cycle. The contents of the instruction register are used to drive the part of
the control logic known as the instruction decoder.

Temporary Data Register

The need for the temporary data registers arises because the ALU has no storage of its
own. The ALU has two inputs. One input is supplied by the accumulator and other by the
temporary data register. The programmer cannot access this temporary data register and,
therefore it is not a part of the programming model.

Control Logic
The control logic is an important block in the microprocessor. The control logic is
responsible for the working of all other parts of the microprocessor together. It
maintains synchronization in the operation of different parts in the microprocessor. The
synchronization is achieved with the help of one of the control logic’s major external
inputs which is the microprocessor’s clock. The clock is a signal which is the basis of all
the timings inside the microprocessor.
Usually, the microprocessor’s control logic is micro programmed. This means that the
architecture of the control logic itself is much like the architecture of a very special
purpose microprocessor.
The control logic receives the signal from the instruction decoder which decodes the
instruction stored in the instruction register. The control logic then generates the control
signals necessary to carry out this instruction. The control logic does a few other special
functions. It looks after the microprocessor power-up sequence. It also processes
interrupts. An interrupt is like a request to the microprocessor from other external
devices such as the memory and I/O. The interrupt asks the microprocessor to execute a
special program.

14
 Introduction to Microprocessors & Microcontroller

Internal Data Bus

The internal data bus connects the different parts of the microprocessor together and
enables communication between these parts. The data transfer through this internal data
bus is controlled by control logic.
The microprocessor’s internal data bus is usually connected to an external data bus.
Due to this, the microprocessor can communicate with external memory or I/O devices.
Usually, the internal data bus is connected to the external data bus by logic called the
bi-directional bus (transceiver).

Operations Performed by Microprocessor

The operations performed by microprocessors can be classified into three groups:
• Internal operations
• Operations initiated by microprocessor
• Operations initiated by external devices

Internal Operations
The microprocessor has to perform various internal operations to process data. These
operations are:
(1) Decode the instruction and generate appropriate control signals for the execution
of the instruction
(2) Perform arithmetic and logical operations
(3) Execute the instructions in sequence by properly updating the contents of the
program counter
(4) Update and store the status information in the form of flags after execution of
specific instructions
(5) Manipulate the stack pointer for the implementation of stack memory
(6) During arithmetic or logical operation, loading of second operand in the TEMP
register

Von-Neumann Architecture Harvard Architecture

Memory Memory Memory

Program
& Program Data
Data

• Program & data both are present • Program and data are separately
in same memory present in different memory

• E.g.: Intel 8085, Intel 8086 (MP) • E.g.: Intel 8051 (MC)

15
 Introduction to Microprocessors & Microcontroller

(7) To test the flag status during the conditional branches

(8) To check existence of any activated interrupt after each instruction execution
(9) To check any active DMA request after each machine cycle

Operations Initiated by Microprocessor

To communicate with external devices or with memory, microprocessor performs
primarily four operations:
(1) Reads data or instruction from the memory
(2) Writes data into the memory
(3) Reads data from input devices
(4) Writes data into the output devices

Operations Initiated by External Devices

External devices can initiate the operation by activating Reset, Interrupt, READY or HOLD
pins of the microprocessor. These operations are:
(1) After activation of Reset pin, suspend all internal operations and clear program
counter so that it can fetch the next instruction from - the predefined memory
address
(2) After activation of any interrupt pin, execute a specific sequence of instructions
called the interrupt service routine and, after completion, resume its interrupted
operation
(3) After activation of the READY pin, extend the machine cycle until the activation of
the Ready pin to interface with the slower devices
(4) After activation of the HOLD pin, relinquish the control of buses and allow the
external controller to use them

Depending on the Program and Data Storage Technique, Two Techniques are Used
(1) Von-Neumann Architecture (Princeton Architecture)
(2) Harvard Architecture

16
 The 8085 Microprocessors

Chapter 2
The 8085 Microprocessors
Objective
Upon completion of this chapter you will be able to:
• Understand the features of 8085 Microprocessors
• Architecture of 8085
• Functional description of 8085 PIN Diagram

Introduction
The 8085 microprocessor is an 8-bit microprocessor suitable for a wide range of
applications. It is a single-chip, NMOS device implemented with approximately 6200
transistors on a 164 × 222 mil chip contained in a 40-pin dual-in-line package.

The Features of 8085 Include

(1) It is an 8-bit microprocessor i.e., it can accept, process, or provide 8-bit data
simultaneously
(2) It operates on a single +5V power supply connected at Vcc power supply, and
ground is connected to Vss
(3) It can operate with 3MHz clock frequency. The 8085 A-Z version can operate at the
maximum frequency of 5MHz
(4) It has 16-bit address lines, hence it can access (216) 64kB of memory
(5) It provides 8-bit I/O addresses to access (28) 256 I/O ports
(6) In 8085, the lower 8-bit address bus (A0 − A7) and data bus (D0 − D7) are
multiplexed to reduce the number of external pins. But due to this, an external
hardware (latch) is required to separate address lines and data lines
(7) It supports the instructions with the following addressing modes:
(a) Immediate
(b) Register
(c) Direct
(d) Indirect
(e) Implied
(8) It has an 8-bit accumulator, flag register, instruction register, six 8-bit general
purpose registers (B, C, D, E, H and L) and two 16-bit registers (SP and PC).
Fetching the operand from the general purpose registers is faster than from the
memory. Hence, skilled programmers always prefer general purpose registers to
store program variables over memory

17
 The 8085 Microprocessors

(9) It provides five hardware interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR
(10) It has a serial I/O which allows serial communication
(11) The external hardware (another microprocessor or equivalent master) can detect
which machine cycle the microprocessor is executing using status signals
(IO/ M , S0, S1). This feature is very useful when more than one processor is using
common system resources (memory and I/O devices)

Architecture of 8085
It consists of various functional blocks as listed below:
• Registers
• Arithmetic and Logic Unit
• Instruction decoder and machine cycle encoder
• Address buffer

RST RST RST

INTR 5.5 6.5 7.5 TRAP SOD SID
INTR

Interrupt Control Serial I/O control

Internal Data Bus

Accumulator Temporary Instruction

Flags (5) W (8) Z (8)
(8) Reg. (8) Reg. (8)
B (8) C (8)

D (8) E (8)
Instruction
Decoder H (8) L (8)
ALU and Stack pointer
Machine 16
cycle Program counter
Encoder 16
Increment/Decrement
Address Latch
Crystal oscillator
X1 Timing & Control
Status DNA Add.Buffer Add/Data
X2

Ready ALE RD WR IO/M S1 S0 Hold HLDA Reset in Reset out Clock out A15 − A8 AD7 − AD0

Architecture of 8085

18
 The 8085 Microprocessors

Arithmetic Logic Unit (ALU)

The ALU performs the actual numerical and logic operations such as ‘add’, ‘subtract’,
‘AND’, ‘OR’, etc. It uses data from memory and Accumulator to perform operations. It is
a combination of accumulator, temporary register, flag register and arithmetic & logic
circuit. The arithmetic unit performs bitwise fundamental arithmetic operations such as
addition and subtraction. The ALU also look after the branching decisions.
Always stores result of the operation in the Accumulator.

Register
The 8085 microprocessor includes six registers, one accumulator, and one flag register,
as shown in the Figure. In addition, it has two 16-bit registers: the stack pointer and the
program counter.
There are two types of registers.
(a) General purpose resistor
(b) Special purpose resistor

General Purpose Resistor

• There are 6-eight bit general purpose resistors which are → B, C, D, E, H, L
• There are three 16-bit general purpose resistors which are → BC, DE, HL (Resistor
pair)
• Any of the resistor pairs can be used to point to the memory. But HL pair is known
as the defined memory pointer

Example: MOV C, M
Here ‘M’ indicates memory contained or resistor whose address is present in HL pair
only.

Special Purpose Resistor

Accumulator (A)
The accumulator is an 8-bit register that is a part of an arithmetic/logic unit (ALU). This
register is used to store 8-bit data and to perform arithmetic and logical operations. The
result of an operation is stored in the accumulator. The accumulator is also identified as
register A.

Program Counter (PC)

It is a 16-bit register which deals with sequencing the execution of instructions. This
register is a memory pointer. Memory locations have 16-bit addresses, and that is why
this is a 16-bit register.

19
 The 8085 Microprocessors

The function of the program counter is to point to the memory address from which
the next byte is to be fetched or the program counter contains the address of the next
instruction to be executed. When a byte (machine code) is being fetched, the program
counter is incremented by one to point to the next memory location.

Example: MOV A ,B

Op-Code Fetch
MP
Memory
8000H
XX
8001H
44
IR

XX

PC
8000

8001

Instruction Register (IR)

It is an 8-bit register which temporarily stores the current instruction of a program. The
latest instruction is sent here from the memory prior to execution. The decoder then
takes the instruction and ‘decodes’ or interprets it. Then, the decoded instruction is
passed on to the next stage which is CPU storage. This opcode in a register is called the
instruction register. This opcode is further sent to the instruction decoder to select one
of the 256 alternatives.

Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points to a
memory location in the R/W memory, called the stack. The beginning of the stack is
defined by loading a 16-bit address in the stack pointer.
Stack: It is a part of the R/W memory which is used to store temporary data and also the
contents of then PC when subroutines are executed. The technique involved in stack is
LIFO (Last In First Out).

20
 The 8085 Microprocessors

Note:
• When data is stored or pushed into stack memory, stack pointer is decremented
• When data is accessed from stack memory stack pointer is incremented
• A single register data cannot be stored in stack memory

Example: Describe the output of the following code using graphical representation if the
stacks pointer points to F008H
LXI D, 5566 H
PUSH D

MP Memory

0000H
LIFO

SP-2 = F006H 66

SP-1 = F007H 55
SP
w w = write
F008 SP = F008H 44
F007
F009H 33 D E
F006
. . 55 66
. .
. .
FFFFH

Flag Register
It is an 8-bit register. There are 5 flags which are set or reset after an operation
according to the data conditions of the result in the accumulator and other registers.
They are called Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The
most commonly used flags are Zero, Carry, and Sign. The microprocessor uses these
flags to test data conditions.
As the result is stored in the accumulator, for most of the ALU operations, flags are
affected by the content of the accumulator except for a few instructions.

Example: Increment & Decrement

Note: Flags are affected or modified only for operations.

21
 The 8085 Microprocessors

Sign Flag
After execution of any arithmetic and logical operation, if D7 of the result is 1, the sign
flag is set. Otherwise it is reset. D7 is reserved for indicating the sign; the remaining is
the magnitude of the number. If D7 is 1, the number will be viewed as a negative number.
If D7 is 0, the number will be viewed as a positive number.

Zero Flag
If the result of an arithmetic and logical operation is zero, then the zero flag is set
otherwise it is reset. It may also be effected for other general purpose registers in the
same instruction.

Example: if A = [00H], then Z = 1

Auxiliary Flag
If D3 generates any carry when doing any arithmetic and logical operation, this flag is set.
Otherwise it is reset.

Parity Flag
If the result of an arithmetic and logical operation contains an even number of 1’s then
this flag will be set and if it is an odd number of 1’s it will be reset.

Carry Flag
If any arithmetic and logical operation results in any carry then carry flag is set otherwise
it is reset.

D7 D6 D5 D4 D3 D2 D1 D0

S Z X AC X P X CY

• These flags have critical importance in the decision-making process of the

micro-processor. The conditions (set or reset) of the flags are tested through the
software instructions. For example, the instruction JC (Jump on Carry) is implemented
to change the sequence of a program when CY flag is set. A thorough understanding
of flags is essential in writing assembly language programs.

PSW (Program Status Word)

PSW is a combination of accumulator and flag registers. It is a 16 bit hardware register
that maintains the status of the program being executed. It shows the current status of
the ALU operation.
PSW register pair

Accumulator Flag register

22
 The 8085 Microprocessors

Solved Examples

Problem: A = 15H, B = BEH, then find A + B = ? and also find the flags.

Solution:

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 1 0 1 0 1

1 0 1 1 1 1 1 0

0 1 1 0 1 0 0 1 1

CY

Flag resisters 90H

S Z X AC X P X CY

1 0 0 1 0 0 0 0

9 0

A + B = E3H

Problem: Find flags for 87H + 79H

Solution:

D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 0 1 1 1
0 1 1 1 1 0 0 1

1 0 0 0 0 0 0 0 0

CY

Flag resisters 55H

S Z X AC X P X CY

0 1 0 1 0 1 0 1

5 5

Note: Here only Zero flag, auxiliary carry flag, carry flag and parity flag is affected.

23
 The 8085 Microprocessors

Temporary Register
W, Z are the two 8-bit registers which are not accessible by the user. They are used by
the processor in some instructions.
Notes: There are no separate instructions for multiplication and division in 8085

Instruction Decoder, Machine Cycle Decoder

After the op-code is fetched into the IR instruction register, it is decoded in this block
with the help of a machine program. The number of machine cycles or operations are
assigned according to the type of instruction.

Micro-Programs
It is a program written by the manufacturer to make the processor understand what an
instruction is or it indicates the type of operations to be performed for an instruction.

Example: MOV B, C

Timing and Control Unit

Generates signals within the microprocessor to carry out the instruction which has
been decoded. In reality, it causes certain connections between the blocks of the
microprocessor to be opened or closed, so that data goes where it is required, and ALU
operations occur.

X1 & X2
• A crystal oscillator is connected between X1 & X2 pin to produce the necessary and
suitable clock frequency for the processor
• A crystal is used as it produces stable oscillation compared to RC and LC oscillator
• An internal clock generator take the reference frequency and produces operating
frequency which is half of the reference frequency and also other frequencies which
are required internally

fcrystal
• Operating frequency fclock =
2

• Operating frequency of 8085 is, fclk = 3MHZ and range is (3 to 6)MHZ

24
 The 8085 Microprocessors

Important Control Signals

• ALE (Address Latch Enable)
It occurs during the first clock cycle of a machine state and enables the address to
get latched into the on chip latch of peripherals.

1; All 16 lines → address bus

ALE = 0; A15 − A3 → address bus
AD7 − AD0 → Data bus

• RD = Read control signal

0 → Active
1 → Inactive

• WR = Write control signal

0 → Active
1 → Inactive

• IO / M = Status signal which indicates either memory or input output operation

0; Memory operation
IO / M =
1; IO operation

IO / M RD WR Control Signal Operation

0 0 1 Memory Read M/M read

0 1 0 Memory Write M/M write

1 0 1 IO/ R IO read

1 1 0 IO/ W IO write

25
 The 8085 Microprocessors

• S1, S0 = These give the status of bus cycle for an operation

S1 S0 Status

0 0 Halt

0 1 Memory write

1 0 Memory read

1 1 Opcode fetch

• HOLD
This indicates if any other device is requesting the use of the address and the data
bus. Then the microprocessor transfers the control to the requesting device as soon
as the current cycle is over. After the process of the requesting device is over, the
control is transferred back to the microprocessor.

• HLDA
HLDA is the acknowledgment signal for HOLD. It indicates whether the HOLD signal is
received or not. After the execution of HOLD request, HLDA goes low.

Regular path Memory

5 DMA operation

2
MP HOLD DMA
Controller
HLDA
3

4 1

HOLD

I/O
Regular path

When more or huge data is to be transferred between memory and I/O at a faster rate,
the DMA operation is used with the help of the DMA controller.

• Reset-in
Low active I/P signal to reset the processor and PC is initialized to 0000H

26
 The 8085 Microprocessors

• Reset-out
Output signal which indicates that the processor is reset. It can be used to reset
IO devices.

• Clock-out
• O/P pin on which the same operating frequency of the processor is available. It
can be used to connect to the IO device for synchronizing operations

• Ready
I/P pin to processor from a slow speed IO device. If ready is high, only then will the
processor either transmit data or receive data from IO device.

• Interrupt Control Unit

Trap, RST 6.5, RST 7.5, RST 5.5, INTR, INTR

• Serial IO Control Unit

It is used for serial communication between the processor and IO devices. Serial
communication means bit by bit transmission.

• SID
I/P pin through which processor receives serial data.

• SOD
O/P pin by which processor transmit serial data.

Note: Both SID and SOD are internally connected to D7 of accumulator.

MAR
Memory address register is used to hold the address before it is placed on the address
bus.

MDR
Memory data register is used to hold the data before it is transferred to memory or when
it is accessed from memory by the processor.

27
 The 8085 Microprocessors

Functional Description

Classification of Signal
(i) Address bus (unidirectional)
(ii) Data bus (Bi-directional)
(iii) Control and status signal (partially uni/Bi-directional)
(iv) Interrupt and externally initiated
(v) Serial IO ports
(vi) Power supply and frequency signal

X1 X2 Vcc Gnd (vi)

SID A15- A8 (Higher order

(v) address bus) (i)
SOD
AD7- AD0 (Multiplexed Data
TRAP address bus) (ii)

RST 7.5 ALE

RST 6.5 RD
8085
RST 5.5 WR
(iii)
INTR IO/M
(iv) Control and status
S1
signal
S0
Ready
Reset-Out
Hold HLDA
Reset-in INTA

Clock-Out

28
 8085 Interrupts

Chapter 3 – 8085 Interrupts

Objective
Upon completion of this chapter, you will be able to:
• Understand the basics of 8085 Interrupts
• Classification of 8085 Interrupts
• Maskable and Non-maskable Interrupts
• Instructions related to interrupt

Introduction
The interrupt driven I/O is one of the data transfer techniques used in h microprocessor
systems. By using this technique, the external device or peripheral can inform the
processor that it is ready for communication. The request for communication informed
by the peripheral is of the asynchronous type, meaning that it can be initiated at any
time without reference to the system clock. These requests are of two types: Maskable
and Non-maskable. In the case of maskable requests, the microprocessor has the
complete right to either service the requested communication or to deny it.

Interrupts of 8085
It is an internal or external signal which may disturb or alter the sequence of execution
of process. Interrupt is an event that demands the attention of the CPU. In general, any
microprocessor is set to be in the fetch execute cycle of the main program, i.e., in the
processing of the main program. If the occurrence of an interrupt event is recognized
by the microprocessor, it performs the following steps (known as interrupts switching
steps):

0000H : 1st Instruction

1H
0H 100
150 C) =

1500H
) ← (P

P
.S.
(PC S) =

Occurance of
oI
t

interrupt event
(TO

te rs
en

1000H : Current Instruction

µP

1001H : Next Instruction µP

ret
urn
P.C 1001H (PC s to
)← M.P
(TO RET
Next Address S)
=1
or 001
H
Return Addres
12FFH : HLT

29
 8085 Interrupts

TOS = Top of the stack

ISR = Interrupt service routine

Step-1:
Microprocessor completes execution of commonly fetched instruction.

Step-2:
Microprocessor saves the next address or written address available in the program
counter by pushing it into the top of the stack & then the program counter with vector
address, i.e., starting address of I.S.R

Step-3:
Microprocessor processes interrupt device routine, through fetch & execute cycle

Step-4:
At the end of I.S.R, when the microprocessor executes RET interrupt, it retrieves the
contents of TOS back into the program counter & interrupt resumes the main program
processes.

Classification of Interrupts
The 8085 has a multilevel interrupt system. It supports two types of interrupts:

Hardware Interrupts
These interrupts are available in the form of input pins i.e., physically available.
• 8085 has 5 hardware interrupts or external interrupts

or TRAP/RST 4.5 Highest Priority

RST 7.5

RST 6.5

RST 5.5

INTR Lowest Priority

Non vectored Interrupt

30
 8085 Interrupts

When any of these pins, except INTR, is active, the internal control circuit of the 8085
produces a CALL to a predetermined memory location. This memory location, where
the subroutine starts is referred to as the vector location and such interrupts are called
vectored interrupts. The INTR is not a vectored interrupt. It receives the address of the
subroutine from the external device.
In 8085, all interrupts except TRAP are maskable. When a logic signal is applied to a
maskable interrupt input, the 8085 is interrupted only if that particular input is enabled.
These interrupts can be enabled or disabled under program control. If disabled, 8089
disables an interrupt request. The interrupt TRAP is non-maskable which means that
E is not maskable by program control. The Fig. 6.6.1 shows the interrupt structure of
8085. The figure indicates that, the 8085 is designed to respond to edge triggering, level
triggering or both.

Priority Input pin Mask

RST
D Q
2 003C16
7.5
+ve edge triggered CLR Q
Reset
M 7.5 003816
RST 7.5 interrupt
recognized

3 RST 003416
Level triggered 6.5
003016
M 6.5
4 RST
5.5 002C16
Level triggered 002816
1 M 5.5 002416
TRAP
Both +ve edge and 002016
EI
Level triggered S Interrupt Get 001816
DI enable Q
Reset R RST 001016
Any interrupt recognized code 000816
from 000016
5 INTR external
hardware
Level triggered

Interrupt Structure of 8085

TRAP: This interrupt is a non-maskable interrupt. It is unaffected by any mask or

interrupt enable. TRAP has the highest priority. TRAP interrupt is edge and level triggered.
This means that the TRAP must go high and remain high until it is acknowledged. This
avoids false triggering caused by noise and transients.
As shown in the Fig. the positive edge of TRAP signal sets the D flip-flop. However, due
to the AND gate, it is necessary to sustain high level on the TRAP input.

31
 8085 Interrupts

TRAP
CALL 0024H
1 D Q

TRAP Q

RESET IN
TRAP
ACKNOWLEDGE

Interrupt Circuit for trap interrupt

• TRAP is both edge and level triggered. It is edge triggered such that it may respond
quickly. It is level triggered in order to differentiate the original signal from practical
application and error signal due to noise

• The signal on the TRAP pin must be high for at least 3 clock periods such that the
error signal due to noise may be avoided

There are Two Ways to Clear TRAP Interrupt

(1) By resetting the microprocessor i.e., giving a low signal on RESETIN pin (External
signal)

(2) By giving a high TRAP ACKNOWLEDGE (Internal signal)

After recognition of TRAP interrupt, 8085 internally generates a high TRAP

ACKNOWLEDGE which clears the flip-flop. Once the TRAP is acknowledged, the
8085 completes its current instruction. It then pushes the address of the next
instruction i.e., return address onto the stack and loads PC with the fixed vector
address 0024H., Due to this, 8085 starts execution of instructions from address
0024H which is the starting address of an interrupt service routine for TRAP.

RST 7.5
As shown in the above figure, it is positive edge triggered and the positive edge trigger
is stored internally by an the D flip-flop until it is cleared by a software reset using SIM
instruction or byan internally generated ACKNOWLEDGE signal. The positive edge signal
on the RST 7.5 pin sets the D flip-flop. If the mask bit M7.5 is 0 i.e., RST 7.5 is unmasked,
then 8085 completes its current instruction. It then pushes the address of the next
instruction onto the stack and loads the PC with the fixed vector address 003CH. Due
to this, 8085 starts execution of instructions from address 003CH which is the starting
address of an interrupt service routine for RST 7.5.

32
 8085 Interrupts

RST 6.5 and RST 5.5

The RST 6.5 and RST 5.5 both are level triggered. These interrupts can be masked using
a SIM instruction. The RST 6.5 has the third priority whereas RST 5.5 has the fourth
priority. The vector addresses of RST 6.5 and RST 5.5 are 0034H and 002CH respectively.
After recognition of RST 6.5 or RST 5.5 interrupt, 8085 completes its current instruction;
pushes the address of the next instruction onto the stack and loads the PC with the
corresponding vector address.

INTR
INTR is a maskable interrupt, but not the vector interrupt. It has the lowest priority. The
following sequence of events occur when the INTR signal goes high.
(1) The 8085 checks the status of the INTR signal during the execution of each
instruction
(2) If the INTR signal is high, then 8085 completes its current instruction and sends
an active low interrupt acknowledge signal (INTA) if the interrupt is enabled
(3) In response to the INTA signal, external logic places an instruction OPCODE on the
data bus. In the case of multibyte instruction, additional interrupt acknowledge
machine cycles are generated by the 8085 to transfer the additional bytes into the
microprocessor
(4) On receiving the instruction, the 8085 saves the address of the next instruction on
the stack and executes the received instruction

Response for RST Instruction

If the external device places an opcode for any one of the RST instruct on (RST 0-RST 7),
then 8085 pushes the contents of PC onto the stack. It then branches the program
control to the vector address of the corresponding RST instruction.

Response for CALL Instruction

If the external device places an opcode for CALL instruction, then 8085 generates two
additional interrupt acknowledge cycles.
(1) lt sends an active low interrupt acknowledge signal for the second time
(2) In response to the second INTA signal, external logic places the lower byte address
for the CALL instruction
(3) After receiving the lower byte address, 8085 sends the third interrupt acknowledge
signal
(4) In response to the third INTA signal, external logic places the higher byte address
for the CALL instruction
(5) After receiving the sixteen bit address for CALL, 8085 pushes the contents of the
PC onto the stack and branches the program control to the subroutine whose
address is received from the external logic

33
 8085 Interrupts

Software Interrupts
These interrupts are available in the form of instructions.
• 8085 has 8 software interrupts

RST 0
RST 1
RST 2
RST 3 Eight, 1 Byte intruction
RST 4 (Priorlly is not needed here)
RST 5 Because processor don't execute two instruction at atime
RST 6
RST 7

Maskable Interrupts
These interrupts can be either enabled or disabled by the program. If enabled, only
the occurrence interrupt event is recognized by the microprocessor. If disabled, the
occurrence of the interrupt event will be ignored by the microprocessor.
• EI (Enable Interrupt) & DI (Disable Interrupt & SIM (Set Interrupt Mask) instruction
are provided for masking
• 8085 has 12 maskable interrupts & only one non-maskable interrupt which is TRAP/
RST 4.5
• All 12 maskable interrupts can be globally enabled or disabled by using ‘EI’ or ‘DI’

Non-Maskable Interrupts
These interrupts cannot be disabled i.e., they always exist in an enabled state. The
8085 microprocessor has only 1 non-maskable interrupt (TRAP/RST4.5) which is used in
emergency conditions.
• EI, DI & SIM instructions don’t affect TRAP

Vectored Interrupts
For these interrupts, vector address, i.e., the starting address of I.S.R is prefixed by the
manufactures. The 8085 microprocessor has 12 vectored interrupts and these are:
RST 0 to RST 7 and RST 4.5, RST 5.5, RST 6.5, RST 7.5

• Any interrupt of 8085 in RST is a vectored interrupt

• ‘RST X’ ↔ Corresponding vector address which is completed by the machine [8x]16

34
 8085 Interrupts

12 Vectored interrupts Vector address

RST 0 -------------------------------- 0000H
RST 1 -------------------------------- 0008H
RST 2 -------------------------------- 0010H
RST 3 -------------------------------- 0018H
RST 4 -------------------------------- 0020H
RST4.5 -------------------------------- 0024H
RST5 -------------------------------- 0028H
RST5.5 -------------------------------- 002CH
RST6 -------------------------------- 0030H
RST6.5 -------------------------------- 0034H
RST 7 -------------------------------- 0038H
RST 7.5 -------------------------------- 003CH

Non-Vectored Interrupt
For these interrupts the vectored address is not prefixed by the designer. As such,
for servicing such interrupts externally, dedicated hardware is required, i.e., external
hardware supplies as well as a vector address are required for the interrupt request.
• 8085 has only 1 non-vectored interrupt (INTR) i.e., interrupt request
• 8259 PIC is normally used for serving a non-vectored interrupt

µP
8085µ 8259 IC
Step 2 Step 1

RST 4.5 INTR IR 0

:
:
:
RST 7.5
:
:
INTA IR 7
Step 3

RST 6.5
Step 4
Vector Address
P.C
RST 5.5
Data Bus Address Register

External hardware that

supplies interrupt request &
requested vector address

35
 8085 Interrupts

• In order to use INTR, the programmer must select one of the software interrupt
address to store ISR of I/O device
• INTA Generates the pulse only to recognize the INTR interrupt
• INTR is a pseudo interrupt input which can be used for increasing the number of
interrupts of 8085, with the use of 8259 PIC
• In the normal mode of operation 8259PIC supports 8 interrupting devices in a
cascaded mode of operation. 8259PIC supports 64 interrupting devices
• INTA is an active low interrupt ACK active pin. The 8085 microprocessor generates
an active low signal via this INTA output, when it receives and recognizes an
interrupt request
• INTR is monitored by the processor in the last clock period of an instruction
• INTA is required only for INTR and not for a vectored interrupt
• Every vectored interrupt in 8085 is given 8 bytes of memory to store the
corresponding program that must be executed in response to an interrupt which is
known as the interrupt service routine (ISR)
• By default all the interrupts are disabled

Example: If external interrupt signal is received via RST 4.5, then microprocessor initialize
PC with?

Solution: Due to the smaller amount of memory between two interrupts we used JMP
instructions.
For RST 4.5 PC initialize with 0024

PC
0024H JMP
JMP 1500H
00
15

0040
Main Program
14FF
1500H
I.S.R
For
RST 4.5
15FFH
1600H I.S.R
For
RST 6
USR = User
160FH define sevice
1610H USR routine

36
 8085 Interrupts

Instructions Related to Interrupts

EI (Enable Interrupt): Use to enable a maskable interrupt.
DI (Disable Interrupt): Use to disable a maskable interrupt.
SIM (Set Interrupt Mask): Use to mask the interrupts or make them available.
RIM (Read Interrupt Mask): Use to know the status of pending interrupts.

37
 8085 Interrupts

38
 Instruction Set of Microprocessor 8085

Chapter 4
Instruction Set of Microprocessor 8085
Objective
Upon completion of this chapter, you will be able to:
• Understand the language of instructions in a Microprocessor
• Explanation of Addressing mode
• Instruction set of 8085

Language of Instructions in a Microprocessor

Microprocessor 8085 can perform 256 different operations. In order to execute any
operation, we have to give the corresponding instruction to the Microprocessor. The
instructions to the microprocessor can be written in languages as given below:

(a) Machine Language Instruction

When an eight bit number is applied to the Instruction decoder input, then only
one circuit generates controlling signals, by which the microprocessor performs a
particular operation. The 8 bit binary number applied to the input of the Instruction
decoder is called the Instruction of the microprocessor in machine language or
machine language instruction.

(b) Hexcode Language Instruction

For feeding the instruction, a Hexadecimal number Keyboard is used. The
programmer has to feed the instructions in the form of a 2-digit Hexadecimal
number operating code (opcode). The instruction to the microprocessor in the
form of a two-digit Hexcode is called Hexcode language instruction. The two-digit
Hexcode is translated into 8 binary bits (machine language).

(c) Assembly Language or Mnemonics

The above two languages are difficult for the programmer. Hence, for convenience,
the instructions to the microprocessor are made in the form of English abbreviations
(short form) and are called Assembly language instructions or mnemonics.
Machine language, Mnemonics and Hexcode of some instructions are shown in the
Table.

Mnemonics Hexcode Language

S.NO. Machine language
(Assembly language) (Opcode)

1 MVI A 3E H 0011 1110

2 LXI H 21 H 0010 0001

3 STA 32 H 0011 0010

39
 Instruction Set of Microprocessor 8085

Programming Model
• Program: Set of instructions
• Instruction: It is a command given to the computer to perform some specific task
• Machine level language:
It is a binary means of communication with a computer through a design set of
instructions specific to a system
• Assembly level language:
Instructions are written in separate words known as ‘Mnemonics’ which are partially
understood by the programmer

MOV B, C
Example: Here MOV, ADD are Mnemonic (Easy to understand)
ADD D

• Both assembly and machine level language are together called Machine level
language
• Overall cycle of writing the program till execution:

Assembly Program

Assembler
Execute

Machine-Code
Decode (Microprogram)

Memory Op-Code Fetch

40
 Instruction Set of Microprocessor 8085

• Basic steps of execution of instruction:

(1) Op-code fetch
(2) Decode
(3) Execute

• Instruction format:

Op-code Operands

• Op-code (Operation code):

It indicates the type of operation to be performed for an instruction.

• Operand:
It is the data on which an operation is to be performed. Operand can be a register,
memory location register pair, 8-bit data or address, 16-bit data or address.

Length of anInstruction
• Number of bytes occupied by the instruction in the memory
• There are three types of instructions classified on the basis of length

(1) 1-Byte Instruction:

Example: MOV
 A,C
Op −code

operands

(2) 2-Byte Instruction:

Example: MVI B, 77H

(3) 3-Byte Instruction:

Example: LXI H , 9080H

 [X → Register pair]
  
Op −code operands
(1 Byte) (2 Byte)

Example:
4000H: MOV A, C → XX
4001H: MVI B, 77H → yy, 77H
4003H: LXI H, 9030H → ZZ, 30H, 90H

41
 Instruction Set of Microprocessor 8085

Memory representation:
F → Fetch
R → Read

(Memory)

4000H XX F

4001H yy F

4002H 77 R

4003H ZZ F

4004H 30 R

4005H 90 R

Note:
• Op-code is always fetch (In any type of process, fetch is always done first)
• Data is read or write

Memory Rule
In all memory related operations, the data present in the lower byte of the register is
transferred to a lower address location whereas higher byte data is transferred to a high
address location and vice-versa.

Standard Codes

B → 000
C → 001 Memory(M) → 110
D → 010 BC → 00
E → 011 DE → 01
H → 100 HL → 10
L → 101 SP → 11
A → 111
• Every register is given a unique code. There are 74 different op-codes in 8085 which
result in 246 instructions

42
 Instruction Set of Microprocessor 8085

Addressing Modes
The mode of specifying an operand’s address is known as addressing mode. There are
various formats specifying the operands. They indicate how the data is accessed for an
instruction. There are 5 types of addressing modes:
(1) Register addressing mode
(2) Implicit/implied addressing mode
(3) Immediate addressing mode
(4) Direct addressing mode
(5) Indirect addressing mode

(1) Register Addressing Mode

In this mode operand/s involved in operation is/are registers.

Example: MOV A, B; SPHL, PCHL, XCHG

ADD B; ADC H; DAD D; SUB A; SBB C; INR A; INX H; DCR B; DCX B
ANA B; ORA H; XRA A; CMP B

(2) Implicit/Implied Addressing Mode

In this mode operand is not given in the instruction and so the machine assumes the
accumulator to be the operand. If the address of the source of data as well as the
address of destination of result is fixed, then there is no need to give any operand
algorithm with the instruction. Such instructions are called implicit addressing
mode.

Example: DAA
RAL; RLC; RAR; RRC

(3) Immediate Addressing Mode

In this mode the operand (either 8-bit or 16-bit) is given in the instruction itself.
If the 8/16 bit data required for executing the instruction is given along with the
instruction then such instruction is called Immediate addressing mode.

Example: MVI C, 66H; MVI M, 54H; LXI SP, 2500H

ADI, 45H; ACI, 78H; SUI FFH; SBI A2H
ANI F4H; ORI 0FH; XRI 49H; CPI 41H
JMP 1000H; JNC 1400H……..JM 1488H; CALL 1200H; CNC 1532H………….CM 1258H
RST 0; ………………………………RST 7

43
 Instruction Set of Microprocessor 8085

(4) Direct Addressing Mode

In this mode address of the operand is specified in the instruction. If the 8/16 bit
data required for executing the instruction is present in the memory location and the
16 bit address of this memory location is given along with the instruction, then such
instructions are called direct addressing mode instructions.

Example: LDA 9000H; OUT F4H; STA 200H; SHLD 4652H; LHLD 2145H

(5) Indirect Addressing Mode

In this mode address of the operand is made available in a register pointer. Indirect
addressing mode is also known as register indirect addressing mode.
Example: LDAX B; STAX B MOV B, M; MOV M, A; PUSH B; POP PSW; XTHL
ADD M; ADC M; SUB M; SBB M; JNR M; DCR M
ANA M; ORM XRA; CMP M
RET; RNC………………………RM

Instruction Set of Microprocessor 8085

Microprocessor 8085 can perform a maximum of 256 different operations. For executing
any operation using the microprocessor, we have to give it the corresponding instruction.
Depending upon the type of operation performed by the instruction, the different
instructions to the microprocessor are divided into the following types:
(1) Data transfer instructions
(2) Arithmetic instructions
(3) Logical instructions
(4) Stack instructions
(5) Branching instructions
(6) Machine control instructions

Instruction set classification Instruction

Type of operation Length of instruction

(i) Data transfer (copy) instruction (i) 1 Byte instruction
(ii) Arithmetic instruction (ii) 2 Byte instruction
(iii) Logical instruction (iii) 3 Byte instruction
(iv) Stack instructions
(v) Branching instruction
(vi) Machine control instruction

44
 Instruction Set of Microprocessor 8085

Notations
r = 8 bit register
rs = 8 bit source register
rd = 8 bit destination register
r16 or rp = 16 bit register pair or 16 bit pointer

Data 8 = 8 bit data

Num 16 = 16 bit data
Addr 16 = 16 bit address of memory location
Add 8 = 8 bit port address

A = Accumulator
PSW = Program status word
M = Memory location contents pointed by HL pointers

• Every instruction consists of 2 parts

(1) Opcode
(2) Operand

Data Transfer Instruction

In this group, the data is transferred from one location known as ‘source’ to another
location known as ‘destination’. It may, in between:-
(a) Register to Register: MOV B, C
(b) Register to Memory: MOV D, M; MOV M, E
(c) Register to I/O: IN 20H; OUT 40H
(d) Register to data: MVI A, 55H

45
 Instruction Set of Microprocessor 8085

Syntax Operation

MVI r, data 8 (r) <= data 8

LXI rp, NUM 16 (rp) <= NUM 16

MVI M, data 8 ((HL)) <= data 8

MOV rd, rs (rd) <= (rs)

SPHL (SP) <= (HL)

PCHL (PC) <= (HL)

XCHG (DE) <=> (HL)

OUT Add 8 (Add 8) <= (A)

IN Add 8 (A) <= (Add 8)

MOV M, r ((HL)) <= (r)

MOV r, M (r) <= ((HL))

STAX rp ((rp)) <= (A)

LDAX rp (A) <= ((rp))

LDA Add 16 (A) <= (Add 16)

STA Add 16 (Add 16) <= (A)

(Add 16) <= (L)
SHLD Add 16 (Add 16 +1) <= (H)
2 memory write operation
(L) <= (Add 16)
LHLD Add 16 (H) <= (Add 16 + 1)
2 memory read operation
((SP)-1) <= (rH)
PUSH rp ((SP)-2) <= (rL)
(SP) decremented by 2
(rL) <= ((SP))
POP rp (rH) <= ((SP)+1)
(SP) incremented by 2
(TOS) <=> (HL)
TOS = Top of the Stack
XTHL
SP is unchanged after the execution
POPH followed by PUSH H

46
 Instruction Set of Microprocessor 8085

Note:
• In almost all data transfer operations, the container of source is unchanged after
the execution
• Flags are not affected by the execution of data transfer group of instructions, since
ALU is not involved
• Working principle of stack is LIFO i.e., last pushed number will be popped out first
• Stack pointer contents decrement by 2 for execution of PUSH and CALL
instructions
• When the PUSH instruction is executed, the stack pointer decrement firsts & writes
to the decremented address
• Stack pointer contents is incremented by 2 for execution of POP and RETURN
instruction
• When POP instruction is executed stack pointer first reads then increments
• Stack pointer contents are unaltered for XTHL instruction since XTHL = POPH
followed by PUSH H

Example: 3000H; MOV C, M if M = 77H

IR

XX
3000H XX F

.
.
D .
.

R
H L C 3500H 77

35 00 77 C
77

Example: 3400H; MOV M, E if (E) = 66H

IR

XX
3400H XX F

PC .
.
3400 D .
3401 .

W
H L E 3700H 66

37 00 66 E
66

47
 Instruction Set of Microprocessor 8085

Example: 3800H: MVI A, FFH

IR

XX
3800H XX Fetch (F)

PC R
3801H FF
3800 A
D
3801 FF

A
FF

Example: 4000H: MVI M, 33H if (HL) = 4600H

Z IR

33 XX
4000H XX F
R
PC 4001H 33

4000 D .
4001 . 33 Z
.
4002
W
4600H 33
H L
46 00

Example: 4700H: LXI H, 5000H

IR

XX
4700H XX F
PC
4700 4701H 00
R
4701 4702H 50 R
D
4702
4703 H L
50 00
H L
50 00

48
 Instruction Set of Microprocessor 8085

Example: 5100H: LDA 5400H if (5400H) = 89H

IR
W Z
54 00 XX
5100H XX F

5101H 33 R
PC R
5102H 54
5100 D
. W Z
5101 .
54 00
5102
A 5400H 89
5103 R
89
89 A

Example: 5000H: STA 6000H, if (A) = 3FH

IR
W Z
60 00 XX
5600H XX F

5601H 00 R
PC R
5602H 60
5600 D
. W Z
5601 .
60 00
5602
A 6000H 3F
5603 W
3F
3F A

Example: LDAX H doesn’t exist, not designed because it is same as MOV A, M

Example: 6200H: LDAX B if (BC) = 6300H & ((BC)) = 79H

IR

XX
6200H XX F

PC .
.
6200 D .
6201 .
R
B C A 6300H 79

63 00 79 A
79

49
 Instruction Set of Microprocessor 8085

Example: STAX H doesn’t exist, not possible because same as MOV M, A

Example: 6400H: STAX B if (A) = 23H & (BC) = 6900

IR

XX
6400H XX F

PC .
.
6400 D .
6401 .

W
B C A 6900H 28

69 00 28 A
28

Example: 7000H: PUSH D if (DE) = 9876H & (SP) = F005H

IR
D E
7000H XX
98 76 XX
. F
.
.
PC D
SP - 2 = F003H 76
7000
W
SP SP - 1 = F004H 98 W
7001
F005 SP = F005H WW
D E
F004 .
98 76
F003 .
.
FFFFH

Example: 7300H: POP H if (HL) = 4030H & (SP) = D00B

IR
7300H XX
XX
. F
.
.
PC D
SP = D009H 30
7300 R
SP SP + 1 = D00AH 40 R
7301
D009 SP + 2 = D00BH WW
H L
D00A .
40 30
D00B .
.
FFFFH

50
 Instruction Set of Microprocessor 8085

Example: 7700H: IN 50 H

IR
Z
7000H XX F
50 XX
50 R
7701H
Z
D
50
PC
Port address 50H
7700
7701
7702 A I/P
Device
WW

Example: 8000H: OUT 70H

IR
Z
XX F
8000H
70 XX
70 R
8001H

Z
D
70
PC Port address 70H

8000

8001

8002 A O/P
Device
43

51
 Instruction Set of Microprocessor 8085

Example: E000H: LHLD E400H

If (E400H) = 46
(E401H) = 8A

IR
WZ
E4 00 XX
E000H XX F

E4 01 00
E001H R
E4 R
D E002H
.
. W Z
PC
. E4 00
E000
H L E400H 46
E001
E401H 8A R R
E002 8A 89
H L
E003
8A 46

Example: E600H: SHLD E800H if (HL) = 3957H

IR
WZ
EB 00 XX
E600H XX F

E601H 00 R
EB R
D E602H
.
. W Z
PC
. EB 00
E600
H L E800H 57
E601
E801H 39 W W
E602 39 57
H L
E603
39 57

52
 Instruction Set of Microprocessor 8085

Arithmetic Instruction
• No multiplexer/division operation is supported by 8085
• 8085 microprocessor has accumulator based ALU i.e., in most of the arithmetic &
logical operations, the accumulator is one of the source operands and also acts as a
destination operand for result storage
(a) Addition; ADD C
(b) Subtraction; SUB M
(c) Increment; INX H
(d) Decrement; DCR M

Syntax Operation

Add r (A) <= (A) + (r)

Decimal adjust after
DAA
addition
DAD rp (HL)+( rp) => (HL)

ADC r (A) <= (A) + (r) + (CY)

ADD M (A) <= (A) + ((HL))

ADC M (A) <= (A) + ((HL)) + (CY)

ADI data 8 (A) <= (A) + data 8

ACI data 8 (A) <= (A) + data 8 + (CY)

SUB r (A) <= (A) - (r)

SBB r (A) <= (A) - (r) - (CY)

SUB M (A) <= (A) - ((HL))

SBB M (A) <= (A) - ((HL)) - (CY)

SUI data 8 (A) <= (A) - data 8

SBI data 8 (A) <= (A) - data 8 - (CY)

INR r (r) <= (r) + 1

INX rp (rp) <= (rp) + 1

INR M (M) <= ((HL)) + 1

DCR r (r) <= (r) – 1

DCR rp (rp) <= (rp) – 1

DCR M (M) <= ((HL)) – 1

53
 Instruction Set of Microprocessor 8085

• DAD instruction is a special instruction for performing 16 bit addition

• For the subtraction operation, the microprocessor uses 2’s complementary
techniques
• After the subtraction operation, carry flag is to be complemented
• If CY = 1, then the result in accumulator is positive (should be treated to be existing
in 2’s complemented form in its original magnitude)
• If CY = 0, then result in the accumulator is negative (should be treated as its original
magnitude)
• 16 bit increment & decrement operations are not performed by ALU. As such the
flags are not affected by the execution of INX & DCX operations
• INR & DCR instructions affect all flags except CY flag
• For DAD, accumulator is unchanged after the operation. If there is a carry out of 16-
bit, the carry flag is affected and remaining flags are unchanged
• DAA is the only instruction which works with the status of the auxiliary carry flag
(AC) in BCD conversions. It is used after addition. It converts 8-bit data present in
the accumulator into two 4-bit BCD numbers. It uses the following condition for
execution, after varying the contents of the accumulator
If D3 − D0 > 9 or AC = 1; Add 6
If D7 − D4 > 9 or CY = 1; Add 6

Example: ADD C
DAA

If (A) = (89)BCD, (C) = (77)BCD

(89)BCD = 1 0 0 0 1 0 0 1
(77)BCD = 0 1 1 1 0 1 1 1
CY = 1 0 0 0 0 0 0 0 0

AC and CY = 1 are one then add 6

0 0 0 0 0 0 0 0
CY 0 1 1 0 0 1 1 0
0 1 1 0 0 1 1 0 = 66H

(A) <= 66H

54
 Instruction Set of Microprocessor 8085

Example: ADD B if (A) = F9H & (B) = 68H

F9 = 1 1 1 1 1 0 0 1
68 = 0 1 1 0 1 0 0 0
CY = 1 0 1 1 0 0 0 0 1
(A) <= 61
S Z X AC X P X CY
0 0 0 1 0 0 0 1

Example: 8000H: ADD M if (A) = 38 & M = C7

38 = 0 0 1 1 1 0 0 0
C7 = 1 1 0 0 0 1 1 1
CY = 0 1 1 1 1 1 1 1 1

(A) <= FFH

S Z X AC X P X CY
1 0 0 0 0 1 0 0

Example: ADI 2EH if (A)=5B

5B = 0 1 0 1 1 0 1 1
2E = 0 0 1 0 1 1 1 0
CY = 0 1 0 0 0 1 0 0 1

(A) <= 89

S Z X AC X P X CY
1 0 0 1 0 0 0 0

Example: A600H: ADC M if CY = 1, (A) = 89 & M = 76

1
89 = 1 0 0 0 1 0 0 1
76 = 0 1 1 1 0 1 1 0
CY = 1 0 0 0 0 0 0 0 0

(A) <= 00H

S Z X AC X P X CY
0 1 0 1 0 1 0 1

55
 Instruction Set of Microprocessor 8085

Example: SUB C if (A) = 94H & (C) = 31H

Manual Processor
A − C A +(− C)

94 = 1 0 0 1 0 1 0 0 94 = 1 0 0 1 0 1 0 0

−31 = 1 1 0 0 1 1 1 1 +CF = 1 1 0 0 1 1 1 1

CY = 1 0 1 1 0 0 0 1 1 CY = 1 0 1 1 0 0 0 1 1

S Z X AC X P X CY S Z X AC X P X CY
0 0 0 * 0 1 0 0 0 0 0 1 0 1 0 1
Using the manual method, we can’t find the ‘AC’ flag but the method used by the
processor has the capability to determine (assign) the Auxiliary flag (AC).

Trick
Find ‘AC’ by using the manual method.
If result is Nibble<Accumulator lower Nibble
Then AC = 1
Else AC = 0

Example: SUI 9CH if (A) = 24

24 = 0 0 1 0 0 1 0 0
−9C = 0 1 1 0 0 1 0 0
CY = 0 1 0 0 0 1 0 0 0

S Z X AC X P X CY
1 0 0 0 0 1 0 0

Example: SBB H if (A) = 5A (H) = 9E

Borrow = 1
H = 9E + 1 = 9F

5A = 0 1 0 1 1 0 1 0
−9F = 0 0 1 0 0 0 0 1
CY = 0 0 1 1 1 1 0 1 1

S Z X AC X P X CY
1 0 0 0 0 1 0 1

56
 Instruction Set of Microprocessor 8085

Example: SBI AEH if (A) = 68

68 = 0 1 1 0 1 0 0 0
−AE = 0 1 0 1 0 0 1 0
CY = 0 1 0 1 1 1 0 1 0

S Z X AC X P X CY
1 0 0 0 0 0 0 1

Example: INR C if (C) = FF

FF = 1 1 1 1 1 1 1 1
+1 = 0 0 0 0 0 0 0 1
CY = 0 0 0 0 0 0 0 0 0

S Z X AC X P X CY
0 1 0 1 0 1 0 X'

X' → Previous status

Example: C000H: INR M if M = 8F

8F = 1 0 0 0 1 1 1 1
+1 = 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0

S Z X AC X P X CY
1 0 0 1 0 1 0 X'

X' → Previous status

Example: INX H if (HL) = FFFFH

FFFF = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
No flag will affect
+1 = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

57
 Instruction Set of Microprocessor 8085

Example: D000H: DCR M if M = 00H

00 = 0 0 0 0 0 0 0 0
−1 = 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1

S Z X AC X P X CY
1 0 0 0 0 1 0 X’

X' → Previous status

Example: DCX D if (DE) = F000H

F000 = 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
−1 = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1

No flag will affect

Example: F000H: DAD B if (BC) = F00F & (HL) = 9876
(BC)+(HL)

F00F = 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1
+9876 = 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0
CY = 1 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1

(HL)=8886H

Logical Instruction
8085 microprocessor has an accumulator base ALU i.e., in most logical operations, one of
the source operands is the accumulator which is also the destination operand for result
storage.
(a) AND; ANA D
(b) OR; ORI FFH
(c) Ex-OR; XRA M
(d) Compare; CDI 00H
(e) Compliment; CMA
(f) Rotate; RRC

58
 Instruction Set of Microprocessor 8085

Syntax Operation

AND accumulator with r

ANA r
(A) <= (A)∧(r)

ANA M (A) <= (A)∧((HL))

ANI data 8 (A) <= (A)∧data 8

ORA r (A) <= (A)∨(r)

ORA M (A) <= (A)∨((HL))

ORI data 8 (A) <= (A)∨data 8

XRA r (A) <= (A)∀(r)

XRA M (A) <= (A)∀((HL))

XRI data 8 (A) <= (A)∀data 8

CMP r (A) − (r)

CMP M (A) − ((HL))

CPI data 8 (A) − data8

Complement contents of
CMA
accumulator

CMC CY <= CY

STC CY <= 1

RLC Rotate accumulator left

Rotate accumulator left through

RAL
carry

RRC Rotate accumulator right

Rotate accumulator right through

RAR
carry

59
 Instruction Set of Microprocessor 8085

• For CMP M operation results are not stored in ‘M’. It differs from SUB instruction. We
have to check status from the flags
• CMA instruction is used for 1’s compliment performing
• Rotate operations include only change of carry flag. No other flags are affected using
the rotate operation
• For any AND operation AC=1 & CY=0
• For any OR operation AC=0 & CY=0
• Set by microprocessor, remaining flags depend on results
• Comparison is performed by doing internal subtraction but result is not stored
in accumulator i.e., both the operands involved in comparison are unaltered. Flag
register is updated after comparison operation

Z CY – (B) Result

1 0 Zero (A)=(B)

0 0 Positive (A)>(B)

0 1 Negative (A)<(B)

Sign flag depends on the subtraction of (A) - (B).

Instructions which make the Accumulator reset
• XRA A
• ANI 00H
• MVI A, 00H
XRA A is preferred since it takes less machine cycles and thereby saves memory and
increases the speed of operation. MVI A, 00H also has the same machine cycles but, in
this operation, the flags are different for different values. In XRA A, flags are not affected.

RAL (Rotate Accumulator Left through Carry)

CY

MSB D6 D5 D4 D3 D2 D1 LSB

60
 Instruction Set of Microprocessor 8085

RLC (Rotate Accumulator Left through without Carry)

CY

MSB D6 D5 D4 D3 D2 D1 LSB

RAR (Rotate Accumulator Right through Carry)

CY

MSB D6 D5 D4 D3 D2 D1 LSB

RRC (Rotate Accumulator Right through without Carry)

CY

MSB D6 D5 D4 D3 D2 D1 LSB

61
 Instruction Set of Microprocessor 8085

Application of Rotate Operation

• Used to find whether a number is odd or even and also to find whether a no. is +Ve
or –Ve

 , we can identify whether the number is

• Suppose a data is given as 1 001100 0
MSB LSB

even or odd just by looking LSB, if LSB=0 then number is even otherwise it is odd

If LSB=1, then number is odd otherwise it is even. If we want to judge whether

the no. is +Ve or –Ve, then if MSB=1 (-ve number), if MSB=0 (+ve number). But in a
microprocessor it is not possible to judge directly. So, we use the carry flag to check
the above condition
• Rotate left: If we want to check for +ve or –ve number, we use RAL (Rotate left with
carry). Thus, the carry flag content is MSB. Now by checking the carry flag we can
identify whether the number is +Ve or –Ve
• Rotate right: When using RAR, carry flag condition is LSB and we can check the carry
flag. If CY=1 (odd number) and if CY=0 (even number)

Effect of Arithmetic and Logical Instruction on Flags

• Flags are affected by arithmetic & logic operations only
• Addition, subtraction, compare, and decimal adjust instructions affect the CY, Z, S,
AC, P flags
• INR & DCR affect the S, Z, AC & P flags. We can’t detect overflow using the INR
instruction
• INX & DCX don’t affect any flags because the processor can process 8 bit data. This
is performed by the Dec/Inc unit of register array
• DAD, CMC, STC, and Rotate affect only the carry flag
• OR & XOR affect all the flags, reset AC = 0, CY = 0.

Example: ANA C if (A) = 55 & (C) = AA

55 = 0 1 0 1 0 1 0 1
AA = 1 0 1 0 1 0 1 0
0 0 0 0 0 0 0 0

S Z X AC X P X CY
0 1 0 1 0 1 0 0

62
 Instruction Set of Microprocessor 8085

Example: ORA L if (A)=DB & (L)=59

DB = 1 1 0 1 1 0 1 1
59 = 0 1 0 1 1 0 0 1
1 1 0 1 1 0 1 1

S Z X AC X P X CY
1 0 0 0 0 1 0 0

Z = 0 & CY = 0
A > B, Positive number

Example: XRA A if (A) = FF

FF = 1 1 1 1 1 1 1 1
FF = 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0

S Z X AC X P X CY
0 1 0 0 0 1 0 0

Example: CMP C if (A) = 59 & (C) = BE

A − C

59 = 0 1 0 1 1 0 0 1
−BE = 0 1 0 0 0 0 1 0
1 0 0 1 1 0 1 1

S Z X AC X P X CY
1 0 0 0 0 1 0 1

63
 Instruction Set of Microprocessor 8085

Example: RRC If (A) = 57H & CY = 0

CY

MSB D6 D5 D4 D3 D2 D1 LSB

0 1 0 1 0 1 1 1

1 0 1 0 1 0 1 1

(A) <= AB

Example: RAR If (A) = 6CH & CY = 1

CY

MSB D6 D5 D4 D3 D2 D1 LSB

0 1 1 0 1 1 0 0

1 0 1 1 0 1 1 0
(A) <= B6

Stack Related Instructions

Stack memory is a part of the Read-write memory (RAM) which is used to save useful
data of register pairs in the form of a stack of data i.e., in an upward direction. As the
data is arranged in the form of stack memory, it will be Last in first out (LIFO) or First in
last out (FILO).
When the data is transferred between the microprocessor and stack memory, for
selecting one memory location, the microprocessor will transfer 16 bit numbers from the
stack pointer to address pins.
Stack pointer is a 16 bit register, which holds the address of the last byte written onto
the stack. This is also called the stack top.

64
 Instruction Set of Microprocessor 8085

Branching Instruction
This group of instructions is also called the program transfer control group. In this
group, the control program is transferred from one location to another conditionally or
unconditionally. These instructions are operated on the program counter and in turn they
change or alter the sequence of processing.

Conditional Instruction
They depend on the status of the flags affected by the previous ALU operation (except
Auxiliary carry flag (AC)).
• When condition is true, control of program is transferred to a 16-bit address. 3
machine cycles i.e., 10T states consumed
• When condition is false, the very next instruction is executed. 2 machine cycle i.e.,
7T states are consumed

Test conditions

CY=0 P=0 Z=0 S=0

CY=1 P=1 Z=1 S=1

• AC can’t be tested. It is used only for internal BCD arithmetic operation

JUMP Instruction

Syntax Operation

JNC Add 16 Jump to address if CY = 0

JC Add 16 Jump to address if CY = 1

JPO Add 16 Jump to address if odd parity (P = 0)

JPE Add 16 Jump to address if even parity (P = 1)

JNZ Add 16 Jump to address if No zero (Z = 0)

JZ Add 16 Jump to address if zero (Z = 1)

JP Add 16 Jump to address if plus (S = 0)

JM Add 16 Jump to address if minus (S = 1)

• There are 9 jump instructions (8-Conditional and 1-Unconditional) and each

instruction require 3-machine cycles. Hence, the total number of machine cycles
required to execute all 9 jump instruction = 9 × 3 = 27machine cycles

65
 Instruction Set of Microprocessor 8085

Example: (C) = 02H

3000H XX
3000H: MVI C, 02H 3001H 02
Loop: 3002H: DCR C 3002H yy
3003H zz Fetch
300H: JNZ LOOP
3004H 02
3006H: HLT
3005H 30
R R
3006H ww

W Z
30 02
+1
PC 3000
3006
3003

• In the above program, if the content of the register ‘c’ is ’n’, the loop executes for
n-times where the condition is true for (n-1) times and, when it is false, only once
• When the condition is false, the PC is incremented twice to execute the next
instruction
• The operation of the remaining conditional jump instructions is similar to JNZ
except that the flags are different

CALL Instruction

Syntax Operation

CNC Add 16 CALL address if CY = 0

CC Add 16 CALL address if CY = 1

CPO Add 16 CALL address if P = 0

CPE Add 16 CALL Address if P = 1

CNZ Add 16 CALL Address if Z = 0

CZ Add 16 CALL Address if Z = 1

CP Add 16 CALL Address if S = 0

CM Add 16 CALL Address if S = 1

When condition is true, the operation is similar to an un-condition call that is 5 machine
cycles i.e., 18 T-States.
• When condition is false, 2 machine cycles i.e., 9 T-States are consumed
• When the condition is false, the SP (Stack Pointer) is unchanged

66
 Instruction Set of Microprocessor 8085

Return Instruction

Syntax Operation

RNC Return if no carry (CY=0)

RC Return if carry (CY=1)

RPO Return if odd parity (P=0)

RPE Return if even parity (P=1)

RNZ Return if no zero (Z=0)

RZ Return if zero (Z=1)

RP Return if plus (S=0)

RM Return if minus (S=1)

• Return instruction is used as the last instruction of a Subroutine or interrupt service

Subroutine
• PCHL instruction is equivalent to an unconditional Jump instruction
• When the condition is true, the operation is similar to an unconditional return
except that fetch is of 6 T-States
• When condition is false only one machine cycle i.e., 6 T-States are consumed
• RST n instructions i.e., software interrupt instructions are equivalent to
unconditional CALL instructions
• Conditional jump instructions are used for iteration control

Unconditional Instruction
The control of the program is transferred to 16 bit address unconditionally.

Syntax Operation

JMP Add 16 (PC) <= Address

((SP)-1) <= (PCH)
CALL Add 16 ((SP)-2) <= (PCL)
& (PC) <= Add 16
(PCL) <= ((SP))
RET
(PCH) <= ((SP)+1)
PCHL (PC) <= (HL)

67
 Instruction Set of Microprocessor 8085

((SP)-1) <= (PCH)

RET n ((SP)-2) <= (PCL)
& (PC) <= [8n]16

• The term used for call in ‘c’ language is function calling, but in a microprocessor,
this function is termed ‘Subroutine’
• If length of instruction is large, it is termed ‘Procedure’
• If length of instruction is small it is termed ‘Macro’
• Call instructions are used to call the subroutine main program

Subroutine
A set or a group of instructions which perform specific functions can be written as a
separate program away from the main program and this is known as Subroutine.

When CALL is Executed

Step-1: The contents of the PC or address of instruction next to the call is pushed on to
stack memory, then SP → SP-2

Step-2: The control of the program is transferred to the Subroutine address and
execution continues.

When RET is Executed

Step-1: The data present at the top of the stack (2 Bytes) pointed by SP is accessed or
loaded into the program counter. Therefore SP → SP+2.

Step-2: Control of the program is transferred to a 16 bit address and execution

continues.

When RST n is Executed

Step-1: The contents of the PC or address of instruction next to RST n is pushed down to
the stack memory, therefore SP → SP-2.

Step-2: Control of the program is transferred to the vector address of RST n and
execution is completed.
• CALL & RET operations are known as subroutine handling operations. CALL
instruction is used for transferring the program control to a subroutine from the
main program and RET instruction is used for transferring the control program back
to the main program from the subroutine.

Example: (BC) = 1234H & (A) = 34

LXI B, 1234 H

68
 Instruction Set of Microprocessor 8085

MOV A, C
JMP QUIT

ORI FFH
These are not executed because of jump instructions.
ANI FFH
OUIT: HLT .
6000H
.
.
.
Example: Main Program: 6005H XX F

6000H CALL 6006H 00

. 6007H 80
. yy R R
PC 6008H
.
6009H x'x'
6005H: CALL RZ . W Z
. 80 00
6008H: NOP .
8000H +1
RZ 8001
6009H: HLT 8004H zz
.
.
RZ: 8000H : SP-2 = F004H 0B
W
SP-1 = F005H 60 W
8004H : RET
SP = F006H ww 6008
.
8001
.
PC
FFFFH

Machine Control Instructions

This group of instructions control the internal actions of the machine.
• HLT → 1 Byte instruction
It is used to stop the execution of a program. The process enters the Halt
acknowledgement cycle. One or more than one wait states are included for every
clock period. Internally the PC is disconnected from the address bus as there is no
provision for the next op-code fetch and so the program stops. A reset or hardware
interrupt is required to come out of the Halt state
• NOP1 → Byte instruction
No operation is performed by the instruction but a delay of 4-T states is
included in the execution time. It is used to write a delay program and also when
communicating with slow speed peripheral devices

Example: MVI C, 03H

L1: JNZ L1
HLT

69
 Instruction Set of Microprocessor 8085

C = 03
02, Z = 0 → True
01, Z = 0 → True
00, Z = 1 → False
Let the above program provide ‘x’ µ second delay, then if we introduce ‘NOP’, the delay is
increased by 4 T-States
• DI (Disable interrupt) → 1 Byte instruction
Used to disable the maskable interrupt. Used at the initial instruction of ISR such
that the processor may not be disturbed by other interrupts.
• EI (Enable interrupt) → 1 Byte instruction. It is used to enable maskable interrupts.
Used at the initial instruction of the main program and at the last instruction of
an ISR, such that the processor may be ready to serve another interrupt. Internally
enabled interrupt flip-flop is set.
• SIM (Set interrupt mask) → 1 Byte instruction
It is a multipurpose instruction used to mask the interrupts or make them available
valid only for RST 7.5, RST 6.5, RST 5.5. It is used along with the contents of the
Accumulator. It is also used to transfer serial data out the processor through SOD
pin.

SOD pin

D7 D6 D5 D4 D3 D2 D1 D0

SOD SDE X R 7.5 MSE M 7.5 M 6.5 M 5.5

Serial O/P
data if 1 = Masked
0 = Available
Reset
Serial data RST 7.5 F.F Mask set enable
Enable 1 = Reset
1 = Enable SOD 1 = D2 − D0 = Valid/significant
0 = Disable SOD 0 = D2 − D0 =Invalid/Insignificnt

• It is not a register, it is a format only

• 'D3' bit is the control over D2 − D0. If it is 1 they are valid/significant else invalid/
insignificant

• D0 − D2 indicate whether interrupt is masked or available

• D4 is an extra provision for RST 7.5 to reset

• D6 is control bit over D7

• D7 , serial data to be transmitted through SOD pin

70
 Instruction Set of Microprocessor 8085

Example: After the execution of following instruction, find

(i) Interrupt Mask
(ii) Serial data transmitted
(iii) Interrupt Available
EI
MVI A, 4CH
SIM

Solution: 4C → 01001100

0 1 0 0 1 1 0 0

SOD SDE X R7.5 MSE M7.5 M6.5 M5.5

(i) Interrupt masked → RST 7.5 (see D3 then D2)

(ii) Interrupt available → RST 6.5, RST 5.5 (rest D1 , D0)

(iii) Serial data transmitted → '0' (See D7)

• RIM (Read interrupt mask) → 1 Byte instruction

It is a multipurpose instruction used to know the status of an interrupt and also to
receive serial data into the processor through the SID pin. Valid only for RST 7.5, RST
6.5, RST 5.5. After execution of the RIM instruction, status is loaded or copied into
the accumulator. It is the reverse of SIM

SID pin

D7 D6 D5 D4 D3 D2 D1 D0

SID I7.5 I6.5 I5.5 IE 7.5 6.5 5.5

Serial I/P
data Status of pending if 1 = Masked
Interrupts 0 = Available
1 = Pending
Interrupt Enable Flip-Flop
1 = Interrupt Enable (For EI)
0 = Interrupt Disable (For DI)

D3 indicates whether the interrupt is enabled or disabled.

• D0 − D2 indicates whether the interrupt is masked or available

• D4 − D6 indicates status of the pending interrupt

• D7 is the serial data received into the processor through the SID pin

71
 Instruction Set of Microprocessor 8085

Example: The content of Accumulator after execution of RIM instruction is 9CH. Find:-
(i) Interrupt masked
(ii) Interrupt available
(iii) Interrupt pending
(iv) Serial data received

Solution: 9CH = 10011100

1 0 0 1 1 1 0 0

SID I7 I6 I5 IE 7.5 6.5 5.5

(i) RST 7.5 (See D3 then D2)

(ii) RST 6.5, RST 5.5 (See D3 then D0 , D1)

(iii) RST 5.5 (See D4)
(iv) '1' (See D7)

Notes:
SIM → Controls the interrupt
RIM → Represents status of the interrupt

Conclusion:
* PUSH Rp
* POP Rp
* CALL SP → SP-2 → SP → SP+2
* Return
* RST n

Solved Examples

Problem:
9900H: LXI H, 1230H
9903H: PCHL
9904H: MVI A, FFH
9906H: HLT
What is content of “A” after execution of above program

Solution: Since the PCHL operation changes the PC to 9906H, the instruction at 9904H is
not executed. Hence, the content of A is undefined.

72
 Instruction Set of Microprocessor 8085

Problem:
After the execution, what is the content of SP and data present at CFFEH
LXI SP, FF00H
LXI H, D000H
SPHL
PUSH B
POP B
HLT

Solution: (SP)=FF00H
(HL)=D000H
(SP)=D000H
SP=D000H after PUSH & POP operation because PUSH and POP cancel each other out.
At CFFEH → 00H (When push perform, SP → SP-2 i.e., CFFEH and at this position lower bit
of HL is place i.e., 00H)

Problem:
Write an assembly language program (ALP) to perform Ex-Or operation between the first
two memory location data and to store the contents of the flag register and accumulator
to the next memory location.

Solution:
LDA 6000H
MOV B, A
LDA 6001
XRA B
LXI SP 6004
PUSH PSW
HLT

B = E7 = 1 1 1 0 0 1 1 1
A = −B1 = 1 0 0 0 0 0 0 1
0 1 1 0 0 1 1 0

S Z X AC X P X CY
0 0 0 0 0 1 0 0

73
 Instruction Set of Microprocessor 8085

(A) <= 66H

(PSW) = 6604H

Problem:
Write an assembly language program to access a data byte from port address 70H,
complement it, and rotate the result left side 5 times. Store the resultant value at 900FH
and after transferring it to port, add 90H.

Solution:
IN 70H
CMA
MVI B, 05 H
L1: RLC
DCR B
JNZ: L1
OUT 90H
STA 900FH
HLT

Problem:
LHLD 7000H
LXI D, 7003H
LDAX D
MOV B, M
ANA B
DAD H
SPHL
PUSH PSW
HLT
Then find address stored in SP and the top of the stack & also find the value stored in
the accumulator.

7000H 02

7001H 70
7002H BD
7003H 3C

74
 Instruction Set of Microprocessor 8085

Solution:
(i) H = 70, L = 02
D = 70, E = 02
(ii) A = 3C
(iii) B = BD

(iv) 3C = 0 0 1 1 1 1 0 0
BD = 1 0 1 1 1 1 0 1
0 0 1 1 1 1 0 0 = 3CH

S Z X AC X P X CY
0 0 0 1 0 1 0 0
PSW = 3C14H

7002
(v) 7002
E004

(vi) SP → E004
(vii) SP → E002

Top of stack = 14H

(A) = 3C

Problem:
Write an assembly language program for 8085 to transfer 4-bytes of data starting from
7000 to 8000H

Solution:
LXI H 7000H
LXI D 8000H
MVI B, 04H
Rept: MOV A, M
STAX D
INX H
INX D
DCR B
JNZ: Rept
HLT

75
 Instruction Set of Microprocessor 8085

Problem:
Find the content of SP and data present at the top of the stack after the execution of the
following program:
900H: LXI SP, FF00H
9003H: LXI H, 9009H
9006H: PCHL
9007H: MVI B, 66H
9009H: CALL R1
900CH: JMP QUIT
R1: 900FH: XRA A
9010H: RP
QUIT: 9011H: HLT

Solution:
SP = FF00H
HL = 9009H
PC = 9009
B = 66H
Due to the Call instruction, the contents of the Program Counter are stored in Stack and
the Program counter contains the address of the subroutine.
PC = 900F & SP = FEFEH
A = 00H & Z = 1, P = 1, CY = 0, AC = 0, S = 0
S = 0 i.e., return to 900CH
PC = 900CH
Hence, at the top of SP, after execution of program = 55 at address FF00H, but content
of SP is OC, 90, 55 as shown in the diagram with the address.

SP-2 = FEFEH 0C

SP-1 = FEFFH 90
SP = FF00H 55
90 0C

76
 8085-Timing Diagrams

Chapter 5 – 8085-Timing Diagrams

Objective
Upon completion of this chapter, you will be able to:
• Understand Timing and Control
• 8085 Machine cycles and their Timings
• State Diagram of 8085

Introduction
During a normal operation, the microprocessor sequentially fetches, decodes and
executes one instruction after another until a halt instruction (HLT) is executed. The
fetching, decoding and execution of a single instruction constitutes an instruction cycle
which consists of one to five read or write operations between processor and memory
or input/output devices. Each memory or I/O operation requires a particular time
period, called machine cycle. In other words, to move a byte of data in or out of the
microprocessor, a machine cycle is required. Each machine cycle consists of 3 to 6 clock
periods/cycles, referred to as T-states. Therefore, we can say that one instruction cycle
consists of one to five machine cycles and one machine cycle consists of three to six
T-states i.e., three to six clock periods, as shown in the figure.

Instruction Cycle

Machine Cycle 1 Machine Cycle 2 Machine Cycle 5

T-State 1 T-State 2 T-State 3 T-State 6

Figure: Relation between instruction cycle, machine cycle and T-state

Timing Diagram
Timing diagram is pictorial representation of execution of an instruction with the help of
various control and status signals.
There are seven different types of machine cycles in the 8085A. Three status sin IO/, S1,
and S0 identify each type as shown in below table. These signals are generated at the
beginning of each machine cycle and remained valid for the duration of the cycle.

77
 8085-Timing Diagrams

Machine cycle Status Control

IO/ M S1 S0 RD WRINTA

Opcode Fetch 0 1 1 0 1 1

Memory Read 0 1 0 0 1 1

Memory Write 0 0 1 1 0 1

I/O Read 1 1 0 0 1 1

I/O Write 1 0 1 1 0 1

INTR Acknowledge 1 1 1 1 1 0

Bus Idle 0 0 0 1 1 1

Table: 8085 Machine cycles

Representation of Signals
Before going to see the timing diagram, we will see the signals and their representation
used in the timing diagrams.

Clock Signal
The 8085 divides the clock frequency provided at X1 and X2 inputs by 2, which is called
operating frequency. All the operations within the 8085 are synchronized with this
operating frequency. Therefore, in the timing diagram operating frequency clock is on the
top and then the signals are shown with reference to operating frequency clock. Ideally,
the clock signal should be square wave with zero rise time and fall time, as shown in the
figure. But in practice, we don’t get zero rise time and fall time. Therefore, the clock and
other signals are always shown with finite rise and fall times.

T-State T-State Tf Tr

1 Clock cycle
(a) Ideal (b) Practical
Figure: Clock signal representation

Single Signal
Single signal is represented by a line. It may have status either logic 0 or logic 1 or
tri-state. The change in the state of the signal takes finite time and hence the state
change of signal is represented with finite rise time and fall time, as shown in the Figure.

78
 8085-Timing Diagrams

Logic - 1 Logic - 1

Tri-state
Logic - 0 Logic - 0 Logic - 0

Tr Tf

Figure: Single signal representation

Group of Signals
Group of signals is also called a bus, e.g. address bus and data bus. To avoid
complications in the timing diagram these signal are grouped and shown in figure.

State change State change

Tri-state
Figure: Group of signals representation

In the group representation individual state is not considered, but the group state is
considered. Change in state of single signal changes the state of group. It is represented
by the cross as shown in the above figure. The tri-state condition of the group signals is
shown by dotted lines. Two straight lines represent valid state/stable state.
In microprocessor systems, activation of signal/signals depends on the state of other
signal/signals. Such situations are shown in the timing diagrams with the help of specific
symbols. There are four possibilities:
• Activation of a signal with the change in state of other signal
• Activation of a signal with the change in state of other signals
• Activation of signals with the change in state of other signal
• Activation of signals with the change in state of other signals
Figures show the representation of dependence of the signal/signals in the timing diagram.

Other signal

Activated signal
(a) Activation of signal with the (b) Activation of signal with the
change in state of other signal change in state of other signal

(c) Activation of a signal with the (d) Activation of signals with the
change in state of other signals change in state of other signals

79
 8085-Timing Diagrams

Signal Timings
In 8085 microprocessor, signals are activated at a specific instant for a specific time period.
Once we understand this, it is very easy to draw timing diagrams. The following section
explains when the signals are activated and for what period they remain in active state.

ALE (Address Latch Enable)

This signal is an active high signal. It is activated in the beginning of the T1 state of each
machine cycle, except bus idle machine cycle, and it remains active in the T1, state as
shown in the figure.

Machine cycle 1 Machine cycle 2

T1 T2 T3 T4 T1 T2 T3

ALE

Figure: ALE activation and its period

A0 − A7 (Lower Byte Address)

The lower byte of address is available on the multiplexed address/data bus (AD0 − AD7)
during T1 state of each machine cycle, except bus idle machine cycle, as shown in figure.

Machine cycle 1 Machine cycle 2

T1 T2 T3 T4 T1 T2 T3

AD0 − AD7 A0 − A1 A0 − A7

Figure: Lower address on the multiplexed bus

D0 − D7 (Data Bus)
The data from memory or I/O device and from microprocessor to memory or I/O device
is transferred during T2 and T3-states. It is important to note that in read machine cycle,
data will appear on the data bus during the later part of the T2-state, as shown in the
figure, whereas in write cycle data will appear on the data bus at the beginning of the T2
state, as shown in the figure.

80
 8085-Timing Diagrams

T1 T2 T3 T1 T2 T3

Address Data Address Data

Figure: Data Bus

To read data from memory or I/O device, it is necessary to select memory or I/O device.
After selection, device will put the data from selected location on the data bus. This
action needs finite time. This time is referred to as access time. In case of write cycle,
data is available in the registers of the microprocessor and it can put that data on the
data bus with zero access time.

A8 − A15 (Higher Byte Address)

The higher byte of address is available on the A8 - A15 bus during T1, T2, and T3-states of
each machine cycle, except bus idle machine cycle, as shown in figure.

T1 T2 T3 T4 T1 T2 T3

A8 - A15 A8 - A15 A8 - A15

Figure: Higher byte address on A8 − A15

IO/ M , S0, S1

Machine cycle 1 Machine cycle 2

T1 T2 T3 T4 T1 T2 T3

IO/M = 0 S0 = 1, S2 = 1 IO/M = O, S0= 0, S2 = 1

Opcode fetch Memory Read

Figure: Status signal

81
 8085-Timing Diagrams

These signals are called status signals. They decide the type of machine cycle to be
executed. They are activated at the beginning of T1 state of each machine cycle and
remain active till the end of the machine cycle.

RD and WR
These signals decide the direction of the data transfer. When RD signal is active, data
is transmitted from memory or I/O device to the microprocessor, and when WR signal
is active, data is transmitted from microprocessor to the memory or I/O device. Both
signals are never active at the same time.
As we know data transfer in 8085 takes place during T2 and T3, these signals are
activated during T2 and T3, as shown in the Figure.

Read cycle Read cycle

T1 T2 T3 T1 T2 T3

RD

WD

Figure: RD and WR Signals

Machine Cycle
It is defined as the time required to access either memory or Input-Output or it is also
equivalent to the time required to transfer a data byte to memory or Input-Output. One
machine cycle may contain 3 to 6 T-States:
Processor only does this 5 operations:
(1) Opcode (Fetch)
(2) mr (Memory Read)
(3) mw (Memory Write)
(4) IOR (Input-Output Read)
(5) IOW (Input-Output Write)

(1) Opcode Fetch Cycle

The first machine cycle of every instruction is opcode fetch cycle in which the
8085 finds the nature of the instruction to be executed. In this machine cycle,
processor places the contents of the Program Counter on the address lines, and
through the read process, reads the opcode of the instruction. Figure (a) shows
flow of data (opcode) from memory to the microprocessor and figure (b) shows the
timing diagram for opcode fetch machine cycle. The length of this cycle is not fixed.
It varies from 4T states to 6T states as per the instruction. The following section
describes the opcode fetch cycle in step-by-step manner.

82
 8085-Timing Diagrams

Step 1:
(State T1) In T1 state, the 8085 places the contents of program counter on the address
bus. The high-order byte of the PC is placed on the A8-A15 lines. The low-order byte of the
PC is placed on the AD0- AD7 lines which stays on only during T1. Thus, microprocessor
activates ALE (Address Latch Enable) which is used to latch the low-order byte of the
address in external latch before it disappears.

IR data

Instruction B C
register
D E
(IR)
H L
SP
PC
Instruction
decoder
(IR)

AD7 AD0

Timing ALE
and Latch
control
A7 A0

Memory

A15 A8

Memory
read
Data bus

Indicates data flow, Indicates address flow

(a) Data (Opcode) Flow from Memory to Microprocessor

In T1, 8085 also sends status signals IO/M, S, and So. IO/M, S1 and S0. IO/specifies
whether it is a memory or I/O operation, S1, status specifies whether it is read/write
operation; S1 and S0 together indicates read, write, opcode fetch, machine cycle
operation, or whether it is in HALT state. In opcode fetch machine cycle status signals
are: I0/M = 0, S1 = 1

83
 8085-Timing Diagrams

Opcode Fetch

T1 T2 T3 T4

CLK

A15
High order memory address Unspecified
A8

AD7
Low order Opcode
AD0
Memory address

ALE

I0/M Status IO/M = 0, S0 = 1, S1 = 1 Opcode fetch

RD

(b) Opcode Fetch Machine Cycle

Step 2:
(State T2) In T2, low-order address disappears from the AD0 – AD7 lines. (However A0 – A 7
remain available as they were latched during T1). In T2 8085 sends signal low to enable
the addressed memory location. The memory device then places the contents of
addressed memory location on the data bus (AD0- AD7).

Step 3:
(State T3) During T3, 8085 loads the data from the data bus in its Instruction Register and
raises RD to high which disables the memory device.

Step 4:
(State T4) In T4, microprocessor decodes the opcode, and on the basis of the instruction
received, it decides whether to enter state T5 or to enter state T1 of the next machine
cycle. One byte instructions those operate on eight bit data (8 bit operand) are executed
in T4.
For example: MOV A, B, ANA D, ADD B, INR L, DCR C, RAL and many more.

Note: For one byte instructions which operate on eight bit data, data is always
available in the internal memory of 8085 i.e., registers.

84
 8085-Timing Diagrams

Step 5:
(State T5 and T6) State T5 and T6, when entered, are used for internal microprocessor
operations required by the instruction. During T5 and T6 8085 performs stack write,
internal 16 bit, and conditional return operations depending upon the type of instruction.
One byte instructions those operate on sixteen bit data (16 bit operand) are executed in
T5 and T6.
For example: DCX H, PCHL, SPHL, INX H, etc.

(2) Memory Read Cycle

The 8085 executes the memory read cycle to read the contents of R/W memory or
ROM. The length of this machine cycle is 3-T states (T1 – T3). In this machine cycle,
processor places the address on the address lines from the stack pointer, general
purpose register pair or program counter, and through the read process, reads the
data from the addressed memory location. Figure (a) shows flow of from memory
to the microprocessor and figure (b) shows the timing diagram for memory read
machine cycle. Memory read machine cycle is similar to the opcode fetch machine
cycle. However, they use only states T1 to T3 and the status signal values (IO/M = 0,
S1 = 1, S0 = 0) appropriate for memory read machine cycle are issued in T1. The
following section describes the memory read machine cycle in step-by-step manner.

IR data

Instruction B C
register
(IR) D E
H L
SP
Instruction
PC
decoder
(IR)

AD7 AD0
Timing and ALE
Latch
control

A7 A0
Memory

A15 A8

Memory
read
Data bus

Indicates data flow, Indicates address flow,

Figure (a) Data flow from memory to the microprocessor

85
 8085-Timing Diagrams

Memory read
T1 T2 T3

CLK

A15 − A8 Memory address

ALE

AD7 − AD0 A 7 − A0 Data from memory

IO/M, S1, S0 IO/M = 0, S1 = 1, S0 = 0

RD

Figure (b) Memory read machine cycle

Step 1:
(State T1) In T1 state, microprocessor places the address on the address lines from stack
pointer, general purpose register pair or program counter and activates ALE signal in
order to latch low-order byte of address. During T1 8085 sends status signals: IO / M = 0,
S1 = 1, and S0 = 0 for memory read machine cycle.

Step 2:
(State T2) In T2 8085 sends RD signal low to enable the addressed memory location. The
memory device then places the contents of addressed memory location on the data bus
(AD0 − AD7).

Step 3:
(State T3) During T3, 8085 loads the data from the data bus into specified register (F, A, B,
C, D, E, H, and L) and raises RD to high which disables the memory device.

86
 8085-Timing Diagrams

(3) Memory Write Cycle

The 8085 executes the memory write cycle to store the data into memory or stack
memory. The length of this machine cycle is 3T states (T1 – T3). In this machine
cycle, processor places the address on the address lines from the stack pointer or
general purpose register pair and through the write process, stores the data into
the addressed memory location. Below figure shows the timing diagram for memory
write machine cycle. The memory write timing diagram is similar to the memory
read timing diagram, except that instead of RD, WR signal goes low during T2 and T3.
The status signals for memory write cycle are : IO/M = 0, S1 = 0 S0 = 1. The following
section describes the memory write machine cycle in a step- by- step manner.

Step 1:
(State T1) In T1, state, the 8085 places the address on the address lines from stack
pointer or general purpose register pair and activates ALE signal in order to latch low-
order byte of address. During T1 8085 sends status signals:
IO/M = 0, S1 =0 and S0 = 1 for memory write machine cycle.

Step 2:
(State T2) In T2 8085 places data on the data bus and sends WR signal low for writing into
the addressed memory location.

Step 3:
(State T3) During T3, WR signal goes high, which disables the memory device and
terminates the write operation.
IR data

Instruction B C
register D E
(IR)
H L
SP
Instruction PC
decoder
(ID)
AD7 AD0
ALE
Timing and Latch
control
A7 A0
Memory

A15 A8

Memory
read Data bus

Indicates Indicates address flow

data flow,

Figure (a) Data flow from memory to the microprocessor

87
 8085-Timing Diagrams

T1 T2 T3

CLK

A15 − A8 Memory address

Figure (b) Memory write

machine cycle
ALE

AD7 − AD0 A 7 − A0 Data from memory

IO/M, S1, S0 IO/M = 0, S1 = 1, S0 = 0

RD

(4) 4.5. I/O Read and I/O Write Cycles

The I/O read and I/O write machine cycles are similar to the memory read and
memory write machine cycles, respectively, except that the IO/M signal is high
for I/O read and I/O write machine cycles. High IO/signal indicates that it is an I/O
operation. Figure 1 (b) and Figure 2 (b) show the timing diagrams for I/O read and I/O
write cycles, respectively.

A B C
IR
D E
H L
SP
PC
Figure 1: (a) Data (opcode) flow
from memory to ID
microprocessor
AD7 AD0
ALE
Timing and Latch
control

A15 − A8

Output OR
device
A7 − A0
I/O
write Data bus

Indicates
Indicates address flow,
data flow,

88
 8085-Timing Diagrams

T1 T2 T3

CLK

ALE

Figure 2: (b) I/O read

memory cycle
A15 − A8 I/0 Addr

AD7 − AD0 I/0 Addr Data from MPU

WR

IO/M, S1, S0 IO/M = 1, S1 = 0, S0 = 1

B C
A IR D E
H L
SP
PC
ID

Figure 2: (a) Data flow

microprocessor to output AD7 AD0
device
Timing and ALE
Latch
control

A15 − A8

Output OR
device
A 7 − A0
I/O
write Data bus

Indicates data flow, Indicates address flow,

89
 8085-Timing Diagrams

I/0 Write

T1 T2 T3

CLK

ALE

A15 − A8 I/0 Addr

AD7 − AD0 I/0 Addr Data from MPU

WR

IO/M, S1, S0 IO/M = 0, S1 = 0, S0 = 1

(b) I/O Write machine cycle

Concept of Wait States

In some applications, speed of memory system and I/O system are not compatible with
the microprocessor’s timings. This means that they take longer time to read/write data.
In such situations, the microprocessor has to confirm whether a peripheral is ready to
transfer data or not. If READY pin is high, the peripheral is ready otherwise 8085 enters
wait state. Below figure shows the timing diagram for memory read machine cycle with
and without wait state. Wait states continue to be inserted as long as READY is low.
After the wait state, 8085 continues with T3 of the machine cycle. During a wait state
the contents of the address bus, the data bus, and the control bus are all held constant.
The wait state then gives an addressed memory or I/O port an extra clock cycle time
to output valid data on the data bus. This feature allows to use cheaper memory or I/O
devices that have longer access times.

90
 8085-Timing Diagrams

MR or IOR MR or IOR
T1 T2 T3 T1 T2 TWAIT T3

CLK

I0/M
I0/M= 0 (MR) OR 1 (I0R), S1 = 1, S0 = 0 I0/M = 0(MR) OR 1 (I0R), S1 = 1, S0= 0
S1, S0

A8 − AD7

OUT IN OUT IN
AD0 − AD15 A0 − AD7 D0 − D7 A0 − A7 D0 − D7

ALE

RD

READY

Figure: Read machine cycle with and without wait state

State Diagram of 8085

Now we study the state diagram of 8085 as shown in figure.
Intel 8085 starts in Treset state at power on. In this state
• Halt flip-flop reset to 0
• The HLDA flip-flop is reset to 0. It results in the HLDA output of 8085 becoming 0
• The INTE flip-flop is reset to 0. It disables the RST 7.5, RST 6.5, RST 5.5 and INTR .
The output of 8085 becoming 1
• PC (Program Counter) is reset to 0. So 8085 fetches. First instruction from address
0000H after reset

T1 State
When reset-in becomes inactive, the 8085 enters the state T1. This is the first clock cycle
of a machine cycle. At the end of T1, if the HALT flip-flop status is 0, it enters state T2
otherwise it will enter into Thalt state.

T2 State
At the end of T2
• If the ready input of 8085 is 0 and the machine cycle is not a BI machine cycle then
the 8085 enters Twait state

91
 8085-Timing Diagrams

Note: Intel 8085 executes a BI machine cycle only for DAD instruction or when it
is required to respond to a vector interrupt.
• If the ready input of 8085 is 1 or the machine cycle is a BI machine cycle, then 8085
checks the HOLD input. If the HOLD input is not active, 8085 enters T3 state. If the
HOLD input is active, 8085 sets the HLDA flip-flop and enters the T3 state.

Treset

Reset in

T1 Hold . Valid Int

Halt
Ready . BT
T2 Twalt Twalt
Valid
Ready + interrupt
BI Ready
HLDA F/F = 1 Halt F/F = 0
Y
HOLD - 1

HLDA F/F = 1
N

T3 OF 6 CLK
T4
OF 4 CLK
N Y
HLT in IR HOLD = 1

Y N HLDA F/F = 1
HALT F/F = 1
T6 T5
HCDA F/F Y
=1

N Activate
HLDA
N Last M/C
cycle of
insth Thold
Y

N Valid
interrupt

Y
Reset INTE F/F

Y Valid HLDA F/F = 0

vector Deactivate HLDA
interrupt

N
Set INTA F/F

92
 8085-Timing Diagrams

TWait State
As long as the ready input remains 0, the 8085 remains in TWait state. When the ready
input becomes 1, 8085 comes out of TWait state.

T3 State
If it is a first machine cycle of an instruction (opcode fetch (OF) machine cycle), the 8085
enters T4 state from T3. If it is not an opcode fetch machine cycle, it checks the status of
the HLDA flip-flop.

T4 State
At the end of T4:
• If it is a six-clock machine cycle, the 8085 again checks the HOLD input. If the
HOLD input is not active, the 8085 enters T5 state. If the HOLD is active, the 8085
sets the HLDA flip-flop and then enters T5 state.
• If it is a four-clock machine cycle, in the last clock cycle, 8085 checks if the code
for HLT instruction is in the IR. If yes, the 8085 sets the HALT flip-flop, and then
checks the status of HLDA flip-flop. If the IR is not having the code for HLT, the
8085 directly checks the status of the HLDA flip-flop.

T5 State
From state T5, 8085 enters state T6. At the end of T6, the HLDA flip-flop status is checked.

Status of HLDA Flip-Flop

In all the states, status of HLDA flip-flop is checked at the end of:
• T3 for MR, MW, IOR, IOW, INTA and BI machine cycles
• T4 for OF machine cycle with four-clock cycles
• T6 for OF machine cycle with six-clock cycles
If the HLDA flip-flop is set, the 8085 activates the HLDA output pin and enters Thold state.
If HLDA flip-flop is in reset condition, then the 8085 finds out if it is the last machine
cycle for the current instruction. If it is not the last machine cycle, the 8085 begins the
next machine cycle by entering T1 state again.

Last Machine Cycle

If it is a last machine cycle, it means the current instruction execution is complete. Then
it checks for any valid interrupts. If there are no valid interrupt requests, the 8085 goes
ahead with the next instruction cycle by entering T1 state again.

Valid Interrupt
If there is any valid interrupt at the end of an instruction cycle, the 8085 resets the
INTE flip-flop. This ensures that the execution of ISR can proceed without any further
interrupts. Then 8085 checks to find out if INTR is the only valid interrupt. If yes, it

93
 8085-Timing Diagrams

sets the INTA flip-flop that activates INTA output pin. Then the 8085 goes ahead with
receiving a 3-byte CALL instruction, or a 1-byte RSTn instruction from an I/O device, by
entering the T1 state of an INTA machine cycle. If an interrupt other than INTR is a valid
interrupt, the 8085 directly goes ahead with BI machine cycle, by entering T1 state again.

Thalt State
At the end of T1 if HALT flip-flop status is 1, the 8085 enters state Thalt. If the HOLD input
remains inactive and there is no valid interrupt request, the 8085 remains in Thalt. It
leaves the Thalt state in case of a valid interrupt or active HOLD input.
If the HOLD input becomes active during Thalt the 8085 sets the HLDA flip-flop, and
activates the HLDA output pin and enters Thold state. As discussed earlier, the 8085
remains in the Thold state as long as the HOLD input is active. When the HOLD input is
deactivated, it comes out of the HOLD state and resets the HLDA flip-flop. Then the
8085 re-enters Thalt state from T1 state.
If a valid interrupt becomes active during Thalt the 8085 resets the HALT, and INTE flip-
flops. This ensures that the 8085 has come out of the halt state, and the execution of
ISR can proceed without any further interrupts.

Thold State
It remains in the Thold state as long as the HOLD input is active. When the HOLD input
is deactivated, the 8085 comes out of the HOLD state and resets the HLDA flip-flop.
Then the 8085 goes ahead with the first clock cycle for the next machine cycle in the
instruction by entering state T1.

Instruction Cycle
It is the time required to complete the execution in instruction. One instruction cycle
may contain 1 to 5 machine cycles

• =
IC IFC + EC

•=
IC1B OPFC + EC

• IC2B = OPFC + mr1C + EC

• IC3B = OPFC + mr1C + mr2C + EC

Execution
• Internal 8 bit operation will be performed during T4 of OPFC
• Internal 16 bit operation requires two clock cycle extra (2T state)
• External 8 bit operation [MWC, MRC, IOWC, IORC] requires 3T state

94
 8085-Timing Diagrams

ICs for Data Transfer Instructions

MVI A, 24H ⇒ 2 Byte instruction
⇒ OPFC + mrc
⇒ 2MC = 4T + 3T = 7T states
MVI M, 88H ⇒ 2 Byte instruction
⇒ OPFC + mrc + Mwc
⇒ 3MC = 4T + 3T + 3T = 10T states
LXI SP, 2800H ⇒ 3 Byte instruction
⇒ OPFC + mr1c + mr2c
⇒ 3MC = 4T + 3T + 3T = 10T states
MOV A,B ⇒ 1 Byte instruction
⇒ OPFC
⇒ 1MC = 4T states
SPHL ⇒ 1 Byte instruction
⇒ OPFC + 2T-[Extra 2T states required]
⇒ 4T + 2T = 6T [Special OPFC]

Note:
• Op-code fetch MCs are of 2 types
• Normal OPFC = 4T
• Special OPFC = 6T
PCHL ⇒ 1 Byte instruction
⇒ OPFC + 2T
⇒ 6T states

XCHG ⇒ 1 Byte instruction

⇒ OPFC + 2T
⇒ 6T states

OUT F8H ⇒ 2B
⇒ OPFC + mr1c + IOW
⇒ 3MC = 4T + 3T + 3T = 10T states

IN F9H ⇒ 2B
⇒ OPFC + mc + IOR
⇒ 3MC = 4T + 3T + 3T = 10T states

95
 8085-Timing Diagrams

MOV M, B ⇒ 1 Byte instruction

⇒ OPFC + MWC
⇒ 2MC = 4T + 3T = 7T states

MOV A, M ⇒ 1 Byte instruction

⇒ OPFC+MRC
⇒ 2MC = 4T + 3T = 7T states

STAX B ⇒ 1 Byte instruction

⇒ OPFC + MWC
⇒ 2MC = 4T + 3T = 7T states

LDAX D ⇒ 1 Byte instruction

⇒ OPFC + MRC
⇒ 2MC = 4T + 3T = 7T states

STA 2000H ⇒ 3 Byte instruction

⇒ OPFC + mr1c + mr2c + MWC
⇒ 4MC = 4T + 3T + 3T + 3T = 13T states

LDA 2001H ⇒ 3 Byte instruction

⇒ OPFC + mr1c + mr2c + MWC
⇒ 4MC = 4T + 3T + 3T + 3T = 13T states

SHLD 4520H ⇒ 3 Byte instruction

⇒ OPFC + mr1c + mr2c + MW1C + MW2C
⇒ 5MC = 4T + 3T + 3T + 3T + 3T = 16T states

LHLD 6000H ⇒ 3 Byte instruction

⇒ OPFC + mr1c + mr2c + MR1C + MR2C
⇒ 5MC = 4T + 3T + 3T + 3T + 3T = 16T states

PUSH B ⇒ 1 Byte instruction

⇒ OPFC + MW1C + MW2C
⇒ 3MC = 4T + 2T + 3T + 3T = 12T states

POP D ⇒ 1 Byte instruction

⇒ OPFC + MR1C + MR2C

96
 8085-Timing Diagrams

⇒ 3MC = 4T + 3T + 3T = 10T states

XTHL ⇒ 1 Byte instruction

⇒ OPFC + MR1C + MR2C + MW1C + MW2C
⇒ 5MC = 4T + 3T + 3T + 3T + 3T = 16T states

ICs for Arithmetic & Logical Instructions

ADD B ⇒ 1 Byte instruction
⇒ OPFC
⇒ 1MC = 4T states
• ADC H, SUB B, SBB, INRH, DCR C, DAA, ANA B, ORA C, RAL, RLC, RAR, RRC

ADDM ⇒ 1 Byte instruction

⇒ OPF + MRC
⇒ 2MC = 4T + 3T = 7T states

• ADO M, SUB M, SBB M, ORA M, XRA M, CMP M

ADI 84H ⇒ 2B
⇒ OPFC + mr1c
⇒ 2MC = 4T + 3T = 7T states
• ACI F4H, SUI 44H, SBI 20H, ORI 40H, ANI 00H, XRI 10H, CPI 11H

DAD H ⇒ 1 Byte instruction

⇒ OPFC + BIC + BIC
⇒ 3MC = 4T + 3T + 3T = 10T
• BIC = Bus ideal cycle

INX B, DCX H ⇒1 Byte instruction

⇒ OPFC + 2T
⇒ 1MC = 4T + 2T = 6T states

INR M ⇒ 1 Byte instruction

⇒ OPFC + MRC + MWC
⇒ 3MC = 4T + 3T + 3T = 10T states

97
 8085-Timing Diagrams

ICs for Program Transfer Instructions

JMP 1000H ⇒ 3 Byte instruction
⇒ OPFC + mr1c + mr2c
⇒ 3MC = 4T + 3T + 3T = 10T

JNC 1000H ⇒ 3 Byte instruction

→ mr2c
⇒ OPFC + mr1c + [Variable machine cycle]
→X

Test result is true = 10T states

Test result is false = 7T states

• JC 1001H, JPE 1200H, JPO Delay, JNZ 1010H, JZ 1210H, JP 1001H, JM 2100H

CALL 1641H ⇒ 3 Byte instruction

⇒ OPFC + mr1c + mr2c + 2T + Mw1c + Mw2c
⇒ 4T + 3T + 3T + 2T + 3T + 3T = 18T states

RST 1 ⇒ 1 Byte instruction

⇒ OPFC + 2T + Mw1c + Mw2c
⇒ 4T + 2T + 3T + 3T = 12T states

• RST 0, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7

CNC 1500H ⇒ 3 Byte instruction

→ mr2c + Mw1c + Mw2c
⇒ OPFC + 2T + mr1c +
→X

Test result is true = 18T states

Test result is false = 9T states

• CC 1000H, CPE 1100H, CPO Delay, CNZ 1010H, CZ 1111H, CP 1212H, CM LOOP
RET ⇒ 1 Byte instruction
⇒ OPFC + MR1C + MR2C
⇒ 4T + 3T + 3T = 10T states

RNC ⇒ 1 Byte instruction

→ MR1C + MR2C
⇒ OPFC + 2T +
→X
Test result is true = 12T states
Test result is false = 6T states
• RC, RPE, RPO, RNZ, RZ, RM, RP

98
 8085-Timing Diagrams

ICs of M.C. Instructions

HLT ⇒ 1 Byte instruction
⇒ OPFC + 1T-[BIC]
⇒ 2MC = 4T + 1T = 5T states

NOP ⇒ 1 Byte instruction

⇒ OPFC
⇒ 4T states
• EI, DI, SIM, RIM

Note: Maximum number of T-States possible for an instruction in 8085 is 18

Timing Diagram
It is a representation of the various control signals generated during execution of an
instruction.
Following Buses and control signals must be shown in the timing diagram

• High order address buses

• Lower order address/data buses
• ALE
• RD
Instruction cycle
A15 Memory read
• WR Op-code fetch
T1 T2 T3 T4 T5 T6 T7
• IO / M
µs
0.33µ
E.g.: 6000 H: MVI A, 99H
ALE

A15 − A8 60H Unknown 60H

AD7 − AD0 Z
00H XX 01H 99H

IO/M, IO/M = 0 S1 = 1, S0 = 0
IO/M = 0 S1 S0 = 1
S1 S0

Steps RD
(1) Fetch
(2) Decode
(3) Execute
• Machine cycle: (here 2-machine cycle)

99
 8085-Timing Diagrams

(1) Op-code fetch

(2) Memory read

• 7 T-States
• For any instruction to be executed, the first machine cycle is op-code fetch which
may be of 4 or 6 T-State.

T1 State
• ALE = 1 (high) is indicating all 16 lines act as address buses
• A15 − A8 contain higher byte address present in program counter (PC)
• AD7 − AD0 contain lower byte of PC
• IO / M = 0 indicates memory operation
• S1 = S0 = 1 for fetch

• RD = 1, inactive as there is no ‘data bus’ available

T2 State
• As ALE becomes low, AD7 − AD0 act as data bus
• When RD is activated, op-code from the memory location is access onto data bus.

T3 State
• Op-code from the data bus is accessed into the instruction register (IR)

Note: It require 2T-States to access either an op-code or data byte from a

memory location into a processor after the address is latched.

T4 State
• The op-code is decoded (D) and execution may also be completed for some
instruction like MOV A, B; but when the instruction is considered a memory read,
operation is required
• Status of higher order bus (address) is unknown

Memory Read
T5 State
• ALE is high in order to point to the next memory location
• T6 and T7 are similar to fetch except that S1 = 1, S1 = 0, for memory use.
• 99H is accessed into Accumulator (A) in T6 and T7 for the instruction given.

100
 8085-Timing Diagrams

Conclusion
• Length of instruction = 2 byte
• No. of machine cycles = 2 (F, R)
• Total T-State = 7 (F → 4, R → 3)
• Total execution time = count period × no. of T-State × count value

1 1
= × T - States × C.V = × 7 × 1= 2.31 µ sec
fclk 3 × 106

T-State

Min Max
Fetch 4 6
Machine cycle 3 6
Instruction 4 18

Note:
• The number of machine cycles required for the execution of an instruction may or
may not be equal to the length of the instruction
• ALE is high in first T-State of a machine cycle

101
 8085-Timing Diagrams

102
 Memory and I/O Interfacing

Chapter 6
Memory and I/O Interfacing
Objective
Upon completion of this chapter, you will be able to understand:
• Memory Interfacing
• I/O mapped I/O
• Memory mapped I/O techniques

Introduction:
Memory is an integral part of a microprocessor system, and in this chapter, we will
discuss how to interface a memory device with the microprocessor. The memory
interfacing circuit is used to access memory quite frequently in order to read instruction
codes and data stored in the memory. This read/write operations are monitored by
control signals. The microprocessor activates these signals when it wants to read
from and write into memory. In this chapter we will see memory structure and its
requirements, concepts in memory interfacing and interfacing examples.

Types of Memory
The internal memory is a semiconductor random access memory.
Classification of Memory

Memory

Read only Memory (ROM) Read/Write Memory (RAM)

Masked ROM PROM EPROM EEPROM Static RAM Dynamic RAM

The Two Basic Forms of Read /Write Memory are:

(1) Static RAM (SRAM)
(2) Dynamic RAM (DRAM)

103
 Memory and I/O Interfacing

Static RAM (SRAM)

Static RAM Memories that consist of circuits capable of retaining their state as long as
power is applied are known as static memories. These are Random Access Memory (RAM)
and hence called static RAM memories.

Dynamic RAM (DRAM)

Dynamic RAM stores the data as a charge on the capacitor. A dynamic RAM contains
thousands of such memory cells.

Comparison between SRAM and DRAM

Sr.No. Static RAM Dynamic RAM

Static RAM contains less memory cells per unit Dynamic RAM contains more memory cells as
1
area compared to static RAM per unit area

2 It has less access time hence faster memories Its access time is greater than static RAM's

Dynamic RAM stores the data as a charge on

Static RAM consists of number of flip-flops.
3 the capacitor. It consists of MOSFET and the
Each flip-flop stores one bit
capacitor for each cell

Refreshing circuitry is required to maintain the

charge on the capacitors after milliseconds.
4 Refreshing circuitry is not required
Extra hardware is required to control refreshing.
This makes system design complicated

5 Cost is more Cost is less

Read only Memories (ROM)

We can’t write data in Read Only Memories (ROM). It is a non-volatile memory i.e., it can
hold data even if power is turned off.
Generally, ROM is used to store the binary codes for the sequence of instructions data
such as look up tables. This is because this type of information does not change. ROMs
are also accessed randomly with unique addresses. In the below figure shows the typical
configuration of a ROM cell. It consists of a transistor T and switch P. The transistor T is
driven by the word line. The contents can be read from the cell when the word line is
logic 1. A logic value 0 is read if the transistor is connected to the ground through switch
P. If switch P is open, a logic value 1 is read. The bit line is connected through a resistor
to the power supply. A sense circuit at the end of the bit line generates the proper
output value. Data is stored into a ROM when it is manufactured.
There are four types of ROM: Masked ROM, PROM, EPROM and EEPROM or EEPROM.

104
 Memory and I/O Interfacing

Bit Line Vcc

Word Line

T P Open: Data Stored (Logic 1)

Close: Data Stored (Logic 0)

Figure: ROM cell

PROM (Programmable Read Only Memory)

PROMS are programmed by user. To provide the programming facility, each address is
selected and the data line intersection has its own fused MOSFET or transistor. When
the fuse is intact, the memory cell is configured as logic 1 and when the fuse is blown
(open circuit), the memory cell is logical 0. Logical 0s are programmed by selecting the
appropriate select line and then driving the vertical data line with a pulse of high current.
The figure shows a PROM fused MOSFET memory cell.
The fuse uses materials like nichrome and polycrystalline. For blowing the fuse it is
necessary to pass around 20 to 50 mA of current for a period of 5 to 20 µs. The blowing
of fuses according to the truth table is called programming of ROM. The PROMS are one
time programmable. Once programmed, the information stored is permanent.

Vcc

Address Line

Fuse Data Line

PROM Memory Cell

EPROM (Erasable Programmable Read Only Memory)

Erasable programmable ROMS use MOS circuitry. They store 1s and 0s as a packet of
charge in a buried layer of the IC chip. EPROMS can be programmed by the user with a
special EPROM programmer.
The important point is that we can erase the stored data in the EPROMSs by exposing
the chip to ultraviolet light through its quartz window for 15 to 20 minutes. It is not
possible to erase selective information, when erased the entire information is lost.

105
 Memory and I/O Interfacing

The chip can be reprogrammed. This memory is ideally suitable for product development,
experimental projects and college laboratories, since this chip can be reused many times.

EEPROM (Electrically Erasable Programmable Read Only Memory)

Electrically erasable programmable ROMs also use MOS circuitry very similar to that of
EPROM.
Data is stored as charge or no charge on an insulated layer or an insulated floating gate
in the device.
The insulating layer is made very thin (< 200 Ǻ). Therefore, a voltage as low as 20 to 25 V
can be used to move charges across the thin barrier in either direction for programming
or erasing. EEPROM allows selective erasing at the register level rather than erasing all
the information since the information can be changed by using electrical signals. The
EEPROM memory also has a special chip erase mode by which entire chip can be erased
in 10ms. This time is quite small as compared to the time required to erase EPROM. It
can be erased and reprogrammed with the device right in the circuit.

Disadvantage
EEPROMS are most expensive and are the least dense ROMs.

Memory Interfacing
Memory location = 2Number of address i/p lines
• A memory with n address i/p lines will have 2n bytes
• Number of address i/p lines is going to decide the memory
E.g.: For 10 address line, 210 bytes = 1KB memory

Memory Mapping
Given names to or addressing memory location is known as memory mapping, Memory
map indicates starting and ending and the range of a memory chip.

Calculating Starting and Ending Address for a Memory Chip

Step-1: Find the no. of address lines according to the capacity of memory.
Step-2: Put equivalent no. of 1s as that of address line and find the hexadecimal value
that must be added or subtracted to get ending or starting address.

106
 Memory and I/O Interfacing

Solved Examples
Problem: Find the memory map for given interfacing logic

A15
A14
A13
A12
A11
A10
CS RD WR
A0
.
.
. 1 KB
.
. n = 10
.
.
.
A9

Solution: For chip select, NAND gate output must be zero, it happens only when

A 15 A 14 A 13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A 1 A0

1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 = AB00H
1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 = ABFFH

Hence AB00 to ABFFH

Problem: Find the memory map for given interfacing logic

A15
A14

A13
A12
A11
CS RD WR
A0
.
.
. 2 KB
.
. 11 address line
.
.
.
.
A10

107
 Memory and I/O Interfacing

Solution: For chip select, NAND gate output must be zero. It happens only when

A 15 A 14 A 13 A 12 A 11 A 10 A9 A8 A 7 A6 A5 A 4 A 3 A 2 A 1 A0
1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 = 8800H
1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 = 8FFFH

Hence 8800H to 8FFFH

Problem: Find the ending address of a 4KB ROM if starting address is C3A9H
Solution:
4 KB = 12 address line [4KB = 212 ⇒ n = 12]

C3A9 → Starting address

+ 0FFF
D3A8 → Ending address

Problem: Calculate the starting address for a 8KB RAM if ending address is 60AB H
Solution:
8 KB = 13 address line [8KB = 213 ⇒ n = 13]

60AB → Starting or ending address

−1FFF
40AC → Starting address

Problem:

A15

A14

E Y0

Y1
A13 C A0 CS
Y2
Y3 2 KB
A12 B
Y4 RAM
Y5 A10
A11 A
Y6
Y7

Find starting and ending address

108
 Memory and I/O Interfacing

Solution:

C B A O/P

A13 A12 A11

1 0 0 Y4

A 15 A 14 A 13 A 12 A 11 A 10 A9 A8 A 7 A6 A5 A 4 A 3 A 2 A 1 A0
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = A000H
1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 = A7FFH

Address Mapping Techniques

The processor identifies an I/O device as one of two types:
(1) I/O mapped I/O
(2) Memory mapped I/O

I/O Mapped I/O

• I/O devices are treated by the microprocessor as I/O devices
• I/O address space is separately available and distinct from memory address space
• I/O devices are recognized with 8 bit port addresses and hence the microprocessor
can differentiate between location and I/O devices

Memory Mapped I/O Techniques

• Memory devices are treated by the microprocessor as memory address
• I/O address space is a part of memory address space i.e., a portion of memory
space is allowed for I/O devices
• I/O devices are recognized with 16 bit addresses and hence the microprocessor
can’t differentiate between memory location I/O devices

I/O Mapped I/O Memory Mapped I/O

• In this device address is 16-bit. Thus, A0 • In this I/O device address is 8-bit. Thus,
to A15 lines are used to generate device A0 to A7 or A8to A15 lines are used to
address generate device address

• I/O has 8-bit port address • I/O has 16-bit address

• 28 → 256; 256 I/P and 256 O/P devices • 216 → 65,536; Address are shared
are possible between memory and I/O

109
 Memory and I/O Interfacing

• Instruction used: • Instruction used:

IN 8 bit port address LDA 16 bit address
OUT 8 bit port address STA 16 bit address
(All arithmetic instruction related to
memory, ADDM, SUB M….)

• Control signals, • Control signals,

MEMR, IOR, IOW MEMR, MEMW

110
 DMA (Direct Memory Access)

Chapter 7
DMA (Direct Memory Access)
Objective
Upon completion of this chapter, you will be able to understand:
• Hardware Controlled Data Transfer
• Data Transfer Modes of DMA

Introduction:
In microprocessor-based systems data transfer can be controlled by either the software
or the hardware. Up till this point we have used program instructions to transfer data
from I/O device to memory or from memory to I/O device. To transfer data by this
method, the microprocessor has to do following tasks:
(1) Fetch the instruction
(2) Decode the instruction and
(3) Execute the instruction
To carry out these tasks, the microprocessor requires considerable time, so this method
of data transfer is not suitable for large data transfers such as data transfer from
magnetic disk or optical disk to memory. In such situations hardware-controlled data
transfer technique is used.

Software Controlled Data Transfer

In this method, the programmer executes a series of instructions to carry out data
transfer. The sample flow chart and program required to transfer data from memory to
I/O device is shown in the figure.

111
 DMA (Direct Memory Access)

Start

Initialization Counter
Initialize Source Pointer

Initializes Part Address

Get byte

Send byte

No
Last byte
?

Yes

Stop

Flowchart

Program
Transfer Subroutine
LXI H, 6000H
BACK: MOV A, M
OUT PA
MOV A, L
CPI 20H
JNZ BACK
RET

112
 DMA (Direct Memory Access)

Hardware Controlled Data Transfer

In this technique, an external device is used to control data transfer. The external device
generates the address and controls signals required to control data transfer and allows
the peripheral device to directly access the memory. Hence, this technique is referred to
as Direct Memory Access (DMA) and the external device which controls the data transfer
is referred to as DMA controller. The figure shows that how the DMA controller operates
in a microprocessor system.

Address
X
AD0 − AD15 Bus
Latches
ALE Y Data
X
Microprocessor Bus
Data Bus Memory
Y
IOR, IOW, X
HLDA HOLD
MEMR, MEMW
HRQ Y Control
DMA Bus
HLDA Controller Peripheral
Control
Bus device (Disk
DRQ Controller)

DACK
Operation of DMA Controller in a Microprocessor System

DMA Ldle Cycle

When the system is turned on, the switches are in the A position, so the buses are
connected from the microprocessor to the system memory and peripherals. The
microprocessor then executes the program until it needs to read a block of data from
the disk. To read a block of data from the disk, the microprocessor sends a series of
Commands to the disk controller device telling it to search and read the desired block
of data from the disk. When the disk controller is ready to transfer the first byte of
data from disk, it sends a DMA request DRQ signal to the DMA controller. Then the DMA
controller sends a hold request HRQ signal to the microprocessor HOLD, input. The
microprocessor responds to this HOLD signal by floating its buses and sending out a hold
acknowledge signal HLDA, to the DMA controller. When the DMA controller receives
the HLDA signal, it sends a control signal to change the switch position from A to B. This
disconnects the microprocessor from the buses and connects the DMA controller to the
buses.

DMA Active Cycle

When the DMA controller gets control of the buses, it sends the memory address
from where the first byte of data from the disk is to be written. It also sends a DMA
acknowledge DACK signal to the disk controller device telling it to get ready for data
transfer. Finally (in the case of DMA write operations), it asserts both the IOR and signals
on the control bus. Asserting the IOR signal enables the disk controller to output the
byte of data from the disk on the data bus and asserting the MEMW signal enables
the addressed memory to accept data from the data bus. In this technique, data is
transferred directly from the disk controller to the memory location without passing
through the CPU or the DMA controller.

113
 DMA (Direct Memory Access)

When the data transfer is complete, the DMA controller unasserts the HOLD request
signal to the microprocessor and releases the bus by changing the switch position from
B to A. After getting the control of all buses the microprocessor executes the remaining
program.

Data Transfer Modes of DMA

The three data transfer modes of DMA controller are:
• Single Transfer Mode
• Block Transfer Mode
• Demand or Burst Transfer Mode

Single Transfer Mode

In this mode, the device can make only one transfer (byte or word). After each transfer,
DMAC gives the control of all buses to the processor. Due to this, the processor can have
access to the buses on a regular basis. It allows the DMAC to time share the buses with
the processor and hence this mode is most commonly used.
The operation of the DMA in a single transfer mode is as given below:
(1) I/O device asserts DRQ line when it is ready to transfer data
(2) The DMAC asserts HLDA line to request use of the buses from the processor
(3) The processor asserts HLDA, granting the control of buses to the DMAC
(4) The DMAC asserts DACK to the requesting I/O device and executes DMA bus cycle,
resulting data transfer
(5) I/O device deasserts its DRQ after data transfer of one byte or word
(6) DMA deasserts DACK line
(7) The word/byte transfer count is decremented and the memory address is
incremented
(8) The HOLD line is deasserted to give control of all buses back to the processor
(9) HOLD signal is reasserted to request the use of buses when I/O device is ready to
transfer another byte or word. The same process is then repeated until the last
transfer
(10) 10. When the transfer count is exhausted, the terminal count is generated to
indicate the end of the transfer

Block Transfer Mode

In this mode, the device can make a number of transfers as programmed in the word
count register. After each transfer, the word count is decremented by 1 and the address
is decremented or incremented by 1. The DMA transfer is continued until the word count
“rolls over” from zero to FFFFH and a Terminal Count (TC) or an external END of Process
EOP is encountered. Block transfer mode is used when the DMAC needs to transfer a
block of data.

114
 DMA (Direct Memory Access)

The operation of DMA in block transfer mode is as given below:

(1) I/O device asserts DRQ line when it is ready to transfer data
(2) The DMAC asserts HLDA line to request use of the buses from the microprocessor
(3) The microprocessor asserts HLDA, granting the control of buses to the DMAC
(4) The DMAC asserts DACK to the requesting I/O device and executes DMA bus cycle,
resulting data transfer
(5) I/O device deasserts its DRQ after data transfer of one byte or word
(6) DMA deasserts DACK line
(7) The word/byte transfer count is decremented and the memory address is
incremented
(8) When the transfer count is exhausted and the data transfer is not complete, the
DMAC waits for another DMA request from the I/O device, indicating that it has
another byte or word to transfer. When DMAC receives the DMA request, steps
through are repeated
(9) If the transfer count is not exhausted, the data transfer is complete then DMAC
deasserts the HOLD to tell the microprocessor that it no longer needs the buses
(10) Microprocessor then deasserts the HLDA signal to tell the DMAC that it has
resumed control of the buses

Demand or Burst Transfer Mode

In this mode the device is programmed to continue making transfers until a TC or
external EOP is encountered or until DREQ goes inactive.
The operation of DMA in demand transfer mode is as given below:
(1) I/O device asserts DRQ line when it is ready to transfer data
(2) The DMAC asserts HLDA line to request use of the buses from the microprocessor
(3) The microprocessor asserts HLDA, granting the control of buses to the DMAC
(4) The DMAC asserts DACK to the requesting I/O device and executes DMA bus cycle,
resulting in data transfer
(5) I/O device deasserts its DRQ after data transfer of one byte or word
(6) DMA deasserts DACK line
(7) The word/byte transfer count is decremented and the memory address is
incremented
(8) The DMAC continues to execute transfer cycles until the I/O device deasserts the
DRQ indicating its inability to continue delivering data. The DMAC deasserts the
HOLD Signal, giving the buses back to the microprocessor. It also deasserts DACK
(9) I/O device can re-initiate demand transfer by reasserting DRQ signal
(10) Transfer continues in this way until the transfer count has been exhausted

115
 DMA (Direct Memory Access)

The flowcharts summarized the three data transfer modes of DMA.

Start

Is No
I/O device
ready for data
transfer
?

Yes

DMA acquires the control of

buses from processor

Transfer one byte

DMA relinquishes control of

buses to processor

Is
terminal
No
count
exhausted
?

Yes

Stop

(a) Single Transfer

116
 DMA (Direct Memory Access)

Start

Is No
I/O device
ready for data
transfer
?

Yes

DMA acquires the control of

buses from processor

Transfer one byte

Is
terminal
No count
exhausted
?

Is Yes
No I/O device
ready for data DMA relinquishes control of
transfer buses to processor
?

Yes Stop

(b) Block Transfer

117
 DMA (Direct Memory Access)

Start

Is No
I/O device
ready for data
transfer
?

Yes

DMA acquires the control of

buses from processor

Transfer one byte

Is Is
I/O device terminal
Yes ready for data No count
transfer exhausted
? ?

No Yes

DMA relinquishes control of

buses to processor

Stop

(c) Demand Transfer

118
 DMA (Direct Memory Access)

DMA Controller 8237

(1) It has 4 identical channels which allow external devices to directly transfer
information to/ from the system memory
(2) It also allows memory-to-memory data transfer
(3) The 8237A is designed to be used in conjunction with an external 8-bit address
register such as the 8282. It contains four independent channels and can be
expanded to any number of channels by cascading additional controller chips
(4) Each channel has a full 64K address and word count capability
(5) DMA controllers 8237A, 8237A-4, 8237A-5 operate with 3 MHz, 4 MHz, and 5 M
respectively. The DMA controller 8237A-5 can transfer up to 1.6 Mbytes/second

PIN Diagram of 8237A

• Data Bus (DB0 − DB7):
These are bi-directional tri-state signals connected to the system data bus. When
the CPU is having control of the system bus it can read the contents of an address
register, status register, temporary register or a word count register and it can also
program control registers of the DMA controller through the data bus. During DMA
cycles these lines are used to send the most significant bytes of the address.

• Address Bus (A0 − A3 and A4 − A7):

The four least significant lines A0 − A3 are bi-directional tri-state signals. In the
idle cycle they are inputs and are used by the CPU to address the register to be
loaded or read. In the active cycle they output the lower 4 bits of the address for
DMA operation. A4 − A7 are unidirectional lines, provide 4-bits of address during DMA
service.

• Address Strobe (ADSTB): This signal is used to demultiplex higher byte address and
data using external latch

• Address Enable (AEN):

This active high signal enables the 8-bit latch containing the upper 8-address bits
onto the system address bus. AEN can also be used to disable other system bus
drivers during DMA transfers.

(
• Memory Read and Memory Write MEMR, MEMW : )
These are active low tri-state signals. The signal is used to access data from the
addressed memory location during a DMA read or memory-to-memory transfer and
signal is used to write data to the addressed memory location during DMA write or
memory-to-memory transfer.

119
 DMA (Direct Memory Access)

• I/O Read and I/O Write (IOR and IOW ):

These are active low bi-directional signals. During the idle cycle, these are input
control signals used by the CPU to read/write the control registers. In the active
cycle, IOR signal is used to access data from a peripheral and IOW signal is used to
load data to the peripheral.
• Chip Select:
This is an active low input, used to select the 8237A as an I/O device during the idle
cycle. This allows the CPU to communicate with 8237A.

• RESET:
This active high signal clears the command, status, request, and temporary
registers. It also clears the first flip-flop and sets the master register. After reset
the device is in the idle cycle.

• READY:
This input is used to extend the memory read and write pulses from the 8237A to
interface slow memories or I/O devices.

• HOLD Request and HRQ:

• Any valid DREQ causes 8237A to issue the HRQ. It is used for requesting CPU to get
the control of system bus.
• HOLD Acknowledge (HLDA): The active high Hold Acknowledge from the CPU
indicates that it has relinquished control of the system bus.
• DREQ3-DREQ3: These are used to indicate to the peripheral devices that the DMA
request is granted.

• End Of Process ( EOP ):

This is an active low bi-directional signal concern with the completion of DMA
service. The EOP output signal is activated at the end of DMA service. The 8237A
allows an external signal to terminate an active DMA service by polling low EOP
input.

120
 DMA (Direct Memory Access)

Block Diagram of 8237A

Control Logic: The 8273A contains three basic blocks of control logic.

EOP DECREMENTOR INC/DECREMENTOR

IO A0-A3
RESET TEMP WORD TEMP ADDRESS BUFFER
CS COUNT REG (16) REG (16)
READY
CLK TIMING 16 BIT BUS
AEN AND 16 BIT BUS
CONTROL READ BUFFER READ WRITE BUFFER OUTPUT
ADSTB A4-A7
BASE BASE CURRENT BASE BUFFER
MEMR
MEMW ADDRESS WORD ADDRESS WORD
IOR (16) COUNT (16) COUNT
IOW (16) (16)

A8-A15
COMMAND
CONTROL
WRITE READ
BUFFER BUFFER D0-D1

DREQ0- 4 COMMAND
PRIORITY IO
DREQ3 ENCODER (8) INTERNAL DATA BUS
BUFFER
HLDA AND
ROTATING MASK

DB0-DB7
HRQ (4)
4
PRIORITY
DACK0- LOGIC STATUS TEMPORARY
DACK3 REQUEST MODE (8) (8)
(4) (4 X 6)

Figure: Internal block diagram of 8237

(1) Timing Control Block: It generates internal timing and external control signals for
8237A by er: Point-to-TCP/IP, IP session
(2) Program Command Control Block: It decodes various commands given to the
microprocessor before servicing a DMA request. It also decodes the Mode Control
Word, which is used to select the type of DMA during the servicing
(3) Priority Encoder Block: It prioritizes between the DMA channels requesting service
simultaneously
(4) Internal Registers: The 8237A contains 344 bits internal memory in the form of
registers. The below table gives the name, size, and number of each register

121
 DMA (Direct Memory Access)

NAME SIZE NUMBER

Base address registers 16 bits 4

Base word count register 16 bits 4

Current address registers 16 bits 4

Current word count registers 16 bits 4

Temporary address registers 16 bits 1

Temporary word count registers 16 bits 1

Status registers 8 bits 1

Command registers 8 bits 1

Temporary registers 8 bits 1

Mode registers 6 bits 4

Mask registers 4 bits 1

Request registers 4 bits 1

122
 8086 Microprocessor

Chapter 8 – 8086 Microprocessor

Objective
Upon completion of this chapter, you will be able to understand:
• Features of 8086
• Architecture & PIN diagram of 8086
• Memory addressing in 8086

Introduction
The INTEL 8086 was the first 16-bit microprocessor. It was developed using HMOS (high
density short channel MOS) technology containing 29,000 transistors housed in 40 pin
DIP package. The 8086 does not have an internal clock circuit. The 8086 requires an
external asymmetric clock source with 33% duty cycle. In this chapter we will study the
features, architecture and addressing modes of 8086.

Features of 8086
(1) The 8086 is a 16-bit microprocessor. The term “16-bit” means that its arithmetic
logic unit, internal registers and most of its instructions are designed to work with
16-bit binary words
(2) The 8086 has a 16-bit data bus, so it can read data from or write data to memory
and I/O ports in either 16-bits or 8-bits at a time
(3) The 8086 has a 20-bit address bus, so it can directly access 220 or 1048576 (1 MB)
memory locations. Each of the 1048576 memory locations is byte (8-bit) wide.
Therefore, a sixteen-bit word is stored in two consecutive memory locations
(4) The 8086 can generate 16-bit I/O address, hence it can access 216 = 65536 I/O
ports
(5) The 8086 provides fourteen 16-bit registers
(6) The 8086 has multiplexed address and data bus which reduces the number of pins
needed, but does slow down the transfer of data (draw back)
(7) The 8086 requires one phase clock with a 33% duty cycle to provide optimized
internal timing as shown in the figure It requires 5 MHz clock range
(8) With 8086, it is possible to perform bit, byte, word and block operations. It
performs the arithmetic and logical operations on bit, byte, word and decimal
numbers including multiply and divide
(9) The Ințel 8086 is designed to operate in two modes, namely the minimum mode
and the maximum model. When only one 8086 microprocessor is to be used in a
microcomputer system, the 8086 is used in the minimum mode of operation. In
this mode, the microprocessor issues the control signal required by memory and
I/O devices. In multiprocessor (more than one processor in the system) systems,
the 8086 operates in maximum mode. In maximum mode, the control signals are
generated with the help of the internal bus controller (8288)

123
 8086 Microprocessor

TON TOFF

T/3 2T/3

(10) The Intel 8086 supports multiprogramming. In multiprogramming, the code for two
or more processes is stored in memory at the same time and is executed in a
time-multiplexed fashion
(11) An interesting feature of the 8086 is that it fetches up to six instruction bytes
from memory and queue stores them in order to speed up instruction execution

Architecture of 8086
The functional block diagram of the 8086 is shown in the below figure. The Architecture
of 8086 can be divided into two units. These are Bus Interface Unit (BIU) and Execution
Unit (EU). These two functional units can work simultaneously to increase system speed
and consequently the throughput. Throughput is a measure of instruction executed per
unit time.

Memory
Interface

BIU C-Bus

∑ 6
5 Instruction
B-bus 4 Stream
3 Byte
ES
CS 2 Queue
1
SS
DS
IP
Control
System

EU A-Bus

AH AL
BH BL Arithmetic
CH CL Logic Unit
DH DL
SP
BP
SI Operands
DI Flags

124
 8086 Microprocessor

BUS Interface Unit (BIU)

The bus interface unit is the 8086 interface to the outside world. It provides a full 16-bit
bidirectional data bus and a 20-bit address bus. The bus interface unit is responsible for
performing, all external bus operation as listed below.

Function of Bus Interface Unit

(1) It sends the address of the memory or I/O
(2) It fetches instructions from memory
(3) It reads data from port/memory
(4) It writes data into port/memory
(5) It supports instruction queuing
(6) It provides the address relocation facility
To implement these functions the BIU contains the instruction pointer, address summer
and bus control logic.

Instruction Queue
To speed up program execution, the BIU fetches six instruction bytes ahead of TIME
from the memory. These prefetched instruction bytes are held for the execution unit in
a group of registers called the queue. With the help of the queue it is possible to fetch
the next instruction when the current instruction is in execution. The BIU is fetching and
storing the instructions in the queue. The queue operates on the principle of first in first
out (FIFO). So that the execution unit gets the instructions for execution in the order in
which they are fetched. The size of the queue is 6 bytes in an 8086 processor. The BIU
fetches the instruction code from memory and stores it in the queue. The Execution Unit
(EU) fetches instruction codes from the queue for execution.

Execution Unit (EU)

Execution Unit Consists of the Following Function Units
(1) Control Circuitry and Instruction Decoders
(2) Arithmetic and Logic Unit (ALU)
(3) Flag Register
(4) General Purpose Registers
(5) Stack Point Register Data
(6) Pointer and Index Register
Execution Unit (EU) works in parallel with BIU and informs the BIU about the location
at which the next instruction or data is to be fetched, The phases of execution of the
instruction are fetch, decode, execute, and write. The fetch phase performs fetching of
the instruction from the instruction queue. The decode phase performs the decoding
of instructions. The execute phase perform-operations on the data. The write phase
performs the operation of storing the result at its destination.

125
 8086 Microprocessor

The Execution Unit is responsible for:

(1) The execution of all instructions
(2) Providing addresses to the BIU for fetching data/instruction and
(3) Manipulating various registers as well as the flag register

Control Circuitry and Instruction Decoder

Control circuit of the EU directs all the internal operations of the processor. The
instructions in the EU translate the instructions fetched from the memory into a series
of actions to be carried out by the execution unit.

Arithmetic and Logic Unit

Arithmetic and Logic Unit performs 8-bit or 16-bit mathematical operations such as
addition, subtraction, multiplication, division, data conversion and logical operations
like logical NOT, OR, and AND. It also performs register increment, decrement, and shift
operations.

Register Organisation of 8086

8086 has a set of registers known as general purpose and special purpose registers.
All of them are 16-bit registers. The general purpose registers can be used as either
8-bit registers or 16-bit registers They may be either used for holding data, variables
and intermediate results temporarily or other purposes like counter or for storing offset
address of some particular addressing modes, etc. The special purpose registers are used
as segment register pointers, index registers or as offset storage registers for particular
addressing modes.

General Data Registers

In the register organisation of 8086. The registers AX, BX, CX and DX are the general
purpose 16-bit registers. AX is used as 16-bit accumulator, with the lower 8-bits of AX
designated as AL and higher 8-bits as AH. AL can be used as an 8-bit accumulator for
8-bit operations. This is the most important general purpose register having multiple
functions.

SP
15 8 7 0

AX AH AL CS BP

BX BH BL DS SI

CX CH CL ES DI

DX DH DL SS IP

General Purpose Register Segment Register Pointer & Index Register

Figure: Register organisation of 8086

126
 8086 Microprocessor

Usually, the letters H and L specify the higher and lower bytes of a particular register. For
example, CH means the higher 8-bits of the CX register and CL means the lower 8-bits of
the CX register. The letter X is used to specify the complete 16-bit register. The register
CX is also used as a default counter case of string and loop instructions. The BX register
is used as an offset storage for forming physical addresses in case of certain addressing
modes. DX register is a general purpose register which is used as an implicit operand or
destination in case of a few instructions.

Segment Registers
The physical address of the 8086 is 20-bit wide to access 1-Mbyte location. However,
its registers memory locations which contain logical address are just 16-bits wide.
Here 8086 uses mem segmentation. It treats the 1-M byte of memory as divided into
segments, with a maximum size segment as 64 Kbytes. The 8086 allows only four active
segments. The 16 bit segment registers are provided within BIU or the 8086. These four
registers are:
(1) Code Segment (CS) Register
(2) Data Segment (DS) Register
(3) Stack Segment (SS) Register
(4) Extra Segment (ES) Register
These are used to hold the upper 16-bits of the starting addresses of the four memory
segments as shown in the figure on which the 8086 works at a particular time. For
example, the value in CS identifies the starting address of the 64-byte segment known
as code segment. By starting address we mean the lowest addressed byte in the active
code segment. The starting address is also known as base address or segment base.

Physical
address
FFFFFH
7 FFFFH Highest address

Top of extra segment

70000H 64 K
ES
Extra segment base
5FFFFH ES = 7000H
CS
Top of stack segment
64 K
SS 50000H
Stack segment base
SS = 5000H
DS 4489FH
Top of code segment
64 K
34BAOH Code segment base
CS = 348AH
2FFFFH Top of data segment
64 K

20000H Bottom of data segment

Figure: Memory Segment

127
 8086 Microprocessor

The BIU always inserts zeros for the lowest 4-bits (nibble) in the contents of the
segment register to generate 20-bit base address. For example, if the code segment
register contains 348AH, then segment will start at address 348AOH.

Function of Segment Registers

(1) The CS register holds the upper 16-bits of the starting address of the segment from
which BIU is currently fetching the instruction code byte
(2) The SS register is used for the upper 16-bits of the starting address for the program
stack (all stack related instructions will operate on stack)
(3) The ES register and DS register are used to hold the upper 16-bit of the starting
address of segments which are used for data

Instruction Pointer
The instruction pointer register holds the 16-bit address of the next code byte within the
code segment. The value contained in the IP is referred to as an offset. This value must
be offset from (added to) the segment base address in CS to produce the required 20-bit
physical address. The Instruction pointer is also called as the program counter in other
microprocessors.

Generation of 20-Bit Address

The contents of the CS register are multiplied by 16 i.e., shifted by 4 positions to the left
by inserting 4 zero bits and then the offset i.e., the contents of the IP register are added
to shifted contents of the CS to generate a physical address. As shown in the figure the
contents of the CS register are 348AH, therefore the shifted contents of the CS register
are 348A0H. When the BIU adds the offset of 4214H in the IP to this starting address, the
result is 20-bit physical of 38AB4H.

Top of code
segment 4489H

3 4 8 A 0
CS
IP +
4 2 1 4

Physical
3 8 A B 4
address
IP = 4214 H Code byte 38AB4H

CS = 348A H Start of code

segment 348A0 H

128
 8086 Microprocessor

Flag Register
A Flag is a flip-flop which indicates some condition produced by the execution of an
instruction or control certain operations of the EU. The flag register contains nine active
flags as shows in the Figure.
Six of them are used to indicate some conditions produced by instructions.

(1) Carry Flag (CF)

In the case of addition, this flag is set if there is a carry out of the MSB. The carry
flag also serves as a borrow flag for subtraction. In the case of subtraction, it is set
when borrow is needed.

(2) Parity Flag (PF)

It is set to 1 if the result of the byte operation or lower byte of the word operation
contains an even number of ones; otherwise, it is zero.

(3) Auxiliary Carry Flag

This flag is set if there is an overflow out of bit 3 i.e., carry from lower nibble to
higher nibble (D3 bit to D4 bit). This flag is used for BCD operations and it is not
available to the programmer.

(4) Zero Flag (ZF)

The zero flag sets if the result of the operation in the ALU is zero and the flag
resets if the result is non-zero.

(5) Sign Flag (SF)

After the execution of arithmetic or logical operations, if the MSB result is 1, the
sign bit is set. Sign bit 1 indicates that the result is negative; Otherwise, it is
positive.

(6) Overflow Flag (OF)

This flag is set if the result is out of range. For addition, this flag is set when there
is a carry into the MSB and no carry out of the MSB or vice-versa. For subtraction,
it is set when the MSB needs a borrow and there is no borrow from the MSB, or
vice-versa.

The Three Remaining Flags are Used to Control Certain Operations of the Processor
(1) Trap Flag (TF)
One way to debug a program is to run the program one instruction at a time and
see the contents of the used registers and memory variables after execution of
every instruction. This process is called single stepping through a program. Trap
Flag is used for single stepping through a program. If set, a trap is execution after
execution of each instruction, i.e., interrupt service routine is executed which
displays various registers and memory variable contents on the display after
execution of each instruction. Thus, a programmer can easily trace and correct

129
 8086 Microprocessor

errors in the program.

(2) Interrupt Flag (IF)

It is used to allow/prohibit the interruption of a program. If set, a certain type of
interrupt (a maskable interrupt) can be recognized by the 8086; otherwise, these
interrupts are ignored.

(3) Direction Flag (DF)

It is used with the string instruction. If DF = 0, the string is processed from its
beginning with the first element having the lowest address. Otherwise, the string
is processed from the high address towards the low address.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U U U U OF DF IF TF SF ZF U AF U PF U CF

Carry flag-set by
U = Undefined carry out of MSB
Parity flag-set if
result has even
parity

Auxiliary carry flag

for BCD
Zero flag-set if result = 0
Sign flag = MSB of result

Trap flag for single step

Interrupt enable flag

Direction flag for string

instruction

Overflow flag

8086 Flag Register Format

Pointers and Index Registers

All segment registers are 16-bit. But it is necessary to put a 20-bit address (physical
address) on the address bus. To get a 20-bit physical address one more register is
associated with each segment register the way IP is associated with CS.
These additional registers belong to the pointer and index group. The pointer and index
group consists of instruction pointer (IP), stack pointer (SP), Base pointer (BP), Source
Index (SI) and Destination Index (DI) registers.

130
 8086 Microprocessor

Stack Pointer (SP)

The stack pointer (SP) register contains the 16-bit offset from the start of the segment
to the top of stack. For stack operation, physical address is produced by adding the
contents of the Stack pointer register to the segment base address in SS. To do this, the
contents of the stack segment register are shifted four bits left and the contents of SP
are added to the shifted result. If the contents of SP are 9F20H and SS are 4000H, then
the physical address is calculated as shown in Figure.

End of stack segment 4FFFFH

Top of stack 49F20H

SP = 9F20 H
SS = 4000 H
Start of stack segment 40000H

Figure: Stack and stack pointer

SS 40000
+ SP 9F20
Physical address 49F20H

Base Pointer, Source Index and Destination Index

These three 16-bit registers can be used as general purpose registers. However, their
main use is to hold 16-bit offset of the data word in one of the segments.

Base Pointer: We can use the BP register instead of SP for accessing the stack using the
based addressing mode. In this case, the 20-bit physical stack address is calculated from
BP and SS.

Source Index: Source Index (SI) can be used to hold the offset of a data word in the data
segment. In this case, the 20-bit physical data address is calculated from SI and DS.

Destination Index: The ES register points to the extra segment in which data is stored.
Storing instruction always uses ES and DI to determine the 20-bit physical address for
destination.

131
 8086 Microprocessor

PIN Diagram of 8086

The 8086 can be operated in two modes: Minimum mode and maximum mode. The
below figure shows the PIN diagram of 8086.

MAX MIN MODE

MODE
GND 1 40 Ucc
AD 14 2 39 AD 15
AD 13 3 38 A16/S3
AD 12 4 37 A17/S4
AD 11 5 36 A18/S5
AD 10 6 35 A19/S6
AD 9 7 34 BHE/S7
AD 8 8 33 MN/MX
AD 7 9 32 RD
8086
AD 6 10 CPU 31 RQ/GT0 (HOLD)
AD 5 11 30 RQ/GT1 (HLDA)
AD 4 12 29 LOCK (WR)
AD 3 13 28 S2 (M/IO)
AD 2 14 27 S1 (DT/R)
AD 1 15 26 S0 (DEN)
AD 0 16 25 QS0 (ALE)
NMI 17 24 QS1 (INTA)
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET

Figure: PIN diagram of 8086

Memory Addressing in 8086

The 8086 microprocessor uses 20-bit address to access memory, With 20-bit address,
the processor can generate 220 = 1 mega-address. The basic memory word size of the
memory used in 8086 system is 8-bit or 1 byte. Hence the physical memory space of
8086 is 1 Mbytes (1 mega byte).
For the programmer, the 8086 memory address space is a sequence of one mega byte in
which one location stores an 8-bit data and two consecutive locations store 16-bit data.
But physically (i.e., in the hardware), the 1 Mb memory space is divided into two banks of
512 KB (512 KB + 512 KB = 1 MB). The two memory banks are called Even (or Lower) bank
and Odd (or Upper) bank. The organization of even and odd memory banks in 8086 based
systems is as shown in figure.
An 8086 based system will have two sets of memory ICs. One set for even bank and
other set for odd bank. The data lines D0 − D7 are connected to the even bank and the
data lines D8 − D15 are connected to the odd bank. The even memory bank is selected
by the address line A0 and the odd memory bank is selected by the control signal BHE.

132
 8086 Microprocessor

The memory banks are selected when these signals are low (active low). Any memory
location in the memory bank is selected by the address lines A1 to A19.
The organization of memory into two banks and providing bank select signals allows the
programmer to read/write the byte (8-bit) operand in any memory address through 16-bit
data bus. Also, it allows the programmer to read/write the word (16-bit) operand starting
from even address or odd address. There are four possible ways to access the data from
memory. The four ways are as listed below.
(1) 8-bit data from Even (Lower) address bank
(2) 8-bit data from Odd (Higher) address bank
(3) 16-bit data starting from Even address
(4) 16-bit data starting from odd address

Data bus

D8 - D15
Address

D0 - D7
bus

Address
8086 Latches

A1 - A19

A1 - A19
CPU
bus

Odd memory Even memory

bank ICs 512 bank ICs 512
(512 k x 8) (512 k x 8)
CS/EN CS/EN

BHE A0

Odd memory bank select signal Even memory bank select signal
1 MB memory
address space 512 KB odd memory 512 KB even memory
FFFFF H address space address space
FFFFE H FFFFF H FFFFE H
FFFFD H FFFFD H FFFFC H
FFFFD H FFFFB H FFFFA H
FFFF9 H FFFF8 H

⇒
00004 H
00003 H 00007 H 00006 H
00001 H 00005 H 00004 H
00001 H 00003 H 00002 H
00000 H 00001 H 00000 H

Figure: Organisation of Even and Odd memory bank in 8086 based system

133
 8086 Microprocessor

The 8-Bit Data from Lower/Even Address Bank

In this case to access memory bytes from the even address, information is transferred
over the lower half of the data bus (D0-D7) when A0 is active low and BHE is active and
high enabling only the even address bank. The below figure depicts the arrangement for
this method.

Odd Even

X+1 X
X+3 X+2
X+5 X+4

Address D8 - D15 D0 - D7

Data bus

BHE = 1 A0 = 0

Figure: 8 bit data access from lower/even address

Consider an example for loading a byte of data into CH register from the memory
location with an even address. Here, the data will be accessed from the even bank via
the (D0-D7) data bus. Even though this data is transferred into the 8086 over lower 8-bit
lines, the 8086 processor will automatically redirect the data to the higher 8-bit of its
internal 16-bit data path and hence to the CH-register. Such capability permits bytes to
do input-output transfer via the AL register to access I/O device connected to either the
upper half of the data bus or the lower half of the 16-bit data bus.

8-bit Data form Higher/Odd Address Bank

To access memory byte from an odd address, information is transferred over the higher
half of the data bus (D8 − D15). This odd memory bank is selected when BHE = 0 and
disabled when the even memory bank when A0 = 1. This segment is shown in figure
below.

134
 8086 Microprocessor

Odd Even

X+1 X
X+3 X+2

Address bus
A1 - A9 D8 - D15 D0 - D7

BHE = 0 A0 = 0

Figure: 8 bit data from odd address bank

16-bit Data Starting from Even Address

Hence, 16-bit data forms an even address and is accessed in a single bus cycle. The
address lines A1 − A19 select the appropriate byte within each bank. A0 is low and BHE is
low and this enables both banks simultaneously. This arrangement is shown in the below
figure.

Odd Even

X+1 X
X+3 X+2
X+5 X+4

D8 - D15 D0 - D7
Address bus
A1 - A9

Data bus

A0 = 0
BHE = 0
BHE = 0 and A0 = 0 ⇒ Both banks enabled

Figure:16-Bit Data Access Starting from Even Address

135
 8086 Microprocessor

16-Bit Data Access Starting from Odd Address

Here a 16-bit word located at an odd address (two consecutive bytes with least
significant byte at an odd byte address) is accessed using two bus cycles. For the first
bus cycle, the lower byte will be accessed. The arrangement with the odd address as
0003 is shown in figure(a) below. Now, during the second bus cycle, the upper byte [with
the even address 0004H as observed in figure (b)] will be accessed during the first bus
cycle. A1 − A19 address bus specifies the memory location and A0 is 1 and BHE is low. This
means that the even memory bank will be disabled and odd memory bank is enabled.
During the second bus cycle, the address is incremented. This means A0 is zero and
BHE is made high and the even memory bank is enabled and the odd memory bank is
disabled.

Odd bank Even bank Odd bank Even bank

0003 0004 0003 0004

0005 0006 0005 0006

Address A1-A19 Address

A1-A19
Data D0-D7 Data D0-D7
D8-D15 D8-D15

(a) First access from odd address (b) Next access from even address

136
8086 Microprocessor

137