MICROPROCESSOR

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 Microprocessor Basic Diagram

Instruction set
and Programming

Advance
Memory Interfacing Microprocessors
Eg
Microprocessor 80386,pentium
8086

8255 8257 8259

Peripheral Device Interfacing

 MODULE 2

The Intel Microprocessors 8086 Architecture

1.1 8086CPU Architecture,
1.2 Programmer’s Model
1.3 Functional Pin Diagram
1.4 Memory Segmentation
1.5 Banking in 8086
1.6 Demultiplexing of Address/Data bus
1.7 Functioning of 8086 in Minimum mode and Maximum mode
1.8 Timing diagrams for Read and Write operations in minimum and
maximum mode
1.9 Interrupt structure and its servicing

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 REVISION OF BASIC CONCEPTS

➢BASIC COMPUTER SYSTEM

➢MEMORY
➢Instruction Cycle
➢Fetch Concept understanding with
➢Decode respect to microprocessor

➢Execute
➢Why Hexa-decimal Number system ?
➢Power of 2
➢System Bus
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BASIC COMPUYTER SYSTEM

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 History of Microprocessors

8085

8086

80186

80286

80386

80486

80586 : P1,P2,P3..C2D,Ci7, Ci9

How 8086 processor looks like?

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 Introduction to 8086

➢Enhanced version of 8085 designed by Intel in 1976

➢It is 16 bit Microprocessor
➢It has a 20 bit address bus so can access upto 220 memory locations
➢16 bit data lines
➢64k I/O Ports
➢14, 16 bit Registers
➢It has powerful instruction set (multiplication & divisions)
➢It supports two modes of operations:
➢Minimum Mode : suitable for single processor
➢Maximum Mode : suitable for multiple processors
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 Features to 8086
➢It has instruction queue capable of storing 6 instructions bytes
from memory resulting in faster processing.
➢It was the first 16 bit processor having 16 bit ALU, 16 Bit
Registers, internal data bus resulting in faster processing
➢Available in 3 versions:
➢5MHz
➢8MHz
➢10 MHz
➢Two stages of pipelining : (Fetch +Execution)
➢Single phase clock with 33% duty cycle
➢ 256 vectored interrupts. Suvarna Bhat
 Comparison with 8085

Parameter 8085 8086

size 8 bit 16 bit
Address Bus 16 bit 20 bit
Memory 64KB 1MB
Instruction No Instruction Queue Instruction Queue of 6
instructions

Pipelining Does not support Supports 2 stages of

Pipelining

I/O 28 - 256 I/O’s 216 - 65,356 I/O’s

Cost Low High

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ARCHITECTURE OF 8086

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 Why 8086 has two parts?

8086 Architecture
Function :
1. Fetch the Instruction
Bus Interface Unit (BIU)
2. Calculate the physical address
3. Manage 6 byte instruction queue

Function:
Execution Unit
1. Execute the instruction
(EU)

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 BUS INTERFACE UNIT (BIU)

➢ It generates 20 bits of physical address for memory access.

➢ Fetch instruction from memory
➢ Transfer data to and from the memory and I/O
➢ Manages pipelining using 6 byte instruction queue

Main Components :
1. Segment Register
2. Address generation circuit
3. IP
4. Prefetch Queue

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Physical Address calculation

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 EXECUTION UNIT (EU)

➢ Decode and execute instructions

➢ Perform arithmetic logic and internal data transfer operation
➢ Send request signal to BIU to access the external module
➢ It operates with respect to ‘T states’ (clock cycle)

Main components :
1. General purpose register
2. Special purpose register
3. ALU
4. Operand
5. Flag register

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FLAG register

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Programmers model

• Software model
• All registers visible to the
programmer
• All GPR’s
• All Segment registers
• All off set registers (special
purpose reg)
• Flag registers

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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 PIN DIAGRAM

S6 : Indicates Whether 8086 is

in-charge or other processor in
S5 : Carries the status of ‘IF’ flag the configuration is in-charge of
the system bus. Low when 8086
is in charge of the system bus

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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PIN DIAGRAM

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 Memory Segmentation

• What is Segmentation ?
Segmentation is the process in which
the main memory of the computer is divided into
different segments/partitions and each
segment/partition has its own base address.

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 Memory Segmentation

Advantages of Segmentation
➢ With the help of memory segmentation we are able to work with registers having only 16-bits.
➢ The data and the code can be stored separately allowing for more flexibility.
➢ Also due to segmentation the logical address range is from 0000H to FFFFH, the code can be loaded at any
location in the memory.

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 Memory Banking

What is Memory Banking ?

• The memory address space is equally divided
into two parts(banks).
• One of the banks contain even addresses
called Even bank and the other contain odd
addresses called Odd bank.
• Even bank always stores lower byte so Even
bank is also called Lower bank(LB) and Odd
bank is also called a Higher bank(HB).

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 Memory Banking

• Why Memory Banking is Done in 8086 ?

8086 has 20-bit addressing model for memory access. Each address represents a single byte -
however, the natural word size of 8086 is 2 bytes (16-bit Data Bus), so you need a way to read two
bytes at the same time - hence, two banks. One bank has all the odd bytes, the other all the even
bytes in a word.

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 Memory BANKING

BHE A0 Operation

0 0 Read or Write 16 bit from both banks

0 1 Read or Write 8 bits from higher bank

1 0 Read or Write 8 bits from lower bank

1 1 No Operation (Processor is Idle)

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 Memory BANKING
e

Examples : 8bit operation on even bank

Eg. MOV BL, [2000H]
MOV BH, [2001H]
MOV BX, [2000H] (aligned operation)
MOV BX, [20001H] (misaligned operation)

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 8282-8bit(octal) Latch
e
1. 8282 is an 8-bit latch.
2. In 8086, the address bus is multiplexed with the data bus and status bits.
3. 8282 is used to latch the address from this bus.
4. The ALE signal is connected to STB of 8282.
5. When STB (ALE) is high, the input is latched and transferred to the output.
Hence address is latched.
6. When STB is low, the input is discarded. Hence, data is not latched. The
previously latched address remains at the output.
7. As totally 21 bits are to be latched (A19-A0, and BHE ), 3 latches are required,
each latch being 8 bit.

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 8286- 8bit data trans-receiver
e
1. 8286 is an 8-bit Trans-receiver.
2. It acts as a bi-directional buffer, and increases the driving capacity of the data
bus.
3. It is enabled when OE is low.
4. T controls the direction of data.
➢If T=1: data is transmitted.
➢If T=0: data is received.
5. As the data bus is 16 bits, 2 trans-receivers are required.
6. Its main function is to prevent address and allow data to be transferred on the
data bus.

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 8284 – clock generator
e

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MINIMUM MODE CONFIGURATION

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 MINIMUM MODE CONFIGURATION
What is Minimum Mode ?
• Programmed when MN/MX# is High

• Clock, Reset, Ready generated by 8284

• 8086 generates RD#, WR#, M/IO#, ALE, DEN#, DT/R#, HOLD, HLDA

• IOR#, IOW#, MEMR#, MEMWR# are generated with external decoder (74 LS 138)

• Single processor in the system and that is 8086, does not support additional

processors

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MINIMUM MODE CONFIGURATION
DEN DT/R Action
1 X Transreceiver is disabled
0 0 Receive data
0 1 Transmit data

M/IO RD WR Operation
1 0 1 Memory Read
1 1 0 Memory Write
0 0 1 I/O Read
0 1 0 I/O Write

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 MINIMUM MODE CONFIGURATION

Basic Terms Related to Timing Diagram

•T-State = 1/Clock Frequency

•Machine or Bus Cycle = Time to Execute One Read/Write Cycle

•Instruction Cycle = Total Time Required to Fetch and Execute one Instruction(Combination of Bus
Cycles)

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 MINIMUM MODE CONFIGURATION

Significance of Clock

•8086 Operates at 5MHz, 8MHz & 10MHz

•Read/Write Cycle in 8086 is of 4-Clock Cycles

•At 5Mhz, one T-State = 1/5MHz=200 nsec, So Read/Write Cycle =4 * 200=800 nsec

•At 8MHz, Read/Write Cycle = 4*125=500 nsec

•At 10MHz, Read/Write Cycle = 4*100=400 nsec

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MINIMUM MODE CONFIGURATION

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MINIMUM MODE CONFIGURATION

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MAXIMUM MODE CONFIGURATION

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 MAXIMUM MODE CONFIGURATION

1. MN/MX=0
2. We can connect more processors to 8086 (8087/8089)
3. Clock provide by 8284 clock generator
4. The most significant part of maximum mode circuit is the 8288 bus controller.
5. Address from the address bus is latched into 8282 8 bit latch.
1. Three latches are needed as address bus is 20 bit.
2. ALE is connected to STB of the latch
3. The ALE for this latch is given is given by 8288 bus controller.
6. The data bus is driven through 8286 8 bit transreceiver
1. Two transreciever is needed, as the data bus is 16 bit.
2. The transreciever are enabled through the DEN signal
3. The direction of the data is controlled by DT/R signal.
4. DEN is connected to OE and DT/R is connected to T
7. Control signals for all the operations are generated by decoding s2, s1 and s0 signals.

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 MAXIMUM MODE CONFIGURATION

DEN (of 8288) DT/R Action S2 S1 S0 Processor state

0 X Transeceiver is
disabled 0 0 0 Int Ack
1 0 Receive data
0 0 1 Read I/O port
1 1 Transmit data
0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Instruction Fetch

1 0 1 Memory Read

1 1 0 Memory Write

1 1 1 Inactive
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TIMING DIAGRAM

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TIMING DIAGRAM

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 8086 INTERRUPTS
➢An Interrupt is a special condition that arise during the working of the
microprocessor.
➢Microprocessor services it by executing a subroutine call Interrupt service
routine.
➢Every activity initiated through interrupt.
➢External signal (hardware interrupts)
➢ NMI (Vector interrupt)
➢ INTR
➢Special instructions (Software interrupts)
➢ INT ‘n’ Instructions

➢ 0 to 255
➢ All 256 interrupts can be invoked by software.
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8086 INTERRUPTS

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8086 INTERRUPTS

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 8086 INTERRUPTS

• The IVT contains ISR address for the 256 interrupts.

• Each ISR address is stored as CS and IP.
• As each ISR address is of 4 bytes (2–CS and 2-IP), each ISR address requires
4 locations to be stored.
• There are 256 interrupts: INT 0 … INT 255 the total size of the IVT is
256 x 4 = 1KB.
• The first 1KB of memory, address 00000 H … 003FF H, are reserved for the
IVT.
• Whenever an interrupt INT N occurs, μP does N x 4 to get values of IP and
CS from the IVT and
• hence perform the ISR.

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 8086 INTERRUPTS
• Dedicated Interrupts: (INT 0 … INT 4)
INT O (Divide Error)
• This interrupt occurs whenever there is division error
• i.e. when the result of a division is too large to be stored.
• This condition normally occurs when the divisor is very small as compared to the dividend or the
• divisor is zero.
• Its ISR address is stored at location 0 x 4 = 00000H in the IVT.

INT 1 (Single Step)

• The μP executes this interrupt after every instruction if the TF is set.
• It puts μP in Single Stepping Mode i.e. the μP pauses after executing every instruction.
• This is very useful during debugging.
• Its ISR generally displays contents of all registers.
• Its ISR address is stored at location 1 x 4 = 00004H in the IVT.
INT 2 (Non Maskable Interrupt)
• The μP executes this ISR in response to an interrupt on the NMI line.
• Its ISR address is stored at location 2 x 4 = 00008H in the IVT.

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 8086 INTERRUPTS
• Dedicated Interrupts: (INT 0 … INT 4)
INT 3 (Breakpoint Interrupt)
• This interrupt is used to cause Breakpoints in the program.
• It is caused by writing the instruction INT 03H or simply INT.
• It is useful in debugging large programs where Single Stepping is inefficient.
• Its ISR is used to display the contents of all registers on the screen.
• Its ISR address is stored at location 3 x 4 = 0000CH in the IVT.
INT 4 (Overflow Interrupt)
• This interrupt occurs if the Overflow Flag is set AND the μP executes the INTO instruction
• (Interrupt on overflow).
• It is used to detect overflow error in signed arithmetic operations.
• Its ISR address is stored at location 4 x 4 = 00010H in the IVT.

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 8086 INTERRUPTS
Reserved Interrupts: (INT 5 … INT 31)
. These levels are reserved by INTEL to be used in higher processors like 80386, Pentium etc. They
are not available to the user.
User defined Interrupts : (INT 32 … INT 255)
• These are user defined, software interrupts.
• ISRs for these interrupts are written by the users to service various user defined conditions.
• These interrupts are invoked by writing the instruction INT n.
• Its ISR address is obtained by the μP from location n x 4 in the IVT.

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 8086 INTERRUPTS
HARDWARE INTERRUPTS
NMI (Non Maskable Interrupt)
• This is a non-maskable, edge triggered, high priority interrupt.
• On receiving an interrupt on NMI line, the μP executes INT 2.
• μP obtains the ISR address from location 2 x 4 = 00008H from the IVT.
• It reads 4 locations starting from this address to get the values for IP and CS, to execute the ISR.
INTR
• This is a maskable, level triggered, low priority interrupt.
• On receiving an interrupt on INTR line, the μP executes 2 INTA pulses.
• 1st INTA pulse --- the interrupting device calculates (prepares to send) the vector number.
• 2nd INTA pulse --- the interrupting device sends the vector number “N” to the μP.
• Now μP multiplies N x 4 and goes to the corresponding location in the IVT to obtain the ISR address.
• INTR is a maskable interrupt.
• It is masked by making IF = 0 by software through CLI instruction.
• It is unmasked by making IF = 1 by software through STI instruction.

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 HOW 8086 RESPOND TO INTERRUPTS
Response to any interrupt --- INT N
i) The μP will PUSH Flag register into the Stack.
SS:[SP–1], SS:[SP-2] Flag --------SP SP – 2
ii) Clear IF and TF in the Flag register and thus disables INTR interrupt.
IF 0, TF 0
iii) PUSH CS into the Stack.
SS:[SP–1], SS:[SP-2] CS ----------SP – 2
iv) PUSH IP into the Stack.
SS:[SP–1], SS:[SP-2] IP-----------SP SP – 2
v) Load new IP from the IVT
IP [N x 4], [N x 4 + 1]
vi) Load new CS from the IVT
IP [N x 4 + 2], [N x 4 + 3]
Since CS and IP get new values, control shifts to the address of the ISR and the ISR thus begins. At the end of
the ISR the microprocessor encounters the IRET instruction and returns to the main program in the following
steps.

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 HOW 8086 RESPOND TO INTERRUPTS

Response to IRET instruction

i) The μP will restore IP from the stack
IP SS:[SP], SS:[SP+1]
SP SP + 2
ii) The μP will restore CS from the stack
CS SS:[SP], SS:[SP+1]
SP SP + 2
iii) The μP will restore FLAG register from the stack
Flag SS:[SP], SS:[SP+1]
SP SP + 2

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8086 INTERRUPTS

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 8086 INTERRUPTS

Priority in 8086 interrupts is of two types:

1. Simultaneous Occurrence:
• When more than one interrupts occur simultaneously then, all s/w interrupts except single
stepping, get the highest priority.
• This is followed by NMI. Next is INTR. Finally, the lowest priority is of the single stepping
interrupt.
• Eg: Assume the μP is executing a DIV instruction that causes a division error and
simultaneously INTR occurs.
• Here INT 0 (Division error) will be serviced first i.e. its ISR will be executed, as it has higher
priority, and then INTR will be serviced.
2. Ability to interrupt another ISR:
• Since software interrupts (INT N) are non-maskable, they can interrupt any ISR. NMI is also
non-maskable hence it can also interrupt any ISR.
• But INTR and Single stepping cannot interrupt another ISR as both are disabled before μP
enters an ISR by IF 0 and TF 0.

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