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Assignment

The document describes a UVM monitor class for a mini stream interface, detailing its construction, operational phases, and transaction capturing. Additionally, it outlines sequences and checkers for verifying FIFO status, including conditions for full and empty states, error handling, and functional coverage points. Key checks include monitoring FIFO behavior during transactions and validating packet sizes and sequences.

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kaushlesh sharma
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4 views3 pages

Assignment

The document describes a UVM monitor class for a mini stream interface, detailing its construction, operational phases, and transaction capturing. Additionally, it outlines sequences and checkers for verifying FIFO status, including conditions for full and empty states, error handling, and functional coverage points. Key checks include monitoring FIFO behavior during transactions and validating packet sizes and sequences.

Uploaded by

kaushlesh sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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class mini_stream_monitor extends uvm_monitor;

// Virtual interface

virtual interface min_strm_if;

// Analysis port for broadcast

uvm_analysis_port #(mini_stream_transaction) ap_mon;

function new(string name = "mini_stream_monitor", uvm_component parent = null);

super.new(name, parent);

ap_mon = new("ap_mon", this);

endfunction

// Build phase: fetch the interface from the configuration database

function void build_phase(uvm_phase phase);

super.build_phase(phase);

if (!uvm_config_db#(virtual min_strm_if)::get(this, "", "vif", min_strm_if)) begin

`uvm_fatal("Monitor", "Unable to get virtual interface")

end

endfunction

task run_phase(uvm_phase phase);

mini_stream_transaction tr;

forever begin

wait (vif.reset_n == 1);

@(posedge min_strm_if.MS_CLK);

wait (min_strm_if.MS_VALID && min_strm_if.MS_READY);


tr = mini_stream_transaction::type_id::create("tr", this);

tr.data = min_strm_if.MS_DATA;

if (min_strm_if.MS_EOP) begin

tr.eop = min_strm_if.MS_EOP;

end

`uvm_info(get_type_name(), $sformatf("Captured transaction: DATA=0x%0h, EOP=%0b", tr.data,


tr.eop), UVM_LOW)

ap_mon.write(tr);

end

endtask

////////////////Assignment 2///////////////////////////////////////////////

Sequences & Checkers for FIFO Status

To verify FIFO empty/full status, sequences should check below conditions:

- Fill FIFO completely and verify Fifo_full is asserted.

- Overload FIFO with an oversized packet, triggering error status.

- Drain FIFO to confirm proper assertion of Fifo_empty when empty.

- Interrupt transactions mid-sequence and check FIFO flag behavior post-recovery.

- Check for Ready deassertion for multiple time during transactions

Checkers:

- Fifo Full Condition: Monitor transaction count until the maximum limit, then ensure MS_READY = 0.

- Fifo Empty Condition: Verify that when all packets are drained, MS_READY = 1.

- Error Handling: Validate the sticky error clears when the register is read.
Functional Coverage Points verify:

- First packet after reset starts at 0.

- Subsequent packets show correct sequential increments.

- Packet Size Scenarios

- Smallest valid packets.

- Largest allowed packet (Max input packet size).

- Oversized packets triggering errors.

- Transitions between empty/full states.

- Behavior when near FIFO full condition.

- Stalling behavior when MS_READY = 0.

- Burst transaction injections.

- Unexpected sequence ordering tests.

- Compare Register read write

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